CYPRESS CY8C24X23A

CY8C21123, CY8C21223, CY8C21323
PSoC® Programmable System-on-Chip™
PSoC® Programmable System-on-Chip™
Features
■
■
■
■
Powerful Harvard-architecture processor:
❐ M8C processor speeds up to 24 MHz
❐ Low power at high speed
❐ Operating voltage: 2.4 V to 5.25 V
❐ Operating voltages down to 1.0 V using on-chip switch mode
pump (SMP)
❐ Industrial temperature range: –40 °C to +85 °C
Logic Block Diagram
®
Advanced peripherals (PSoC blocks):
❐ Four analog type “E” PSoC blocks provide:
• Two comparators with digital to analog converter (DAC)
references
• Single or dual 10-Bit 8-to-1 analog to digital converter
(ADC)
❐ Four digital PSoC blocks provide:
• 8- to 32-bit timers, counters, and pulse width modulators
(PWMs)
• CRC and PRS modules
❐ Full duplex UART, SPI™ master or slave: Connectable to all
general-purpose I/O (GPIO) pins
❐ Complex peripherals by combining blocks
Port 1
Complete development tools:
™
❐ Free development software (PSoC Designer )
❐ Full-featured, in-circuit emulator (ICE) and programmer
❐ Full-speed emulation
❐ Complex breakpoint structure
❐ 128-KB trace memory
■
Precision, programmable clocking:
❐ Internal ±2.5% 24- / 48-MHz main oscillator
❐ Internal low-speed, low-power oscillator for watchdog and
sleep functionality
Port 0
PSoC
CORE
SystemBus
Global Digital Interconnect
Global Analog Interconnect
SROM
SRAM
Flash
CPU Core
(M8C)
Interrupt
Controller
Sleep and
Watchdog
Clock Sources
(Includes IMO and ILO)
Flexible on-chip memory:
❐ 4 KB flash program storage 50,000 erase/write cycles
❐ 256 bytes SRAM data storage
❐ In-system serial programming (ISSP)
❐ Partial flash updates
❐ Flexible protection modes
❐ EEPROM emulation in flash
■
■
Additional system resources:
2
❐ I C master, slave and multi-master to 400 kHz
❐ Watchdog and sleep timers
❐ User-configurable low-voltage detection (LVD)
❐ Integrated supervisory circuit
❐ On-chip precision voltage reference
DIGITAL SYSTEM
Digital
PSoC Block
Array
Digital
Clocks
ANALOG SYSTEM
Analog
PSoC Block
Array
POR and LVD
I2C
System Resets
Sw itch
Mode
Pump
Analog
Ref.
Internal
Voltage
Ref.
SYSTEM RESOURCES
Programmable pin configurations:
❐ 25-mA sink, 10-mA source on all GPIOs
❐ Pull-up, pull-down, high Z, strong, or open-drain drive modes
on all GPIOs
❐ Up to eight analog inputs on all GPIOs
❐ Configurable interrupt on all GPIOs
Cypress Semiconductor Corporation
Document Number: 38-12022 Rev. *Q
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 1, 2011
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Contents
PSoC Functional Overview.............................................. 3
PSoC Core .................................................................. 3
Digital System ............................................................. 3
Analog System ............................................................ 4
Additional System Resources ..................................... 4
PSoC Device Characteristics ...................................... 5
Getting Started.................................................................. 5
Application Notes ........................................................ 5
Development Kits ........................................................ 5
Training ....................................................................... 5
CYPros Consultants .................................................... 5
Solutions Library.......................................................... 5
Technical Support ....................................................... 5
Development Tool Selection ........................................... 6
Software ...................................................................... 6
Designing with PSoC Designer ....................................... 7
Select Components ..................................................... 7
Configure Components ............................................... 7
Organize and Connect ................................................ 7
Generate, Verify, and Debug....................................... 7
Pin Information ................................................................. 8
8-Pin Part Pinout ....................................................... 8
16-Pin Part Pinout ...................................................... 8
20-Pin Part Pinout .................................................... 10
24-Pin Part Pinout .................................................... 11
Register Reference......................................................... 12
Register Conventions ................................................ 12
Register Mapping Tables .......................................... 12
Document Number: 38-12022 Rev. *Q
Electrical Specifications ................................................
Absolute Maximum Ratings.......................................
Operating Temperature ............................................
DC Electrical Characteristics.....................................
AC Electrical Characteristics .....................................
Packaging Information...................................................
Packaging Dimensions..............................................
Thermal Impedances ................................................
Solder Reflow Peak Temperature .............................
Ordering Information......................................................
Ordering Code Definitions ........................................
Acronyms ........................................................................
Acronyms Used .........................................................
Reference Documents....................................................
Document Conventions .................................................
Units of Measure .......................................................
Numeric Conventions ................................................
Glossary ..........................................................................
Document History Page .................................................
Sales, Solutions, and Legal Information ......................
Worldwide Sales and Design Support.......................
Products ....................................................................
PSoC Solutions .........................................................
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Page 2 of 43
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PSoC Functional Overview
The PSoC family consists of many programmable
system-on-chip controller devices. These devices are designed
to replace multiple traditional MCU-based system components
with a low cost single-chip programmable component. A PSoC
device includes configurable blocks of analog and digital logic,
and programmable interconnect. This architecture allows you to
create customized peripheral configurations, to match the
requirements of each individual application. Additionally, a fast
CPU, Flash program memory, SRAM data memory, and
configurable I/O are included in a range of convenient pinouts.
Digital System
The digital system consists of four digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8, 16, 24, and 32-bit peripherals, which
are called user modules. Digital peripheral configurations
include:
■
PWMs (8- to 32-bit)
■
PWMs with dead band (8- to 32-bit)
The PSoC architecture, as shown in Figure 1, consists of four
main areas: the Core, the System Resources, the Digital
System, and the Analog System. Configurable global bus
resources allow the combining of all device resources into a
complete custom system. Each PSoC device includes four digital
blocks. Depending on the PSoC package, up to two analog
comparators and up to 16 GPIO are also included. The GPIO
provide access to the global digital and analog interconnects.
■
Counters (8- to 32-bit)
■
Timers (8- to 32-bit)
■
UART 8-bit with selectable parity (up to two)
■
SPI master and slave
■
I2C slave, master, multi-master (one available as a system
resource)
PSoC Core
■
Cyclical redundancy checker/generator (8-bit)
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and internal main
oscillator (IMO), and internal low-speed oscillator (ILO). The
CPU core, called the M8C, is a powerful processor with speeds
up to 24 MHz. The M8C is a four MIPS 8-bit Harvard-architecture
microprocessor.
■
IrDA (up to two)
■
Pseudo random sequence generators (8- to 32-bit)
System Resources provide additional capability, such as digital
clocks or I2C functionality for implementing an I2C master, slave,
MultiMaster, an internal voltage reference that provides an
absolute value of 1.3 V to a number of PSoC subsystems, an
SMP that generates normal operating voltages off a single
battery cell, and various system resets supported by the M8C.
The digital system consists of an array of digital PSoC blocks,
which can be configured into any number of digital peripherals.
The digital blocks can be connected to the GPIO through a series
of global bus that can route any signal to any pin. This frees
designs from the constraints of a fixed peripheral controller.
The digital blocks can be connected to any GPIO through a
series of global bus that can route any signal to any pin. The
busses also allow for signal multiplexing and performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This provides an optimum
choice of system resources for your application. Family
resources are shown in Table 1 on page 5.
Figure 1. Digital System Block Diagram
Port 1
Port 0
To System Bus
DigitalClocks
FromCore
The analog system consists of four analog PSoC blocks,
supporting comparators and analog-to-digital conversion up to
10 bits of precision.
To Analog
System
DIGITAL SYSTEM
Row 0
DBB00
DBB01
DCB02
4
DCB03
4
8
8
8
8
GIE[7:0]
GIO[7:0]
Document Number: 38-12022 Rev. *Q
Row Output
Configuration
Row Input
Configuration
Digital PSoC Block Array
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
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Analog System
Additional System Resources
The analog system consists of four configurable blocks to allow
creation of complex analog signal flows. Analog peripherals are
very flexible and may be customized to support specific
application requirements. Some of the more common PSoC
analog functions (most available as user modules) are:
System resources, some of which listed in the previous sections,
provide additional capability useful to complete systems.
Additional resources include a switch mode pump, low voltage
detection, and power on reset. The merits of each system
resource are.
■
Analog-to-digital converters (single or dual, with 8-bit or 10-bit
resolution)
■
■
Pin-to-pin comparators (one)
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
■
Single-ended comparators (up to 2) with absolute (1.3 V)
reference or 8-bit DAC reference
■
■
1.3 V reference (as a system resource)
The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi-master modes are all
supported.
■
LVD interrupts can signal the application of falling voltage
levels, while the advanced POR (power on reset) circuit
eliminates the need for a system supervisor.
■
An internal 1.3 V voltage reference provides an absolute
reference for the analog system, including ADCs and DACs.
■
An integrated switch mode pump (SMP) generates normal
operating voltages from a single 1.2 V battery cell, providing a
low cost boost converter.
In most PSoC devices, analog blocks are provided in columns of
three, which includes one CT (continuous time) and two SC
(switched capacitor) blocks. The CY8C21x23 devices provide
limited functionality Type “E” analog blocks. Each column
contains one CT block and one SC block.
The number of blocks on the device family is listed in Table 1 on
page 5.
Figure 2. CY8C21x23 Analog System Block Diagram
Array Input
Configuration
ACI0[1:0]
ACI1[1:0]
ACOL1MUX
Array
ACE00
ACE01
ASE10
ASE11
Document Number: 38-12022 Rev. *Q
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PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks, and 12, 6, or 4
analog blocks. Table 1 lists the resources available for specific PSoC device groups. The PSoC device covered by this datasheet is
highlighted.
Table 1. PSoC Device Characteristics
PSoC Part
Number
Digital
I/O
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Outputs
Analog
Columns
Analog
Blocks
SRAM
Size
Flash
Size
CY8C29x66
up to 64
4
16
up to 12
4
4
12
2K
32 K
CY8C28xxx
up to 44
up to 3
up to 12
up to 44
up to 4
up to 6
up to
12 + 4[1]
1K
16 K
CY8C27x43
up to 44
2
8
up to 12
4
4
12
256
16 K
CY8C24x94
up to 56
1
4
up to 48
2
2
6
1K
16 K
CY8C24x23A
up to 24
1
4
up to 12
2
2
6
256
4K
CY8C23x33
up to 26
1
4
up to 12
2
2
4
256
8K
CY8C22x45
up to 38
2
8
up to 38
0
4
6[1]
1K
16 K
CY8C21x45
up to 24
1
4
up to 24
0
4
6[1]
512
8K
CY8C21x34
up to 28
1
4
up to 28
0
2
4[1]
512
8K
[1]
256
4K
CY8C21x23
up to 16
1
4
up to 8
0
2
CY8C20x34
up to 28
0
0
up to 28
0
0
3[1,2]
4
512
8K
CY8C20xx6
up to 36
0
0
up to 36
0
0
3[1,2]
up to
2K
up to
32 K
Getting Started
The quickest way to understand PSoC silicon is to read this
datasheet and then use the PSoC Designer Integrated Development Environment (IDE). This datasheet is an overview of the
PSoC integrated circuit and presents specific pin, register, and
electrical specifications.
For in depth information, along with detailed programming
details, see the Technical Reference Manual for this PSoC
device.
Training
Free PSoC technical training (on demand, webinars, and
workshops) is available online at http://www.cypress.com. The
training covers a wide variety of topics and skill levels to assist
you in your designs.
CYPros Consultants
For up to date ordering, packaging, and electrical specification
information, see the latest PSoC device datasheets on the web
at http://www.cypress.com.
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to http://www.cypress.com and refer to
CYPros Consultants.
Application Notes
Solutions Library
Application notes are an excellent introduction to the wide variety
of possible PSoC designs. They can be found at
http://www.cypress.com.
Visit our growing library of solution focused designs at
http://www.cypress.com. Here you can find various application
designs that include firmware and hardware design files that
enable you to complete your designs quickly.
Development Kits
PSoC Development Kits are available online from Cypress at
http://www.cypress.com and through a growing number of
regional and global distributors, which include Arrow, Avnet,
Digi-Key, Farnell, Future Electronics, and Newark.
Technical Support
For assistance with technical issues, search KnowledgeBase
articles and forums at http://www.cypress.com. If you cannot find
an answer to your question, call technical support at
1-800-541-4736.
Notes
1. Limited analog functionality.
2. Two analog blocks and one CapSense®.
Document Number: 38-12022 Rev. *Q
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Development Tool Selection
Software
PSoC Designer
At the core of the PSoC development software suite is
PSoC Designer. Utilized by thousands of PSoC developers, this
robust software has been facilitating PSoC designs for years.
PSoC Designer is available free of charge at
http://www.cypress.com. PSoC Designer comes with a free C
compiler.
PSoC Designer Software Subsystems
You choose a base device to work with and then select different
onboard analog and digital components called user modules that
use the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters. You configure the user modules
for your chosen application and connect them to each other and
to the proper pins. Then you generate your project. This prepopulates your project with APIs and libraries that you can use to
program your application.
The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration
allows for changing configurations at run time. Code Generation
Tools PSoC Designer supports multiple third-party C compilers
and assemblers. The code generation tools work seamlessly
within the PSoC Designer interface and have been tested with a
full range of debugging tools. The choice is yours.
Assemblers. The assemblers allow assembly code to be
merged seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices. The
optimizing C compilers provide all the features of C tailored to
the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Document Number: 38-12022 Rev. *Q
Debugger
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write I/O
registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
In-Circuit Emulator
A low cost, high functionality In-Circuit Emulator (ICE) is
available for development support. This hardware has the
capability to program single devices. The emulator consists of a
base unit that connects to the PC by way of a USB port. The base
unit is universal and operates with all PSoC devices. Emulation
pods for each device family are available separately. The
emulation pod takes the place of the PSoC device in the target
board and performs full speed (24MHz) operation.
Standard Cypress PSoC IDE tools are available for debugging
the CY8C20x36A/66A family of parts. However, the additional
trace length and a minimal ground plane in the Flex-Pod can
create noise problems that make it difficult to debug the design.
A custom bonded On-Chip Debug (OCD) device is available in a
48-pin QFN package. The OCD device is recommended for
debugging designs that have high current and/or high analog
accuracy requirements. The QFN package is compact and is
connected to the ICE through a high density connector.
PSoC Programmer
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer. PSoC Programmer software is
compatible with both PSoC ICE-Cube in-circuit emulator and
PSoC MiniProg. PSoC programmer is available free of charge at
http://www.cypress.com/psocprogrammer.
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Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
Organize and Connect
The PSoC development process can be summarized in the
following four steps:
1. Select User Modules
2. Configure User Modules
3. Organize and Connect
4. Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, you perform the "Generate
Configuration Files" step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system. The
generated code provides application programming interfaces
(APIs) with high-level functions to control and respond to
hardware events at run time and interrupt service routines that
you can adapt as needed.
Select Components
PSoC Designer provides a library of pre-built, pre-tested
hardware peripheral components called "user modules." User
modules make selecting and implementing peripheral devices,
both analog and digital, simple.
Configure Components
Each of the User Modules you select establishes the basic
register settings that implement the selected function. They also
provide parameters and properties that allow you to tailor their
precise configuration to your particular application. For example,
a PWM User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by
selecting values from drop-down menus. All the user modules
are documented in datasheets that may be viewed directly in
PSoC Designer or on the Cypress website. These user module
datasheets explain the internal operation of the User Module and
provide performance specifications. Each datasheet describes
the use of each user module parameter, and other information
you may need to successfully implement your design.
Document Number: 38-12022 Rev. *Q
You build signal chains at the chip level by interconnecting user
modules to each other and the I/O pins. You perform the
selection, configuration, and routing so that you have complete
control over all on-chip resources.
Generate, Verify, and Debug
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
The last step in the development process takes place inside
PSoC Designer's Debugger (access by clicking the Connect
icon). PSoC Designer downloads the HEX image to the ICE
where it runs at full speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition
to traditional single-step, run-to-breakpoint and watch-variable
features, the debug interface provides a large trace buffer and
allows you to define complex breakpoint events that include
monitoring address and data bus values, memory locations and
external signals.
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Pin Information
This section describes, lists, and illustrates the CY8C21x23 PSoC device pins and pinout configurations. Every port pin (labeled with
a “P”) is capable of Digital I/O. However, VSS, VDD, SMP, and XRES are not capable of Digital I/O.
8-Pin Part Pinout
Table 2. Pin Definitions – CY8C21123 8-Pin SOIC
Pin
No.
Type
Digital
Pin
Analog Name
Description
1
I/O
I
P0[5]
Analog column mux input
2
I/O
I
P0[3]
Analog column mux input
3
I/O
P1[1]
I2C serial clock (SCL), ISSP-SCLK[3]
VSS
Ground connection
P1[0]
I2C serial data (SDA), ISSP-SDATA[3]
4
Power
5
I/O
6
I/O
I
P0[2]
Analog column mux input
7
I/O
I
P0[4]
Analog column mux input
8
Power
VDD
Supply
LEGEND: A = Analog, I = Input, and O = Output.
Figure 3. CY8C21123 8-Pin SOIC
A, I, P0[5]
A, I, P0[3]
I2C SCL, P1[1]
1
VSS
4
8
2
7
SOIC
3
6
5
VDD
P0[4], A, I
P0[2], A, I
P1[0], I2C SDA
voltage
16-Pin Part Pinout
Table 3. Pin Definitions – CY8C21223 16-Pin SOIC
Pin
No.
Type
Digital
Pin
Analog Name
Description
1
I/O
I
P0[7]
Analog column mux input
2
I/O
I
P0[5]
Analog column mux input
3
I/O
I
P0[3]
Analog column mux input
4
I/O
I
P0[1]
Analog column mux input
SMP
SMP connection to required external
components
5
Power
6
7
Power
I/O
8
Power
VSS
Ground connection
P1[1]
I2C SCL, ISSP-SCLK[3]
VSS
Ground connection
I2C SDA, ISSP-SDATA[3]
9
I/O
P1[0]
10
I/O
P1[2]
11
I/O
P1[4]
Optional external clock input (EXTCLK)
12
I/O
I
P0[0]
Analog column mux input
13
I/O
I
P0[2]
Analog column mux input
14
I/O
I
P0[4]
Analog column mux input
15
I/O
I
P0[6]
Analog column mux input
VDD
Supply voltage
16
Power
Figure 4. CY8C21223 16-Pin SOIC
A, I, P0[7]
1
16
VDD
A, I, P0[5]
2
15
P0[6], A, I
A, I, P0[3]
3
14
P0[4], A, I
A, I, P0[1]
4
13
P0[2], A, I
SMP
5
12
P0[0], A, I
VSS
6
11
P1[4], EXTCLK
I2C SCL, P1[1]
7
10
P1[2]
VSS
8
9
SOIC
P1[0], I2C SDA
LEGEND A = Analog, I = Input, and O = Output.
Document Number: 38-12022 Rev. *Q
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Table 4. Pin Definitions – CY8C21223 16-Pin QFN with no E-Pad[3]
I
2
I/O
I
3
I/O
4
I/O
P1[5]
I2C SDA
5
I/O
P1[3]
6
I/O
P1[1]
I2C SCL, ISSP-SCLK[3]
VSS
Ground connection
I2C SDA, ISSP-SDATA[3]
7
Power
P0[3]
Analog column mux input
P0[1]
Analog column mux input
P1[7]
I2C SCL
8
I/O
P1[0]
9
I/O
P1[6]
10
I/O
11
12
Input
I/O
13
I
EXTCLK
XRES
Active high external reset with internal
pull-down
P0[4]
VREF
VDD
Supply voltage
14
I/O
I
P0[7]
Analog column mux input
15
I/O
I
P0[5]
Analog column mux input
NC
No connect
16
Power
P1[4]
NC
P0[5], AI
P0[7], AI
VDD
Analog
I/O
AI, P0[3]
AI, P0[1]
I2C SCL, P1[7]
I2C SDA, P1[5]
1
2
3
4
16
15
14
13
Digital
1
Figure 5. CY8C21223 16-Pin QFN
12
11
(Top View) 10
9
QFN
6
7
8
Description
5
Pin
Name
P1[3]
Type
I2C SCL, P1[1]
VSS
I2C SDA, P1[0]
Pin
No.
P0[4], VREF
XRES
P1[4]
P1[6]
LEGEND A = Analog, I = Input, and O = Output.
Notes
3. These are the ISSP pins, which are not high Z at POR (power on reset). See the PSoC Technical Reference Manual for details.
4. The center pad on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it
must be electrically floated and not connected to any other signal.
Document Number: 38-12022 Rev. *Q
Page 9 of 43
[+] Feedback
CY8C21123, CY8C21223, CY8C21323
20-Pin Part Pinout
Table 5. Pin Definitions – CY8C21323 20-Pin SSOP
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Type
Digital Analog
I/O
I
I/O
I
I/O
I
I/O
I
Power
I/O
I/O
I/O
I/O
Power
I/O
I/O
I/O
I/O
Input
I/O
I/O
I/O
I/O
I
I
I
I
Power
Pin
Name
P0[7]
P0[5]
P0[3]
P0[1]
VSS
P1[7]
P1[5]
P1[3]
P1[1]
VSS
P1[0]
P1[2]
P1[4]
P1[6]
XRES
P0[0]
P0[2]
P0[4]
P0[6]
VDD
Description
Analog column mux input
Analog column mux input
Analog column mux input
Analog column mux input
Ground connection
I2C SCL
I2C SDA
Figure 6. CY8C21323 20-Pin SSOP
A, I, P0[7]
1
20
VDD
A, I, P0[5]
2
19
P0[6], A, I
A, I, P0[3]
3
18
P0[4], A, I
A, I, P0[1]
4
17
P0[2], A, I
VSS
5
16
P0[0], A, I
I2C SCL, P1[7]
6
15
XRES
I2C SDA, P1[5]
7
14
P1[6]
P1[3]
8
13
P1[4], EXTCLK
I2C SCL, P1[1]
9
12
P1[2]
VSS
10
11
P1[0], I2C SDA
SSOP
I2C SCL, ISSP-SCLK[3]
Ground connection
I2C SDA, ISSP-SDATA[3]
Optional EXTCLK input
Active high external reset with internal
pull-down
Analog column mux input
Analog column mux input
Analog column mux input
Analog column mux input
Supply voltage
LEGEND A = Analog, I = Input, and O = Output.
Document Number: 38-12022 Rev. *Q
Page 10 of 43
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CY8C21123, CY8C21223, CY8C21323
24-Pin Part Pinout
Table 6. Pin Definitions – CY8C21323 24-Pin QFN[5]
15
16
17
18
19
20
21
22
23
24
Input
I/O
I/O
I/O
I/O
I
I
I
I
Power
Power
I/O
I/O
I/O
I
I
I
NC
P0[0]
P0[2]
P0[4]
P0[6]
VDD
VSS
P0[7]
P0[5]
P0[3]
P0[7], A, I
VSS
VDD
P0[6], A, I
20
19
P0[3], A, I
P0[5], A, I
18
17
QFN 16
(Top View) 15
14
13
11
12
Optional (EXTCLK) input
1
2
3
4
5
6
P1[2]
EXTCLK, P1[4]
Power
I/O
I/O
I/O
I/O
I2C SCL, ISSP-SCLK[3]
No connection
Ground connection
I2C SDA, ISSP-SDATA[3]
A, I, P0[1]
SMP
V SS
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
VSS
I2C SDA, P1[0]
VSS
P1[7]
P1[5]
P1[3]
P1[1]
NC
VSS
P1[0]
P1[2]
P1[4]
P1[6]
XRES
23
22
21
Power
I/O
I/O
I/O
I/O
Analog column mux input
SMP connection to required external
components
Ground connection
I2C SCL
I2C SDA
Figure 7. CY8C21323 24-Pin QFN
24
3
4
5
6
7
8
9
10
11
12
13
14
Description
7
8
9
10
1
2
Type
Pin
Digital Analog Name
I/O
I
P0[1]
Power
SMP
I2C SCL, P1[1]
NC
Pin
No.
P0[4], A, I
P0[2], A, I
P0[0], A, I
NC
XRES
P1[6]
Active high external reset with internal
pull-down
No connection
Analog column mux input
Analog column mux input
Analog column mux input
Analog column mux input
Supply voltage
Ground connection
Analog column mux input
Analog column mux input
Analog column mux input
LEGEND A = Analog, I = Input, and O = Output.
Note
5. The center pad on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it
must be electrically floated and not connected to any other signal.
Document Number: 38-12022 Rev. *Q
Page 11 of 43
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CY8C21123, CY8C21223, CY8C21323
Register Reference
This section lists the registers of the CY8C21x23 PSoC device.
For detailed register information, refer the PSoC Technical
Reference Manual.
Register Conventions
The register conventions specific to this section are listed in the
following table.
Table 7. Register Conventions
Convention
Register Mapping Tables
The PSoC device has a total register address space of
512 bytes. The register space is referred to as I/O space and is
divided into two banks. The XOI bit in the Flag register (CPU_F)
determines the bank you are currently in. When the XOI bit is set,
you are in Bank 1.
Note In the following register mapping tables, blank fields are
Reserved and must not be accessed.
Description
R
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
Document Number: 38-12022 Rev. *Q
Page 12 of 43
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CY8C21123, CY8C21223, CY8C21323
Table 8. Register Map Bank 0 Table: User Space
Name
Addr
(0,Hex)
Access
Name
Addr
(0,Hex)
Access
Name
Name
Access
00
RW
40
01
RW
41
81
C1
PRT0GS
02
RW
42
82
C2
PRT0DM2
03
RW
43
83
PRT1DR
04
RW
44
PRT1IE
05
RW
45
85
C5
PRT1GS
06
RW
46
86
C6
PRT1DM2
07
RW
47
87
C7
08
48
88
C8
09
49
89
C9
0A
4A
8A
CA
0B
4B
8B
CB
0C
4C
8C
CC
0D
4D
8D
CD
0E
4E
8E
CE
0F
4F
8F
CF
10
50
90
D0
11
51
91
D1
12
52
92
D2
13
53
93
D3
14
54
94
D4
15
55
95
16
56
96
I2C_CFG
D6
RW
17
57
97
I2C_SCR
D7
#
18
58
98
I2C_DR
D8
RW
19
59
99
I2C_MSCR
D9
#
1A
5A
9A
INT_CLR0
DA
RW
1B
5B
9B
INT_CLR1
DB
RW
1C
5C
9C
1D
5D
9D
INT_CLR3
DD
RW
1E
5E
9E
INT_MSK3
DE
RW
1F
5F
9F
60
RW
84
RW
Addr
(0,Hex)
PRT0IE
ASE11CR0
80
Access
PRT0DR
AMX_IN
ASE10CR0
Addr
(0,Hex)
C0
C3
RW
C4
D5
DC
DF
DBB00DR0
20
#
DBB00DR1
21
W
DBB00DR2
22
RW
DBB00CR0
23
#
DBB01DR0
24
#
DBB01DR1
25
W
DBB01DR2
26
RW
DBB01CR0
27
#
DCB02DR0
28
#
ADC0_CR
68
#
A8
E8
DCB02DR1
29
W
ADC1_CR
69
#
A9
E9
DCB02DR2
2A
RW
6A
AA
EA
DCB02CR0
2B
#
6B
AB
EB
DCB03DR0
2C
#
TMP_DR0
6C
RW
AC
EC
DCB03DR1
2D
W
TMP_DR1
6D
RW
AD
ED
DCB03DR2
2E
RW
TMP_DR2
6E
RW
AE
EE
DCB03CR0
2F
#
TMP_DR3
6F
RW
AF
EF
61
PWM_CR
62
RW
63
CMP_CR0
64
#
65
CMP_CR1
66
Document Number: 38-12022 Rev. *Q
INT_MSK0
E0
RW
A1
INT_MSK1
E1
RW
A2
INT_VC
E2
RC
A3
RES_WDT
E3
W
A4
E4
A5
RW
67
Blank fields are Reserved and must not be accessed.
A0
E5
A6
DEC_CR0
E6
RW
A7
DEC_CR1
E7
RW
# Access is bit specific.
Page 13 of 43
[+] Feedback
CY8C21123, CY8C21223, CY8C21323
Table 8. Register Map Bank 0 Table: User Space (continued)
Name
Addr
(0,Hex)
Access
Name
Addr
(0,Hex)
Access
Name
Addr
(0,Hex)
Access
Name
Addr
(0,Hex)
30
70
RDI0RI
B0
RW
F0
31
71
RDI0SYN
B1
RW
F1
32
ACE00CR1
72
RW
RDI0IS
B2
RW
F2
33
ACE00CR2
73
RW
RDI0LT0
B3
RW
F3
34
74
RDI0LT1
B4
RW
F4
35
75
RDI0RO0
B5
RW
F5
RDI0RO1
B6
RW
36
ACE01CR1
76
RW
37
ACE01CR2
77
RW
B7
Access
F6
CPU_F
F7
RL
38
78
B8
F8
39
79
B9
F9
3A
7A
BA
FA
3B
7B
BB
FB
3C
7C
BC
FC
3D
7D
BD
3E
7E
BE
CPU_SCR1
FE
#
3F
7F
BF
CPU_SCR0
FF
#
Blank fields are Reserved and must not be accessed.
FD
# Access is bit specific.
Table 9. Register Map Bank 1 Table: Configuration Space
Name
Addr
(1,Hex)
Access
Name
Addr
(1,Hex)
Access
Name
Name
Access
00
RW
40
01
RW
41
81
C1
PRT0IC0
02
RW
42
82
C2
PRT0IC1
03
RW
43
83
PRT1DM0
04
RW
44
PRT1DM1
05
RW
45
85
C5
PRT1IC0
06
RW
46
86
C6
PRT1IC1
07
RW
47
87
C7
08
48
88
C8
09
49
89
C9
0A
4A
8A
CA
0B
4B
8B
CB
0C
4C
8C
CC
0D
4D
8D
CD
0E
4E
8E
CE
0F
4F
8F
10
50
90
GDI_O_IN
D0
RW
11
51
91
GDI_E_IN
D1
RW
12
52
92
GDI_O_OU
D2
RW
13
53
93
GDI_E_OU
D3
RW
14
54
94
D4
15
55
95
D5
16
56
96
D6
17
57
97
D7
18
58
98
D8
19
59
99
D9
1A
5A
9A
DA
1B
5B
9B
DB
Document Number: 38-12022 Rev. *Q
84
RW
Addr
(1,Hex)
PRT0DM1
ASE11CR0
80
Access
PRT0DM0
Blank fields are Reserved and must not be accessed.
ASE10CR0
Addr
(1,Hex)
C0
C3
RW
C4
CF
# Access is bit specific.
Page 14 of 43
[+] Feedback
CY8C21123, CY8C21223, CY8C21323
Table 9. Register Map Bank 1 Table: Configuration Space (continued)
Name
Addr
(1,Hex)
Access
Name
Addr
(1,Hex)
Access
Name
Addr
(1,Hex)
Access
Name
Addr
(1,Hex)
Access
1C
5C
9C
1D
5D
9D
OSC_GO_EN
DC
DD
RW
1E
5E
9E
OSC_CR4
DE
RW
1F
5F
9F
OSC_CR3
DF
RW
DBB00FN
20
RW
CLK_CR0
60
RW
A0
OSC_CR0
E0
RW
DBB00IN
21
RW
CLK_CR1
61
RW
A1
OSC_CR1
E1
RW
DBB00OU
22
RW
ABF_CR0
62
RW
A2
OSC_CR2
E2
RW
AMD_CR0
63
RW
A3
VLT_CR
E3
RW
CMP_GO_EN
64
RW
A4
VLT_CMP
E4
R
A5
ADC0_TR
E5
RW
ADC1_TR
E6
RW
23
DBB01FN
24
RW
DBB01IN
25
RW
DBB01OU
26
RW
27
65
AMD_CR1
66
RW
A6
ALT_CR0
67
RW
A7
E7
DCB02FN
28
RW
68
A8
IMO_TR
E8
W
DCB02IN
29
RW
69
A9
ILO_TR
E9
W
2A
RW
DCB02OU
2B
AA
BDG_TR
EA
RW
CLK_CR3
6A
6B
RW
AB
ECO_TR
EB
W
DCB03FN
2C
RW
TMP_DR0
6C
RW
AC
EC
DCB03IN
2D
RW
TMP_DR1
6D
RW
AD
ED
DCB03OU
2E
RW
TMP_DR2
6E
RW
AE
EE
TMP_DR3
6F
RW
AF
2F
EF
30
70
RDI0RI
B0
RW
F0
31
71
RDI0SYN
B1
RW
F1
32
ACE00CR1
72
RW
RDI0IS
B2
RW
F2
33
ACE00CR2
73
RW
RDI0LT0
B3
RW
F3
34
74
RDI0LT1
B4
RW
F4
35
75
RDI0RO0
B5
RW
F5
RDI0RO1
B6
RW
36
ACE01CR1
76
RW
37
ACE01CR2
77
RW
B7
F6
CPU_F
F7
RL
38
78
B8
39
79
B9
3A
7A
BA
3B
7B
BB
FB
3C
7C
BC
FC
3D
7D
BD
3E
7E
BE
CPU_SCR1
FE
#
3F
7F
BF
CPU_SCR0
FF
#
Blank fields are Reserved and must not be accessed.
Document Number: 38-12022 Rev. *Q
F8
F9
FLS_PR1
FA
RW
FD
# Access is bit specific.
Page 15 of 43
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CY8C21123, CY8C21223, CY8C21323
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C21x23 PSoC device. For up to date electrical specifications,
check if you have the latest datasheet by visiting the web at http://www.cypress.com.
Specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted.
Refer to Table 24 on page 25 for the electrical specifications on the IMO using SLIMO mode.
5.25
SLIMO Mode = 0
Figure 11. Voltage versus IMO Frequency
Figure 10. Voltage versus CPU Frequency
5.25
SLIMO
Mode=1
4.75
Vdd Voltage
Vdd Voltage
lid ng
Va rati n
e io
Op Reg
4.75
3.60
3.00
3.00
2.40
2.40
93 kHz
12 MHz
3 MHz
24 MHz
SLIMO
Mode=0
SLIMO
SLIMO
Mode=1
Mode=0
SLIMO SLIMO
Mode=1 Mode=1
6 MHz
93 kHz
12 MHz
24 MHz
IMO Frequency
CPU Frequency
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Table 10. Absolute Maximum Ratings
Symbol
TSTG
Description
Storage temperature
TBAKETEMP
Bake temperature
tBAKETIME
Bake time
TA
VDD
VIO
VIOZ
IMIO
ESD
LU
Ambient temperature with power applied
Supply voltage on VDD relative to VSS
DC input voltage
DC voltage applied to tristate
Maximum current into any port pin
Electro static discharge voltage
Latch-up current
Document Number: 38-12022 Rev. *Q
Min
–55
Typ
–
Max
+100
Units
°C
–
125
°C
See
package
label
–40
–0.5
VSS – 0.5
VSS – 0.5
–25
2000
–
–
See
package
label
72
Hours
–
–
–
–
–
–
–
+85
+6.0
VDD + 0.5
VDD + 0.5
+50
–
200
°C
V
V
V
mA
V
mA
Notes
Higher storage temperatures
reduce data retention time.
Recommended storage
temperature is +25 °C ± 25 °C.
Extended duration storage
temperatures higher than 65 °C
degrade reliability.
Human body model ESD
Page 16 of 43
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CY8C21123, CY8C21223, CY8C21323
Operating Temperature
Table 11. Operating Temperature
Symbol
TA
TJ
Description
Ambient temperature
Junction temperature
Min
–40
–40
Typ
–
–
Max
+85
+100
Units
°C
°C
Notes
The temperature rise from
ambient to junction is package
specific. SeeTable 36 on page
34. You must limit the power
consumption to comply with this
requirement.
DC Electrical Characteristics
DC Chip-Level Specifications
Table 12 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C ≤ TA ≤ 85 °C, 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, or 2.4 V to 3.0 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 12. DC Chip-Level Specifications
Symbol
Description
VDD
Supply voltage
Min
2.40
Typ
–
Max
5.25
Units
Notes
V
See DC POR and LVD
specifications,
Table 19 on page 21.
mA Conditions are VDD = 5.0 V,
25 °C, CPU = 3 MHz, SYSCLK
doubler disabled. VC1 = 1.5 MHz
VC2 = 93.75 kHz
VC3 = 0.366 kHz
mA Conditions are VDD = 3.3 V,
25 °C, CPU = 3 MHz, clock doubler
disabled. VC1 = 375 kHz
VC2 = 23.4 kHz
VC3 = 0.091 kHz
mA Conditions are VDD = 2.55 V,
25 °C, CPU = 3 MHz, clock doubler
disabled. VC1 = 375 kHz VC2 =
23.4 kHz
VC3 = 0.091 kHz
µA
VDD = 2.55 V, 0 °C to 40 °C
IDD
Supply current, IMO = 24 MHz
–
3
4
IDD3
Supply current, IMO = 6 MHz
–
1.2
2
IDD27
Supply current, IMO = 6 MHz
–
1.1
1.5
ISB27
–
2.6
4
–
2.8
5
µA
VDD = 3.3 V, –40 °C ≤ TA ≤ 85 °C
VREF
Sleep (mode) current with POR, LVD, sleep
timer, WDT, and internal slow
oscillator active. Mid temperature range.
Sleep (mode) current with POR, LVD, sleep
timer, WDT, and internal slow
oscillator active.
Reference voltage (bandgap)
1.28
1.30
1.32
V
VREF27
Reference voltage (bandgap)
1.16
1.30
1.330
V
Trimmed for appropriate VDD. VDD
= 3.0 V to 5.25 V
Trimmed for appropriate VDD. VDD
= 2.4 V to 3.0 V
AGND
Analog ground
VREF – 0.003
VREF
VREF + 0.003
V
ISB
Document Number: 38-12022 Rev. *Q
Page 17 of 43
[+] Feedback
CY8C21123, CY8C21223, CY8C21323
DC GPIO Specifications
Table 13 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C ≤ TA ≤ 85 °C, 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C
and are for design guidance only.
Table 13. 5-V and 3.3-V DC GPIO Specifications
Symbol
Description
Pull-up resistor
RPU
Pull-down resistor
RPD
High output level
VOH
Min
4
4
VDD – 1.0
Typ
5.6
5.6
–
Max
8
8
–
VOL
Low output level
–
–
0.75
IOH
High level source current
10
–
–
IOL
Low level sink current
25
–
–
VIL
VIH
VH
IIL
CIN
Input low level
Input high level
Input hysteresis
Input leakage (absolute value)
Capacitive load on pins as input
–
2.1
–
–
–
–
–
60
1
3.5
0.8
COUT
Capacitive load on pins as output
–
3.5
10
–
–
10
Units
Notes
kΩ
kΩ
V
IOH = 10 mA, VDD = 4.75 to 5.25 V (8 total
loads, 4 on even port pins (for example,
P0[2], P1[4]), 4 on odd port pins (for
example, P0[3], P1[5])).
80 mA maximum combined IOH budget.
V
IOL = 25 mA, VDD = 4.75 to 5.25 V (8 total
loads, 4 on even port pins (for example,
P0[2], P1[4]), 4 on odd port pins (for
example, P0[3], P1[5])).
150 mA maximum combined IOL budget.
mA VOH = VDD – 1.0 V, see the limitations of the
total current in the note for VOH
mA VOL = 0.75 V, see the limitations of the total
current in the note for VOL
V
VDD = 3.0 to 5.25
V
VDD = 3.0 to 5.25
mV
nA
Gross tested to 1 µA
pF
Package and pin dependent.
Temp = 25 °C
pF
Package and pin dependent.
Temp = 25 °C
Table 14 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4 V to 3.0 V and
–40 °C ≤ TA ≤ 85 °C. Typical parameters apply to 2.7 V at 25 °C and are for design guidance only.
Table 14. 2.7-V DC GPIO Specifications
Symbol
Description
Pull-up resistor
RPU
Pull-down resistor
RPD
High output level
VOH
Min
4
4
VDD – 0.4
Typ
5.6
5.6
–
Max
8
8
–
Units
kΩ
kΩ
V
VOL
Low output level
–
–
0.75
V
IOH
High level source current
2.5
–
–
mA
IOL
Low level sink current
10
–
–
mA
VIL
VIH
VH
IIL
CIN
Input low level
Input high level
Input hysteresis
Input leakage (absolute value)
Capacitive load on pins as input
–
2.0
–
–
–
–
–
60
1
3.5
0.75
–
–
–
10
V
V
mV
nA
pF
COUT
Capacitive load on pins as output
–
3.5
10
pF
Document Number: 38-12022 Rev. *Q
Notes
IOH = 2.5 mA (6.25 Typ), VDD = 2.4 to
3.0 V (16 mA maximum, 50 mA Typ
combined IOH budget).
IOL = 10 mA, VDD = 2.4 to 3.0 V (90 mA
maximum combined IOL budget).
VOH = VDD – 0.4 V, see the limitations of the
total current in the note for VOH
VOL = 0.75 V, see the limitations of the total
current in the note for VOL
VDD = 2.4 to 3.0
VDD = 2.4 to 3.0
Gross tested to 1 µA
Package and pin dependent.
Temp = 25 °C
Package and pin dependent.
Temp = 25 °C
Page 18 of 43
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CY8C21123, CY8C21223, CY8C21323
DC Amplifier Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C ≤ TA ≤ 85 °C, 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, or 2.4 V to 3.0 V and –40 °C ≤ TA ≤ 85 °C, respectively.
Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 15. 5-V DC Amplifier Specifications
Symbol
VOSOA
Description
Input offset voltage (absolute value)
Min
Typ
Max
Units
–
2.5
15
mV
Notes
TCVOSOA Average input offset voltage drift
–
10
–
µV/°C
IEBOA
Input leakage current (port 0 analog pins)
–
200
–
pA
Gross tested to 1 µA
CINOA
Input capacitance (port 0 analog pins)
–
4.5
9.5
pF
Package and pin dependent.
Temp = 25 °C
VCMOA
Common mode voltage range
0.0
–
VDD – 1
V
GOLOA
Open loop gain
80
–
–
dB
ISOA
Amplifier supply current
–
10
30
µA
Min
Typ
Max
Units
–
2.5
15
mV
–
10
–
µV/°C
Table 16. 3.3-V DC Amplifier Specifications
Symbol
VOSOA
Description
Input offset voltage (absolute value)
TCVOSOA Average input offset voltage drift
Notes
IEBOA
Input leakage current (port 0 analog pins)
–
200
–
pA
Gross tested to 1 µA
CINOA
Input capacitance (port 0 analog pins)
–
4.5
9.5
pF
Package and pin dependent.
Temp = 25 °C
VCMOA
Common mode voltage range
0
–
VDD – 1
V
GOLOA
Open loop gain
80
–
–
dB
ISOA
Amplifier supply current
–
10
30
µA
Min
Typ
Max
Units
–
2.5
15
mV
Table 17. 2.7V DC Amplifier Specifications
Symbol
VOSOA
Description
Input offset voltage (absolute value)
Notes
TCVOSOA Average input offset voltage drift
–
10
–
µV/°C
IEBOA
Input leakage current (port 0 analog pins)
–
200
–
pA
Gross tested to 1 µA
CINOA
Input capacitance (port 0 analog pins)
–
4.5
9.5
pF
Package and pin dependent.
Temp = 25 °C
VCMOA
Common mode voltage range
0
–
VDD – 1
V
GOLOA
Open loop gain
80
–
–
dB
ISOA
Amplifier supply current
–
10
30
µA
Document Number: 38-12022 Rev. *Q
Page 19 of 43
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DC Switch Mode Pump Specifications
Table 18 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C ≤ TA ≤ 85 °C, 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, or 2.4 V to 3.0 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 18. DC Switch Mode Pump (SMP) Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
VPUMP5V
5 V output voltage from pump
4.75
5.0
5.25
V
Configuration of footnote.[6] Average,
neglecting ripple. SMP trip voltage is set to
5.0 V.
VPUMP3V
3.3 V output voltage from pump
3.00
3.25
3.60
V
Configuration of footnote.[6] Average,
neglecting ripple. SMP trip voltage is set to
3.25 V.
VPUMP2V
2.6 V output voltage from pump
2.45
2.55
2.80
V
Configuration of footnote.[6] Average,
neglecting ripple. SMP trip voltage is set to
2.55 V.
IPUMP
Available output current
VBAT = 1.8 V, VPUMP = 5.0 V
VBAT = 1.5 V, VPUMP = 3.25 V
VBAT = 1.3 V, VPUMP = 2.55 V
5
8
8
–
–
–
–
–
–
mA
mA
mA
Configuration of footnote.[6]
SMP trip voltage is set to 5.0 V.
SMP trip voltage is set to 3.25 V.
SMP trip voltage is set to 2.55 V.
VBAT5V
Input voltage range from battery
1.8
–
5.0
V
Configuration of footnote.[6] SMP trip
voltage is set to 5.0 V.
VBAT3V
Input voltage range from battery
1.0
–
3.3
V
Configuration of footnote.[6] SMP trip
voltage is set to 3.25 V.
VBAT2V
Input voltage range from battery
1.0
–
2.8
V
Configuration of footnote.[6] SMP trip
voltage is set to 2.55 V.
VBATSTART
Minimum input voltage from battery to start
pump
1.2
–
–
V
Configuration of footnote.[6] 0 °C ≤ TA ≤
100. 1.25 V at TA = –40 °C.
ΔVPUMP_Line
Line regulation (over Vi range)
–
5
–
%VO Configuration of footnote.[6] VO is the “VDD
Value for PUMP Trip” specified by the
VM[2:0] setting in the DC POR and LVD
Specification, Table 19 on page 21.
ΔVPUMP_Load
Load regulation
–
5
–
%VO Configuration of footnote.[6] VO is the “VDD
Value for PUMP Trip” specified by the
VM[2:0] setting in the DC POR and LVD
Specification, Table 19 on page 21.
ΔVPUMP_Ripple
Output voltage ripple (depends on cap/load)
–
100
–
mVpp Configuration of footnote.[6] Load is
5 mA.
E3
Efficiency
35
50
–
%
Configuration of footnote.[6] Load is
5 mA. SMP trip voltage is set to 3.25 V.
E2
Efficiency
35
80
–
%
For I load = 1 mA, VPUMP = 2.55 V,
VBAT = 1.3 V, 10 uH inductor, 1 uF
capacitor, and Schottky diode.
FPUMP
Switching frequency
–
1.3
–
MHz
DCPUMP
Switching duty cycle
–
50
–
%
Note
6. L1 = 2 mH inductor, C1 = 10 mF capacitor, D1 = Schottky diode. Refer to Figure 12 on page 21.
Document Number: 38-12022 Rev. *Q
Page 20 of 43
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Figure 12. Basic Switch Mode Pump Circuit
D1
Vdd
V
DD
L1
V BAT
+
V PUMP
C1
SMP
Battery
PSoCTM
V ss
DC POR and LVD Specifications
Table 19 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C ≤ TA ≤ 85 °C, 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, or 2.4 V to 3.0 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 19. DC POR and LVD Specifications
Symbol
Description
VPPOR0
VPPOR1
VPPOR2
VDD value for PPOR trip
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
VPUMP0
VPUMP1
VPUMP2
VPUMP3
VPUMP4
VPUMP5
VPUMP6
VPUMP7
Min
Typ
Max
Units
–
–
–
2.36
2.82
4.55
2.40
2.95
4.70
V
V
V
VDD value for LVD trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.40
2.85
2.95
3.06
4.37
4.50
4.62
4.71
2.45
2.92
3.02
3.13
4.48
4.64
4.73
4.81
2.51[7]
2.99[8]
3.09
3.20
4.55
4.75
4.83
4.95
V
V
V
V
V
V
V
V
VDD value for PUMP trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.45
2.96
3.03
3.18
4.54
4.62
4.71
4.89
2.55
3.02
3.10
3.25
4.64
4.73
4.82
5.00
2.62[9]
3.09
3.16
3.32[10]
4.74
4.83
4.92
5.12
V
V
V
V
V
V
V
V
Notes
VDD must be greater than or equal to
2.5 V during startup, reset from the
XRES pin, or reset from watchdog.
Notes
7. Always greater than 50 mV above VPPOR (PORLEV = 00) for falling supply.
8. Always greater than 50 mV above VPPOR (PORLEV = 01) for falling supply.
9. Always greater than 50 mV above VLVD0.
10. Always greater than 50 mV above VLVD3.
Document Number: 38-12022 Rev. *Q
Page 21 of 43
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DC Programming Specifications
Table 20 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C ≤ TA ≤ 85 °C, 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, or 2.4 V to 3.0 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 20. DC Programming Specifications
Symbol
VDDP
Description
VDD for programming and erase
Min
4.5
Typ
5.0
Max
5.5
Units
V
VDDLV
Low VDD for verify
2.4
2.5
2.6
V
VDDHV
High VDD for verify
5.1
5.2
5.3
V
VDDIWRITE
Supply voltage for flash write operations
2.70
–
5.25
V
IDDP
VILP
VIHP
IILP
Supply current during programming or verify
–
Input low voltage during programming or verify
–
Input high voltage during programming or verify
2.2
Input current when applying VILP to P1[0] or P1[1]
–
during programming or verify
Input current when applying VIHP to P1[0] or P1[1]
–
during programming or verify
Output low voltage during programming or verify
–
Output high voltage during programming or verify VDD – 1.0
Flash endurance (per block)
50,000[11]
[12]
Flash endurance (total)
1,800,0000
Flash data retention
10
5
–
–
–
25
0.8
–
0.2
mA
V
V
mA
–
1.5
mA
–
–
–
–0
–
VSS + 0.75
VDD
–
–0
–
V
V
–
–0
Years
IIHP
VOLV
VOHV
FlashENPB
FlashENT
FlashDR
Notes
This specification applies to
the functional requirements
of external programmer tools
This specification applies to
the functional requirements
of external programmer tools
This specification applies to
the functional requirements
of external programmer tools
This specification applies to
this device when it is
executing internal flash
writes
Driving internal pull-down
resistor
Driving internal pull-down
resistor
Erase/write cycles per block
Erase/write cycles
DC I2C Specifications
Table 20 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C ≤ TA ≤ 85 °C, 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, or 2.4 V to 3.0 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 21. DC I2C Specifications[13]
Symbol
Description
VILI2C
Input low level
VIHI2C
Input high level
Min
–
–
0.7 × VDD
Typ
–
–
–
Max
0.3 × VDD
0.25 × VDD
–
Units
V
V
V
Notes
2.4 V ≤ VDD ≤ 3.6 V
4.75 V ≤ VDD ≤ 5.25 V
2.4 V ≤ VDD ≤ 5.25 V
Notes
11. The 50,000 cycle flash endurance per block is guaranteed if the flash is operating within one voltage range. Voltage ranges are 2.4 V to 3.0 V, 3.0 V to 3.6 V,
and 4.75 V to 5.25 V.
12. A maximum of 36 × 50,000 block endurance cycles is allowed. This may be balanced between operations on 36 × 1 blocks of 50,000 maximum cycles each, 36 × 2
blocks of 25,000 maximum cycles each, or 36 × 4 blocks of 12,500 maximum cycles each (and so forth to limit the total number of cycles to 36 × 50,000 and that no
single block ever sees more than 50,000 cycles).For the full industrial range, you must employ a temperature sensor user module (FlashTemp) and feed the result to
the temperature argument before writing. Refer to the application note, Design Aids — Reading and Writing PSoC® Flash – AN2015 for more information on Flash APIs.
13. All GPIO meet the DC GPIO VIL and VIH specifications mentioned in section DC GPIO Specifications on page 18. The I2C GPIO pins also meet the mentioned specs.
Document Number: 38-12022 Rev. *Q
Page 22 of 43
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AC Electrical Characteristics
AC Chip-Level Specifications
Table 22 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C ≤ TA ≤ 85 °C, 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, or 2.4 V to 3.0 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 22. 5-V and 3.3-V AC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
MHz
Trimmed for 5 V or 3.3 V
operation using factory trim
values. Refer to Figure 11 on
page 16.
SLIMO mode = 0.
FIMO24
IMO frequency for 24 MHz
23.4
24
24.6[14,15]
FIMO6
IMO frequency for 6 MHz
5.5
6
6.5[14,15]
MHz
Trimmed for 3.3 V operation
using factory trim values. See
Figure 11 on page 16.
SLIMO mode = 1.
FCPU1
CPU frequency (5 V nominal)
0.0937
24
24.6[14]
MHz
12 MHz only for
SLIMO mode = 0.
FCPU2
CPU frequency (3.3 V nominal)
0.0937
12
12.3[15]
MHz
SLIMO Mode = 0.
MHz
Refer to the section AC Digital
Block Specifications on page 26.
0
[14,16]
FBLK5
Digital PSoC block frequency
(5 V nominal)
0
48
FBLK33
Digital PSoC block frequency
(3.3 V nominal)
0
24
24.6[16]
MHz
F32K1
ILO frequency
15
32
64
kHz
F32K_U
ILO untrimmed frequency
5
–
100
kHz
49.2
tXRST
External reset pulse width
10
–
–
µs
DC24M
24 MHz duty cycle
40
50
60
%
DCILO
ILO duty cycle
20
50
80
%
–
kHz
[14,15]
MHz
Step24M
24 MHz trim step size
Fout48M
48 MHz output frequency
–
50
46.8
48.0
FMAX
Maximum frequency of signal on row input or
row output.
–
–
12.3
MHz
SRPOWER_UP
Power supply slew rate
–
–
250
V/ms
tPOWERUP
Time from end of POR to CPU executing code
–
16
100
ms
tjit_IMO
24-MHz IMO cycle-to-cycle jitter (RMS) [17]
–
200
700
ps
24-MHz IMO long term N cycle-to-cycle jitter
(RMS) [17]
–
300
900
ps
24-MHz IMO period jitter (RMS) [17]
–
100
400
ps
49.2
After a reset and before the M8C
starts to run, the ILO is not
trimmed. See the system resets
section of the PSoC Technical
Reference Manual for details on
this timing.
Trimmed. Using factory trim
values.
VDD slew rate during power-up.
Power-up from 0 V. See the
system resets section of the
PSoC Technical Reference
Manual.
N = 32
Notes
14. 4.75 V < VDD < 5.25 V.
15. 3.0 V < VDD < 3.6 V. Refer to the application note, Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation – AN2012 for more information on
trimming for operation at 3.3 V.
16. See the individual user module datasheets for information on maximum frequencies for user modules.
17. Refer to the application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information on jitter specifications.
Document Number: 38-12022 Rev. *Q
Page 23 of 43
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Table 23. 2.7-V AC Chip-Level Specifications
Min
Typ
Max
Units
FIMO12
Symbol
IMO frequency for 12 MHz
Description
11.5
120
12.7[18,19]
MHz
Trimmed for 2.7 V operation
using factory trim values. See
Figure 11 on page 16.
SLIMO mode = 1.
FIMO6
IMO frequency for 6 MHz
5.5
6
6.5[18,19]
MHz
Trimmed for 2.7 V operation
using factory trim values. See
Figure 11 on page 16.
SLIMO mode = 1.
FCPU1
CPU frequency (2.7 V nominal)
0.093
3
3.15[18]
MHz
24 MHz only for
SLIMO mode = 0.
FBLK27
Digital PSoC block frequency (2.7 V nominal)
0
12
12.5[18,19]
MHz
Refer to the section AC Digital
Block Specifications on page 26.
F32K1
ILO frequency
8
32
96
kHz
F32K_U
ILO untrimmed frequency
5
–
100
kHz
tXRST
External reset pulse width
10
–
–
µs
DCILO
ILO duty cycle
20
50
80
%
FMAX
Maximum frequency of signal on row input or row
output
–
–
12.3
MHz
SRPOWER_UP
Power supply slew rate
–
–
250
V/ms VDD slew rate during power-up.
tPOWERUP
Time from end of POR to CPU executing code
–
16
100
tjit_IMO
12-MHz IMO cycle-to-cycle jitter (RMS)[20]
–
400
1000
ps
12-MHz IMO long term N cycle-to-cycle jitter
(RMS)[20]
–
600
1300
ps
12-MHz IMO period jitter (RMS)[20]
–
100
500
ps
ms
Notes
After a reset and before the M8C
starts to run, the ILO is not
trimmed. See the system resets
section of the PSoC Technical
Reference Manual for details on
this timing.
Power-up from 0 V. See the
system resets section of the
PSoC Technical Reference
Manual.
N = 32
Notes
18. 2.4 V < VDD < 3.0 V.
19. Refer to the application note Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation – AN2012 for more information on maximum frequency
for user modules.
20. Refer to the application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information on jitter specifications.
Document Number: 38-12022 Rev. *Q
Page 24 of 43
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AC General Purpose I/O Specifications
Table 24 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C ≤ TA ≤ 85 °C, 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, or 2.4 V to 3.0 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 24. 5-V and 3.3-V AC GPIO Specifications
Min
Typ
Max
Units
FGPIO
Symbol
GPIO operating frequency
Description
0
–
12
MHz
Notes
Normal strong mode
tRiseF
Rise time, normal strong mode, Cload = 50 pF
3
–
18
ns
VDD = 4.5 V to 5.25 V, 10% to 90%
tFallF
Fall time, normal strong mode, Cload = 50 pF
2
–
18
ns
VDD = 4.5 V to 5.25 V, 10% to 90%
tRiseS
Rise time, slow strong mode, Cload = 50 pF
10
27
–
ns
VDD = 3 V to 5.25 V, 10% to 90%
tFallS
Fall time, slow strong mode, Cload = 50 pF
10
22
–
ns
VDD = 3 V to 5.25 V, 10% to 90%
Table 25. 2.7-V AC GPIO Specifications
Min
Typ
Max
Units
FGPIO
Symbol
GPIO operating frequency
Description
0
–
3
MHz
tRiseF
Rise time, normal strong mode, Cload = 50 pF
6
–
50
ns
Notes
Normal strong mode
VDD = 2.4 V to 3.0 V, 10% to 90%
tFallF
Fall time, normal strong mode, Cload = 50 pF
6
–
50
ns
VDD = 2.4 V to 3.0 V, 10% to 90%
tRiseS
Rise time, slow strong mode, Cload = 50 pF
18
40
120
ns
VDD = 2.4 V to 3.0 V, 10% to 90%
tFallS
Fall time, slow strong mode, Cload = 50 pF
18
40
120
ns
VDD = 2.4 V to 3.0 V, 10% to 90%
Figure 13. GPIO Timing Diagram
90%
GPIO
Pin
10%
TRiseF
TRiseS
TFallF
TFallS
AC Amplifier Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25
V and –40 °C ≤ TA ≤ 85 °C, 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, or 2.4 V to 3.0 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical
parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Settling times, slew rates, and gain bandwidth are based on the analog continuous time PSoC block.
Table 26. 5-V and 3.3-V AC Amplifier Specifications
Min
Typ
Max
Units
tCOMP1
Symbol
Comparator mode response time, 50 mVpp signal centered on Ref
Description
–
–
100
ns
tCOMP2
Comparator mode response time, 2.5 V input, 0.5 V overdrive
–
–
300
ns
Table 27. 2.7-V AC Amplifier Specifications
Min
Typ
Max
Units
tCOMP1
Symbol
Comparator mode response time, 50 mVpp signal centered on Ref
Description
–
–
600
ns
tCOMP2
Comparator mode response time, 1.5 V input, 0.5 V overdrive
–
–
300
ns
Document Number: 38-12022 Rev. *Q
Page 25 of 43
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CY8C21123, CY8C21223, CY8C21323
AC Digital Block Specifications
Table 28 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C ≤ TA ≤ 85 °C, 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, or 2.4 V to 3.0 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 28. 5-V and 3.3-V AC Digital Block Specifications
Function
All functions
Timer
Counter
Dead Band
CRCPRS
(PRS
Mode)
CRCPRS
(CRC
Mode)
SPIM
SPIS
Transmitter
Receiver
Description
Block input clock frequency
VDD ≥ 4.75 V
VDD < 4.75 V
Input clock frequency
No capture, VDD ≥ 4.75 V
No capture, VDD < 4.75 V
With capture
Capture pulse width
Input clock frequency
No enable input, VDD ≥ 4.75 V
No enable input, VDD < 4.75 V
With enable input
Enable input pulse width
Kill pulse width
Asynchronous restart mode
Synchronous restart mode
Disable mode
Input clock frequency
VDD ≥ 4.75 V
VDD < 4.75 V
Input clock frequency
VDD ≥ 4.75 V
VDD < 4.75 V
Input clock frequency
Input clock frequency
Input clock (SCLK) frequency
Width of SS_negated between
transmissions
Input clock frequency
VDD ≥ 4.75 V, 2 stop bits
VDD ≥ 4.75 V, 1 stop bit
VDD < 4.75 V
Input clock frequency
VDD ≥ 4.75 V, 2 stop bits
VDD ≥ 4.75 V, 1 stop bit
VDD < 4.75 V
Min
Typ
Max
Unit
–
–
–
–
49.2
24.6
MHz
MHz
–
–
–
50[21]
–
–
–
–
49.2
24.6
24.6
–
MHz
MHz
MHz
ns
–
–
–
50[21]
–
–
–
–
49.2
24.6
24.6
–
MHz
MHz
MHz
ns
20
50[21]
50[21]
–
–
–
–
–
–
ns
ns
ns
–
–
–
–
49.2
24.6
MHz
MHz
–
–
–
–
–
–
49.2
24.6
24.6
MHz
MHz
MHz
–
–
8.2
MHz
–
50[21]
–
–
4.1
–
MHz
ns
–
–
–
–
–
–
49.2
24.6
24.6
MHz
MHz
MHz
–
–
–
–
–
–
49.2
24.6
24.6
MHz
MHz
MHz
Notes
The SPI serial clock (SCLK) frequency is equal to
the input clock frequency divided by 2.
The input clock is the SPI SCLK in SPIS mode.
The baud rate is equal to the input clock frequency
divided by 8.
The baud rate is equal to the input clock frequency
divided by 8.
Note
21. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document Number: 38-12022 Rev. *Q
Page 26 of 43
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CY8C21123, CY8C21223, CY8C21323
Table 29. 2.7-V AC Digital Block Specifications
Function
Description
All
functions
Block input clock frequency
Timer
Capture pulse width
Input clock frequency, with or without capture
Counter
Typ
Max
Units
–
–
12.7
MHz
100[22]
–
–
ns
–
–
12.7
MHz
100
–
–
ns
Input clock frequency, no enable input
–
–
12.7
MHz
Input clock frequency, enable input
–
–
12.7
MHz
Asynchronous restart mode
20
–
–
ns
Synchronous restart mode
100
–
–
ns
Disable mode
100
–
–
ns
Input clock frequency
–
–
12.7
MHz
CRCPRS
(PRS mode)
Input clock frequency
–
–
12.7
MHz
CRCPRS
(CRC mode)
Input clock frequency
–
–
12.7
MHz
SPIM
Input clock frequency
–
–
6.35
MHz
SPIS
Input clock (SCLK) frequency
–
–
4.1
MHz
100
–
–
ns
Dead band
Enable input pulse width
Min
Notes
2.4 V < VDD < 3.0 V.
Kill pulse width:
Width of SS_ Negated between transmissions
The SPI serial clock (SCLK)
frequency is equal to the input clock
frequency divided by 2.
Transmitter
Input clock frequency
–
–
12.7
MHz
The baud rate is equal to the input
clock frequency divided by 8.
Receiver
Input clock frequency
–
–
12.7
MHz
The baud rate is equal to the input
clock frequency divided by 8.
Note
22. 100 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).
Document Number: 38-12022 Rev. *Q
Page 27 of 43
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CY8C21123, CY8C21223, CY8C21323
AC External Clock Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V, 3.3 V, or
2.7 V at 25 °C and are for design guidance only.
Table 30. 5-V AC External Clock Specifications
Min
Typ
Max
Units
FOSCEXT
Symbol
Frequency
Description
0.093
–
24.6
MHz
Notes
–
High period
20.6
–
5300
ns
–
Low period
20.6
–
–
ns
–
Power-up IMO to switch
150
–
–
µs
Min
Typ
Max
Units
Notes
Table 31. 3.3-V AC External Clock Specifications
Symbol
Description
FOSCEXT
Frequency with CPU clock divide by 1
0.093
–
12.3
MHz
Maximum CPU frequency is 12 MHz at
3.3 V. With the CPU clock divider set to
1, the external clock must adhere to the
maximum frequency and duty cycle
requirements.
FOSCEXT
Frequency with CPU clock divide by 2 or
greater
0.186
–
24.6
MHz
If the frequency of the external clock is
greater than 12 MHz, the CPU clock
divider must be set to 2 or greater. In this
case, the CPU clock divider ensures
that the fifty percent duty cycle
requirement is met.
–
High period with CPU clock divide by 1
41.7
–
5300
ns
–
Low period with CPU clock divide by 1
41.7
–
–
ns
–
Power-up IMO to switch
150
–
–
µs
Table 32. 2.7-V AC External Clock Specifications
Min
Typ
Max
Units
Notes
FOSCEXT
Symbol
Frequency with CPU clock divide by 1
Description
0.093
–
6.060
MHz
Maximum CPU frequency is 3 MHz at
2.7 V. With the CPU clock divider set to
1, the external clock must adhere to the
maximum frequency and duty cycle
requirements.
FOSCEXT
Frequency with CPU clock divide by 2 or
greater
0.186
–
12.12
MHz
If the frequency of the external clock is
greater than 3 MHz, the CPU clock
divider must be set to 2 or greater. In this
case, the CPU clock divider ensures
that the fifty percent duty cycle
requirement is met.
–
High period with CPU clock divide by 1
83.4
–
5300
ns
–
Low period with CPU clock divide by 1
83.4
–
–
ns
–
Power-up IMO to switch
150
–
–
µs
Document Number: 38-12022 Rev. *Q
Page 28 of 43
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CY8C21123, CY8C21223, CY8C21323
AC Programming Specifications
Table 33 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C
and are for design guidance only.
Table 33. AC Programming Specifications
Symbol
tRSCLK
tFSCLK
tSSCLK
tHSCLK
FSCLK
tERASEB
tWRITE
tDSCLK3
tDSCLK2
tERASEALL
Description
Rise time of SCLK
Fall time of SCLK
Data set up time to falling edge of SCLK
Data hold time from falling edge of SCLK
Frequency of SCLK
Flash erase time (block)
Flash block write time
Data out delay from falling edge of SCLK
Data out delay from falling edge of SCLK
Flash erase time (bulk)
tPROGRAM_HOT Flash block erase + flash block write time
tPROGRAM_COLD Flash block erase + flash block write time
Min
1
1
40
40
0
–
–
–
–
–
Typ
–
–
–
–
–
10
80
–
–
20
Max
20
20
–
–
8
–
–
50
70
–
Units
ns
ns
ns
ns
MHz
ms
ms
ns
ns
ms
–
–
–
–
180[24]
360[24]
ms
ms
Notes
3.0 ≤ VDD ≤ 3.6.
2.4 ≤ VDD ≤ 3.0.
Erase all blocks and
protection fields at once.
0 °C ≤ Tj ≤ 100 °C.
–40 °C ≤ Tj ≤ 0 °C.
AC I2C Specifications
Table 34 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C ≤ TA ≤ 85 °C, 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, or 2.4 V to 3.0 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 34. AC Characteristics of the I2C SDA and SCL Pins for VCC ≥ 3.0 V
Symbol
Description
Standard Mode
Min
Max
0
100
Fast Mode
Min
Max
0
400
Units
FSCLI2C
SCL clock frequency
tHDSTAI2C
4.0
–
0.6
–
µs
tLOWI2C
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
Low period of the SCL clock
4.7
–
1.3
–
µs
tHIGHI2C
High period of the SCL clock
4.0
–
0.6
–
µs
tSUSTAI2C
Setup time for a repeated START condition
4.7
–
0.6
–
µs
tHDDATI2C
Data hold time
0
–
0
–
µs
2500
–0
–0
ns0
–
µs
time0
[23]
kHz
tSUDATI2C
Data setup
tSUSTOI2C
Setup time for STOP condition
4.0
–
0.6
tBUFI2C
Bus free time between a STOP and START condition
4.7
–
1.3
–
µs
tSPI2C
Pulse width of spikes are suppressed by the input filter
–
–
0
50
ns
100
Notes
23. A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSUDAT ≥ 250 ns must then be met. This automatically becomes
the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line trmax + tSUDAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C-bus specification) before the SCL line is released.
24. For the full industrial range, you must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to the application note, Design Aids — Reading and Writing PSoC® Flash – AN2015 for more information on Flash APIs.
Document Number: 38-12022 Rev. *Q
Page 29 of 43
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CY8C21123, CY8C21223, CY8C21323
Table 35. 2.7-V AC Characteristics of the I2C SDA and SCL Pins (Fast Mode Not Supported)
Symbol
Standard Mode
Min
Max
0
100
Description
FSCLI2C
SCL clock frequency
tHDSTAI2C
tLOWI2C
Hold time (repeated) START Condition. After this period, the first clock
pulse is generated.
Low period of the SCL clock
tHIGHI2C
tSUSTAI2C
tHDDATI2C
tSUDATI2C
Fast Mode
Min
Max
–
–
Units
kHz
4.0
–
–
–
µs
4.7
–
–
–
µs
High period of the SCL clock
4.0
–
–
–
µs
Setup time for a repeated START condition
4.7
–
–
–
µs
Data hold time
0
–
–
–
µs
Data setup time
250
–
–
–
ns
tSUSTOI2C
Setup time for STOP condition
4.0
–
–
–
µs
tBUFI2C
Bus free time between a STOP and START condition
4.7
–
–
–
µs
tSPI2C
Pulse width of spikes are suppressed by the input filter.
–
–
–
–
ns
Figure 14. Definition for Timing for Fast/Standard Mode on the I2C Bus
I2C_SDA
TSUDATI2C
THDSTAI2C
TSPI2C
THDDATI2CTSUSTAI2C
TBUFI2C
I2C_SCL
THIGHI2C TLOWI2C
S
START Condition
Document Number: 38-12022 Rev. *Q
TSUSTOI2C
Sr
Repeated START Condition
P
S
STOP Condition
Page 30 of 43
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CY8C21123, CY8C21223, CY8C21323
Packaging Information
This section illustrates the packaging specifications for the CY8C21x23 PSoC device, along with the thermal impedances for each
package and minimum solder reflow peak temperature.
Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of
the emulation tools' dimensions, refer to the emulator pod drawings at http://www.cypress.com.
Packaging Dimensions
Figure 15. 8-Pin (150-Mil) SOIC
51-85066 *D
Document Number: 38-12022 Rev. *Q
Page 31 of 43
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CY8C21123, CY8C21223, CY8C21323
Figure 16. 16-Pin (150-Mil) SOIC
PIN 1 ID
8
1
*
*
9
16
MIN.
MAX.
DIMENSIONS IN INCHES[MM]
0.291[7.391]
0.299[7.594]
REFERENCE JEDEC MO-119
0.394[10.007]
0.419[10.642]
PART #
S16.3 STANDARD PKG.
SZ16.3 LEAD FREE PKG.
0.026[0.660]
0.032[0.812]
SEATING PLANE
0.397[10.083]
0.413[10.490]
0.092[2.336]
0.105[2.667]
*
0.004[0.101]
0.0118[0.299]
0.050[1.270]
TYP.
0.004[0.101]
0.0091[0.231]
0.0125[0.317]
0.015[0.381]
0.050[1.270]
0.013[0.330]
0.019[0.482]
51-85022 *D
-
-
Figure 17. 16-Pin QFN with no E-Pad
2.9
3.1
0.20 min
1
1
2
2.9
3.1
0.20 DIA TYP.
0.45
0.55
2
1.5 (NOM)
PIN #1 ID
0.152 REF.
0.30
0.18
0.05 MAX
0.50
0.60 MAX
1.5
SEATING PLANE
TOP VIEW
SIDE VIEW
BOTTOM VIEW
NOTES:
PART NO.
DESCRIPTION
LG16A
LEAD-FREE
LD16A
STANDARD
1. JEDEC # MO-220
2. Package Weight: 0.014g
3. DIMENSIONS IN MM, MIN
MAX
001-09116 *E
Document Number: 38-12022 Rev. *Q
Page 32 of 43
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Figure 18. 20-Pin (210-Mil) SSOP
51-85077 *E
Figure 19. 24-Pin (4 × 4) QFN
SIDE VIEW
TOP VIEW
BOTTOM VIEW
0.05
3.90
4.10
Ø0.50
C
1.00 MAX.
0.23±0.05
0.05 MAX.
3.70
3.80
0.80 MAX.
2.49
0.20 REF.
N
PIN1 ID
0.20 R.
N
1
1
2
2.45
2.55
3.90
4.10
3.70
3.80
2
2.49
SOLDERABLE
EXPOSED
PAD
0.45
0.30-0.50
0.42±0.18
(4X)
0°-12°
C
NOTES:
1.
SEATING
PLANE
0.50
2.45
2.55
HATCH IS SOLDERABLE EXPOSED METAL.
2. REFERENCE JEDEC#: MO-220
3. PACKAGE WEIGHT: 0.042g
4. ALL DIMENSIONS ARE IN MM [MIN/MAX]
5. PACKAGE CODE
PART #
DESCRIPTION
LF24A
LY24A
STANDARD
LEAD FREE
Document Number: 38-12022 Rev. *Q
51-85203 *B
Page 33 of 43
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Important Note For information on the preferred dimensions for mounting QFN packages, refer the application note,
Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages available at http://www.amkor.com.
Note that pinned vias for thermal conduction are not required for the low power 24, 32, and 48-pin QFN PSoC devices.
Thermal Impedances
Table 36. Thermal Impedances per Package
Package
Typical θJA [25]
8 SOIC
186 °C/W
16 SOIC
125 °C/W
16 QFN
46 °C/W
20 SSOP
117 °C/W
24 QFN
[26]
40 °C/W
Solder Reflow Peak Temperature
Table 37 lists the minimum solder reflow peak temperature to achieve good solderability.
Table 37. Solder Reflow Peak Temperature
Package
Maximum Peak Temperature
Time at Maximum Temperature
8 SOIC
260 °C
20 s
16 SOIC
260 °C
20 s
16 QFN
260 °C
20 s
20 SSOP
260 °C
20 s
24 QFN
260 °C
20 s
Notes
25. TJ = TA + POWER × θJA
26. To achieve the thermal impedance specified for the QFN package, refer to "Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF)
Packages" available at http://www.amkor.com.
27. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220+/-5 °C with Sn-Pb or 245+/-5 °C with Sn-Ag-Cu
paste. Refer to the solder manufacturer specifications.
Document Number: 38-12022 Rev. *Q
Page 34 of 43
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Ordering Information
The following table lists the CY8C21x23 PSoC device’s key package features and ordering codes.
Digital
PSoC
Blocks
Analog
Blocks
Digital I/O
Pins
Analog
Inputs
Analog
Outputs
XRES Pin
Table 38. CY8C21x23 PSoC Device Key Features and Ordering Information
8-Pin (150-Mil) SOIC
CY8C21123-24SXI
4K
256
No
–40 °C to +85 °C
4
4
6
4
0
No
8-Pin (150-Mil) SOIC
(Tape and Reel)
CY8C21123-24SXIT
4K
256
No
–40 °C to +85 °C
4
4
6
4
0
No
16-Pin (150-Mil) SOIC
CY8C21223-24SXI
4K
256
Yes
–40 °C to +85 °C
4
4
12
8
0
No
16-Pin (150-Mil) SOIC
(Tape and Reel)
CY8C21223-24SXIT
4K
256
Yes
–40 °C to +85 °C
4
4
12
8
0
No
16-Pin (3 × 3) QFN with CY8C21223-24LGXI
no E-Pad
4K
256
No
–40 °C to +85 °C
4
4
12
8
0
Yes
20-Pin (210-Mil) SSOP CY8C21323-24PVXI
4K
256
No
–40 °C to +85 °C
4
4
16
8
0
Yes
20-Pin (210-Mil) SSOP CY8C21323-24PVXIT
(Tape and Reel)
4K
256
No
–40 °C to +85 °C
4
4
16
8
0
Yes
24-Pin (4 × 4) QFN
CY8C21323-24LFXI
4K
256
Yes
–40 °C to +85 °C
4
4
16
8
0
Yes
24-Pin (4 × 4) QFN
(Tape and Reel)
CY8C21323-24LFXIT
4K
256
Yes
–40 °C to +85 °C
4
4
16
8
0
Yes
Package
Ordering Code
Flash
(Bytes)
RAM
(Bytes)
Switch
Mode
Pump
Temperature
Range
Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).
Ordering Code Definitions
CY 8 C 21 xxx-24xx
Package Type:
SX = SOIC Pb-Free
PVX = SSOP Pb-Free
LFX/LGX = QFN Pb-Free
Thermal Rating:
C = Commercial
I = Industrial
E = Extended
Speed: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress
Document Number: 38-12022 Rev. *Q
Page 35 of 43
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Acronyms
Acronyms Used
Table 39 lists the acronyms that are used in this document.
Table 39. Acronyms Used in this Datasheet
Acronym
AC
Description
alternating current
Acronym
PCB
Description
printed circuit board
ADC
analog-to-digital converter
PGA
programmable gain amplifier
API
application programming interface
POR
power on reset
CMOS
CPU
CRC
CT
DAC
DC
EEPROM
GPIO
complementary metal oxide semiconductor
central processing unit
cyclic redundancy check
PPOR
PRS
PSoC®
precision power on reset
pseudo-random sequence
Programmable System-on-Chip
continuous time
PWM
pulse width modulator
digital-to-analog converter
QFN
quad flat no leads
SC
switched capacitor
direct current
electrically erasable programmable read-only
memory
SLIMO
slow IMO
general purpose I/O
SMP
switch mode pump
in-circuit emulator
SOIC
small-outline integrated circuit
IDE
integrated development environment
SPITM
serial peripheral interface
ILO
internal low speed oscillator
SRAM
static random access memory
IMO
internal main oscillator
SROM
supervisory read only memory
I/O
input/output
SSOP
shrink small-outline package
IrDA
infrared data association
UART
ISSP
in-system serial programming
ICE
USB
universal asynchronous reciever / transmitter
universal serial bus
LVD
low voltage detect
WDT
watchdog timer
MCU
microcontroller unit
XRES
external reset
MIPS
million instructions per second
Reference Documents
CY8CPLC20, CY8CLED16P01, CY8C29x66, CY8C27x43, CY8C24x94, CY8C24x23, CY8C24x23A, CY8C22x13, CY8C21x34,
CY8C21x23, CY7C64215, CY7C603xx, CY8CNP1xx, and CYWUSB6953 PSoC® Programmable System-on-Chip Technical
Reference Manual (TRM) (001-14463)
Design Aids – Reading and Writing PSoC® Flash – AN2015 (001-40459)
Adjusting PSoC® Trims for 3.3 V and 2.7 V Operation – AN2012 (001-17397)
Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 (001-14503)
Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages – available at http://www.amkor.com.
Document Number: 38-12022 Rev. *Q
Page 36 of 43
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CY8C21123, CY8C21223, CY8C21323
Document Conventions
Units of Measure
Table 40 lists the unit sof measures.
Table 40. Units of Measure
Symbol
dB
Unit of Measure
Symbol
decibels
mH
Unit of Measure
millihenry
°C
degree Celsius
µH
microhenry
µF
microfarad
µs
microsecond
pF
picofarad
ms
millisecond
kHz
kilohertz
ns
nanosecond
MHz
megahertz
ps
picosecond
rt-Hz
root hertz
µV
microvolts
mV
millivolts
kΩ
kilohm
Ω
ohm
µA
microampere
V
volts
mA
milliampere
W
watt
nA
nanoampere
mm
pA
pikoampere
%
mVpp
millivolts peak-to-peak
millimeter
percent
Numeric Conventions
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).
Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended
lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimals.
Glossary
active high
1. A logic signal having its asserted state as the logic 1 state.
2. A logic signal having the logic 1 state as the higher voltage of the two states.
analog blocks
The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous
time) blocks. These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain
stages, and much more.
analog-to-digital
(ADC)
A device that changes an analog signal to a digital signal of corresponding magnitude. Typically,
an ADC converts a voltage to a digital number. The digital-to-analog (DAC) converter performs
the reverse operation.
Application
programming
interface (API)
A series of software routines that comprise an interface between a computer application and
lower level services and functions (for example, user modules and libraries). APIs serve as
building blocks for programmers that create software applications.
asynchronous
A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal.
bandgap
reference
A stable voltage reference design that matches the positive temperature coefficient of VT with
the negative temperature coefficient of VBE, to produce a zero temperature coefficient (ideally)
reference.
bandwidth
1. The frequency range of a message or information processing system measured in hertz.
2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or
loss); it is sometimes represented more specifically as, for example, full width at half maximum.
Document Number: 38-12022 Rev. *Q
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Glossary (continued)
bias
1. A systematic deviation of a value from a reference value.
2. The amount by which the average of a set of values departs from a reference value.
3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a
reference level to operate the device.
block
1. A functional unit that performs a single function, such as an oscillator.
2. A functional unit that may be configured to perform one of several functions, such as a digital
PSoC block or an analog PSoC block.
buffer
1. A storage area for data that is used to compensate for a speed difference, when transferring
data from one device to another. Usually refers to an area reserved for IO operations, into
which data is read, or from which data is written.
2. A portion of memory set aside to store data, often before it is sent to an external device or as
it is received from an external device.
3. An amplifier used to lower the output impedance of a system.
bus
1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets
with similar routing patterns.
2. A set of signals performing a common function and carrying similar data. Typically represented
using vector notation; for example, address[7:0].
3. One or more conductors that serve as a common connection for a group of related devices.
clock
The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is
sometimes used to synchronize different logic blocks.
comparator
An electronic circuit that produces an output voltage or current whenever two input levels simultaneously
satisfy predetermined amplitude requirements.
compiler
A program that translates a high level language, such as C, into machine language.
configuration
space
In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to
‘1’.
crystal oscillator
An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric
crystal is less sensitive to ambient temperature than other circuit components.
cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear
check (CRC)
feedback shift register. Similar calculations may be used for a variety of other purposes such as
data compression.
data bus
A bi-directional set of signals used by a computer to convey information from a memory location
to the central processing unit and vice versa. More generally, a set of signals used to convey
data between digital functions.
debugger
A hardware and software system that allows you to analyze the operation of the system
under development. A debugger usually allows the developer to step through the firmware one
step at a time, set break points, and analyze memory.
dead band
A period of time when neither of two or more signals are in their active state or in transition.
digital blocks
The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC
generator, pseudo-random number generator, or SPI.
Document Number: 38-12022 Rev. *Q
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Glossary (continued)
digital-to-analog
(DAC)
A device that changes a digital signal to an analog signal of corresponding magnitude. The analogto-digital (ADC) converter performs the reverse operation.
duty cycle
The relationship of a clock period high time to its low time, expressed as a percent.
emulator
Duplicates (provides an emulation of) the functions of one system with a different system, so that
the second system appears to behave like the first system.
External Reset
(XRES)
An active high signal that is driven into the PSoC device. It causes all operation of the CPU and
blocks to stop and return to a pre-defined state.
Flash
An electrically programmable and erasable, non-volatile technology that provides you the
programmability and data storage of EPROMs, plus in-system erasability. Non-volatile means
that the data is retained when power is OFF.
Flash block
The smallest amount of Flash ROM space that may be programmed at one time and the smallest
amount of Flash space that may be protected. A Flash block holds 64 bytes.
frequency
The number of cycles or events per unit of time, for a periodic function.
gain
The ratio of output current, voltage, or power to input current, voltage, or power, respectively.
Gain is usually expressed in dB.
I2C
A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an
Inter-Integrated Circuit. It is used to connect low-speed peripherals in an embedded system. The
original system was created in the early 1980s as a battery control interface, but it was later used
as a simple internal bus system for building control electronics. I2C uses only two bi-directional
pins, clock and data, both running at +5V and pulled high with resistors. The bus operates at 100
kbits/second in standard mode and 400 kbits/second in fast mode.
ICE
The in-circuit emulator that allows you to test the project in a hardware environment, while
viewing the debugging device activity in a software environment (PSoC Designer).
input/output (I/O) A device that introduces data into or extracts data from a system.
interrupt
A suspension of a process, such as the execution of a computer program, caused by an event
external to that process, and performed in such a way that the process can be resumed.
interrupt service
routine (ISR)
A block of code that normal code execution is diverted to when the M8C receives a hardware
interrupt. Many interrupt sources may each exist with its own priority and individual ISR code
block. Each ISR code block ends with the RETI instruction, returning the device to the point in
the program where it left normal program execution.
jitter
1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on
serial data streams.
2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between
successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles.
low-voltage detect A circuit that senses VDD and provides an interrupt to the system when VDD falls lower than a selected threshold.
(LVD)
M8C
An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside
a PSoC by interfacing to the Flash, SRAM, and register space.
Document Number: 38-12022 Rev. *Q
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Glossary (continued)
master device
A device that controls the timing for data exchanges between two devices. Or when devices are
cascaded in width, the master device is the one that controls the timing for data exchanges
between the cascaded devices and an external interface. The controlled device is called the
slave device.
microcontroller
An integrated circuit chip that is designed primarily for control systems and products. In addition
to a CPU, a microcontroller typically includes memory, timing circuits, and IO circuitry. The reason
for this is to permit the realization of a controller with a minimal quantity of chips, thus
achieving maximal possible miniaturization. This in turn, reduces the volume and the cost of
the controller. The microcontroller is normally not used for general-purpose computation as is a
microprocessor.
mixed-signal
The reference to a circuit containing both analog and digital techniques and components.
modulator
A device that imposes a signal on a carrier.
noise
1. A disturbance that affects a signal and that may distort the information carried by the signal.
2. The random variations of one or more characteristics of any entity such as voltage, current, or data.
oscillator
A circuit that may be crystal controlled and is used to generate a clock frequency.
parity
A technique for testing transmitting data. Typically, a binary digit is added to the data to make the
sum of all the digits of the binary data either always even (even parity) or always odd (odd parity).
Phase-locked
loop (PLL)
An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative
to a reference signal.
pinouts
The pin number assignment: the relation between the logical inputs and outputs of the PSoC
device and their physical counterparts in the printed circuit board (PCB) package. Pinouts
involve pin numbers as a link between schematic and PCB design (both being computer generated
files) and may also involve pin names.
port
A group of pins, usually eight.
Power on reset
(POR)
A circuit that forces the PSoC device to reset when the voltage is lower than a pre-set level. This is
one type of hardware reset.
PSoC®
Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-onChip™ is a trademark of Cypress.
PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology.
pulse width
An output in the form of duty cycle which varies as a function of the applied measurand
modulator (PWM)
RAM
An acronym for random access memory. A data-storage device from which data can be read out
and new data can be written in.
register
A storage device with a specific capacity, such as a bit or byte.
reset
A means of bringing a system back to a know state. See hardware reset and software reset.
ROM
An acronym for read only memory. A data-storage device from which data can be read out, but
new data cannot be written in.
Document Number: 38-12022 Rev. *Q
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Glossary (continued)
serial
1. Pertaining to a process in which all events occur one after the other.
2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or
channel.
settling time
The time it takes for an output signal or value to stabilize after the input has changed from one
value to another.
shift register
A memory storage device that sequentially shifts a word either left or right to output a stream of
serial data.
slave device
A device that allows another device to control the timing for data exchanges between two
devices. Or when devices are cascaded in width, the slave device is the one that allows another
device to control the timing of data exchanges between the cascaded devices and an external
interface. The controlling device is called the master device.
SRAM
An acronym for static random access memory. A memory device where you can store and
retrieve data at a high rate of speed. The term static is used because, after a value is loaded into an SRAM cell,
it remains unchanged until it is explicitly altered or until power is removed from the device.
SROM
An acronym for supervisory read only memory. The SROM holds code that is used to boot the
device, calibrate circuitry, and perform Flash operations. The functions of the SROM may be
accessed in normal user code, operating from Flash.
stop bit
A signal following a character or block that prepares the receiving device to receive the next
character or block.
synchronous
1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal.
2. A system whose operation is synchronized by a clock signal.
tri-state
A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does
not drive any value in the Z state and, in many respects, may be considered to be disconnected
from the rest of the circuit, allowing another output to drive the same net.
UART
A UART or universal asynchronous receiver-transmitter translates between parallel bits of data
and serial bits.
user modules
Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and
configuring the lower level Analog and Digital PSoC Blocks. User Modules also provide high
level API (Application Programming Interface) for the peripheral function.
user space
The bank 0 space of the register map. The registers in this bank are more likely to be modified
during normal program execution and not just during initialization. Registers in bank 1 are most
likely to be modified only during the initialization phase of the program.
VDD
A name for a power net meaning "voltage drain." The most positive power supply signal. Usually
5 V or 3.3 V.
VSS
A name for a power net meaning "voltage source." The most negative power supply signal.
watchdog timer
A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified
period of time.
Document Number: 38-12022 Rev. *Q
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CY8C21123, CY8C21223, CY8C21323
Document History Page
Document Title: CY8C21123, CY8C21223, CY8C21323 PSoC® Programmable System-on-Chip™
Document Number:38-12022
Orig. of
Submission
Revision
ECN
Description of Change
Change
Date
**
133248
NWJ
See ECN New silicon and document (Revision **).
*A
208900
NWJ
See ECN Add new part, new package and update all ordering codes to Pb-free.
*B
212081
NWJ
See ECN Expand and prepare Preliminary version.
*C
227321
CMS Team
See ECN Update specs., data, format.
*D
235973
SFV
See ECN Updated Overview and Electrical Spec. chapters, along with 24-pin pinout.
Added CMP_GO_EN register (1,64h) to mapping table.
*E
290991
HMT
See ECN Update datasheet standards per SFV memo. Fix device table. Add part
numbers to pinouts and fine tune. Change 20-pin SSOP to CY8C21323. Add
Reflow Temp. table. Update diagrams and specs.
*F
301636
HMT
See ECN DC Chip-Level Specification changes. Update links to new CY.com Portal.
*G
324073
HMT
See ECN Obtained clearer 16 SOIC package. Update Thermal Impedances and Solder
Reflow tables. Re-add pinout ISSP notation. Fix ADC type-o. Fix TMP register
names. Update Electrical Specifications. Add CY logo. Update CY copyright.
Make datasheet Final.
*H
2588457
KET/HMI/
10/22/2008 New package information on page 9. Converted datasheet to new template.
AESA
Added 16-Pin OFN package diagram.
*I
2618175 OGNE/PYRS
12/09/08 Added Note in Ordering Information Section. Changed title from PSoC
Mixed-Signal Array to PSoC Programmable System-on-Chip. Updated ‘Development Tools’ and ‘Designing with PSoC Designer’ sections on pages 5 and 6
*J
2682782 MAXK/AESA 04/03/2009 Corrected 16 COL pinout.
*K
2699713
MAXK
04/29/09 Minor ECN to correct paragraph style of 16 COL Pinout. No change in content.
*L
2762497
JVY
09/11/2009 Updated DC GPIO, AC Chip-Level, and AC Programming Specifications as
follows:
Modified FIMO6 and TWRITE specifications.
Replaced TRAMP time) specification with SRPOWER_UP (slew rate) specification.
Added note [11] to Flash Endurance specification.
Added IOH, IOL, DCILO, F32K_U, TPOWERUP, TERASEALL, TPROGRAM_HOT, and
TPROGRAM_COLD specifications..
*M
2792630
TTO
10/26/2009 Updated ordering information for CY8C21223-24LGXI to indicate availability of
XRES pin.
2901653
NJF
03/30/2010 Changed 16-pin COL to 16-pin QFN in the datasheet.
*N
Added Contents.
Updated links in Sales, Solutions, and Legal Information
Updated Cypress website links.
Added TBAKETEMP and TBAKETIME parameters in Absolute Maximum Ratings
Updated 5-V and 3.3-V AC Chip-Level Specifications
Updated Notes in Packaging Information and package diagrams.
Updated Ordering Code Definitions
2928895
YJI
05/06/2010 No technical updates.
*O
Included with EROS spec.
*P
3044869
NJF
10/01/2010 Added PSoC Device Characteristics table .
Added DC I2C Specifications table.
Added F32K_U max limit.
Added Tjit_IMO specification, removed existing jitter specifications.
Updated Units of Measure, Acronyms, Glossary, and References sections.
Updated solder reflow specifications.
No specific changes were made to AC Digital Block Specifications table and
I2C Timing Diagram. They were updated for clearer understanding.
Updated Figure 13 since the labelling for y-axis was incorrect.
Template and styles update.
*Q
3263669
YJI
05/23/2011 Updated 16-pin SOIC and 20-pin SSOP package diagrams.
Updated Development Tool Selection and Designing with PSoC Designer
sections.
Document Number: 38-12022 Rev. *Q
Page 42 of 43
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CY8C21123, CY8C21223, CY8C21323
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
cypress.com/go/memory
cypress.com/go/image
PSoC
Touch Sensing
cypress.com/go/psoc
cypress.com/go/touch
USB Controllers
Wireless/RF
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-12022 Rev. *Q
Revised June 1, 2011
Page 43 of 43
PSoC Designer is a trademark and PSoC is a registered trademark of Cypress Semiconductor Corporation.
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided
that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors.
All products and company names mentioned in this document may be the trademarks of their respective holders.
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