LATTICE 81080V

ispLSI 81080V
®
3.3V In-System Programmable
SuperBIG™ High Density PLD
• ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Features
• SuperBIG HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 3.3V Power Supply
— 60,000 PLD Gates/1080 Macrocells
— 192-360 I/O Pins Supporting 3.3V/2.5V I/O
— 1440 Registers
— High-Speed Global and Big Fast Megablock (BFM)
Interconnect
— Wide 20-Macrocell Generic Logic Block (GLB) for
High Performance
— Wide Input Gating (44 Inputs per GLB) for Fast
Counters, State Machines, Address Decoders, Etc.
— PCB-Efficient Ball Grid Array (BGA) Package
Options
2
Functional Block Diagram
12
I/O
12
I/O
12
I/O
12
I/O
12
I/O
12
I/O
12
I/O
Big Fast Megablock 0
12
I/O
12
I/O
Big Fast Megablock 1
12
I/O
12
I/O
Big Fast Megablock 2
12
I/O
12
I/O
Big Fast Megablock 3
12
I/O
12
I/O
Big Fast Megablock 4
12
I/O
®
• HIGH-PERFORMANCE E CMOS TECHNOLOGY
— fmax = 125 MHz Maximum Operating Frequency
— tpd = 8.5 ns Propagation Delay
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Programmable Speed/Power Logic Path
Optimization
• IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND
3.3V IN-SYSTEM PROGRAMMABLE
Global Routing Plane
• ARCHITECTURE FEATURES
— Enhanced Pin-Locking Architecture, Symmetrical
Generic Logic Blocks Connected by Hierarchical
Big Fast Megablock and Global Routing Planes
— Product Term Sharing Array Supports up to 28
Product Terms per Macrocell Output
— Macrocells Support Concurrent Combinatorial and
Registered Functions
— Embedded Tristate Bus Can Be Used as an Internal
Tristate Bus or as an Extension of an External
Tristate Bus
— Macrocell and I/O Registers Feature Multiple Control
Options, Including Set, Reset and Clock Enable
— I/O Pins Support Programmable Bus Hold, Pull-Up,
Open-Drain and Slew Rate Options
— Separate VCCIO Power Supply to Support 3.3V or
2.5V Input/Output Logic Levels
— I/O Cell Register Programmable as Input Register for
Fast Setup Time or Output Register for Fast Clock to
Output Time
12
I/O
Big Fast Megablock 5
12
I/O
12
I/O
Big Fast Megablock 6
12
I/O
12
I/O
Big Fast Megablock 7
12
I/O
12
I/O
Big Fast Megablock 8
12
I/O
Boundary
Scan
12
I/O
12
I/O
12
I/O
12
I/O
12
I/O
12
I/O
81080v block
ispLSI 8000V Family Description
The ispLSI 8000V Family of Register-Intensive, 3.3V
SuperBIG In-System Programmable Logic Devices is
based on Big Fast Megablocks of 120 registered macrocells and a Global Routing Plane (GRP) structure
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
81080v_03
1
July 2000
Specifications ispLSI 81080V
Functional Block Diagram
Figure 1. ispLSI 81080V Functional Block Diagram (Perspective)
Big Fast Megablock Routing Pool (BRP)
Big Fast Megablock Routing Pool (BRP)
Big Fast Megablock Routing Pool (BRP)
Big Fast Megablock Routing Pool (BRP)
Global Routing Plane (GRP) with Tristate Bus Lines
2
Specifications ispLSI 81080V
ispLSI 8000V Family Description (Continued)
device. A global, local and product term clock enable is
also provided, eliminating the need to gate the clock to
the macrocell registers. Reset and preset for the macrocell register is provided from both global and product term
signals. The polarity of all of these control signals is
selectable on an individual macrocell basis. The macrocell register can be programmed to operate as a D-type
register, a D-type flow-through latch or a T-type flip flop.
interconnecting the Big Fast Megablocks. Each Big Fast
Megablock contains 120 registered macrocells arranged
in six groups of 20, a group of 20 being referred to as a
Generic Logic Block, or GLB. Within the Big Fast
Megablock, a Big Fast Megablock Routing Pool (BRP)
interconnects the six GLBs to each other and to 24 Big
Fast Megablock I/O cells with optional I/O registers. The
Global Routing Plane which interconnects the Big Fast
Megablocks has additional global I/Os with optional I/O
registers. The 192-I/O version contains 72 Big Fast
Megablock I/Os and 120 global I/Os, while the 360-I/O
version contains 216 Big Fast Megablock I/Os and 144
global I/Os.
The 20 outputs from the GLB can drive both the Big Fast
Megablock Routing Pool within the Big Fast Megablock
and the Global Routing Plane between the Big Fast
Megablocks. The Big Fast Megablock Routing Pool contains general purpose tracks which interconnect the six
GLBs within the Big Fast Megablock and dedicated
tracks for the signals from the Big Fast Megablock I/O
cells. The Global Routing Plane contains general purpose tracks that interconnect the Big Fast Megablocks
and also carry the signals from the I/Os connected to the
Global Routing Plane.
Outputs from the GLBs in a Big Fast Megablock can drive
both the Big Fast Megablock Routing Pool within the Big
Fast Megablock and the Global Routing Plane between
the Big Fast Megablocks. Switching resources are provided to allow signals in the Global Routing Plane to drive
any or all the Big Fast Megablocks in the device. This
mechanism allows fast, efficient connections, both within
the Big Fast Megablocks and between them.
Control signals for the I/O cell registers are generated
using an extra product term within each GLB, or using
dedicated input pins. Each GLB has two extra product
terms beyond the 80 available for the macrocell logic.
The first additional product term is used as an optional
shared product term clock for all the macrocells within the
GLB. The second additional product term is then routed
to an I/O Control Bus using a separate routing structure
from the Big Fast Megablock Routing Pool and Global
Routing Plane. Use of a separate control bus routing
structure allows the I/O registers to have many control
signals with no impact on the interconnection of the GLBs
and Big Fast Megablocks. The I/O Control Bus is split into
four quadrants, each servicing the I/O cell control requirements for one edge of the device. Signals in the
control bus can be independently selected by any or all
I/O cells to act as clock, clock enable, output enable,
reset or preset.
Each GLB contains 20 macrocells and a fully populated,
programmable AND-array with 82 logic product terms.
The GLB has 44 inputs from the Big Fast Megablock
Routing Pool which are available in both true and complement form for every product term. Up to 20 of these inputs
can be switched to provide local feedback into the GLB
for logic functions that require it. The 80 general-purpose
product terms can be grouped into 20 sets of four and
sent into a Product Term Sharing Array (PTSA) which
allows sharing up to a maximum of 28 product terms for
a single function. Alternatively, the PTSA can be bypassed for functions of four product terms or less.
The 20 registered macrocells in the GLB are driven by the
20 outputs from the PTSA or the PTSA bypass. Each
macrocell contains a programmable XOR gate, a programmable register/latch/toggle flip-flop and the
necessary clocks and control logic to allow combinatorial
or registered operation. Each macrocell has two outputs,
one output can be fed back inside the GLB to the ANDarray, while the other output drives both the Big Fast
Megablock Routing Pool and the Global Routing Plane.
This dual output capability from the macrocell allows
efficient use of the hardware resources. One output can
be a registered function for example, while the other
output can be an unrelated combinatorial function.
Each Big Fast Megablock has 24 I/O cells. The Global
Routing Pool has 144 I/O cells. Each I/O cell can be
configured as a combinatorial input, combinatorial output, registered input, registered output or bidirectional
I/O. I/O cell registers can be clocked from one of several
global, local or product term clocks which are selected
from the I/O control bus. A global and product term clock
enable is also provided, eliminating the need for the user
to gate the clock to the I/O cell registers. Reset and preset
for the I/O cell register is provided from both global and
product term signals. The polarity of all of these control
Macrocell registers can be clocked from one of several
global, local or product term clocks available on the
3
Specifications ispLSI 81080V
ispLSI 8000V Family Description (Continued)
Embedded Tristate Bus
signals is selectable on an individual I/O cell basis. The
I/O cell register can be programmed to operate as a Dtype register or a D-type latch.
There is a 108-line embedded internal tristate bus as part
of the Global Routing Plane (GRP), enabling multiple
GLBs to drive the same tracks. This bus can be partitioned into various bus widths such as twelve 9-line
buses, six 18-line buses or three 36-line buses. The
GLBs can dynamically share a subset of the Global
Routing Plane tracks. This feature eliminates the need to
convert tristate buses to wide multiplexers on the programmable device. Up to 18 macrocells per GLB can
participate in driving the embedded tristate bus. The
remaining two macrocells per GLB are used to generate
the internal tristate driver control signals on each data
byte (with parity). The embedded tristate bus can also be
configured as an extension of an external tristate bus
using the bidirectional capability of the I/O cells connected to the Global Routing Plane. The Global Routing
Plane I/Os 0-8 and 15-23 from each group (I/OGx as
defined in the I/O Pin Location Table) can connect to the
internal tristate bus as well as the unidirectional/nontristate global routing channels. I/Os 9-14 connect only to
the global routing channel.
The input thresholds are fixed at levels which comply with
both 3.3V and 2.5V interfaces. The output driver can
source 4mA and sink 8mA (3.3V output supply). The
output drivers have a separate VCCIO power supply
which is independent of the main VCC supply for the
device. This feature allows the output drivers to run from
either 3.3V or 2.5V while the device logic is always
powered from 3.3V. The output drivers also provide
individually programmable edge rates and open drain
capability. A programmable pullup resistor is provided to
tie off unused inputs and a programmable bus-hold latch
is available to hold tristate outputs in their last valid state
until the bus is driven again by another device.
The ispLSI 8000V Family features 3.3V, non-volatile insystem programmability for both the logic and the
interconnect structures, providing the means to develop
truly reconfigurable systems. Programming is achieved
through the industry standard IEEE 1149.1-compliant
Boundary Scan interface using the JTAG protocol. Boundary Scan test is also supported through the same interface.
The embedded tristate bus has internal bus hold and
arbitration features in order to make the function more
“user friendly”. The bus hold feature keeps the internal
bus at the previously driven logic state when the bus is
not driven to eliminate bus float. The bus arbitration is
performed on a “first come, first served” priority. In other
words, once a logic block drives the bus, other logic
blocks cannot drive the bus until the first releases the bus.
This arbitration feature prevents internal bus contention
when there is an overlap between two bus enable signals. Typically, it takes about 3ns to resolve one bus
signal coming off the bus to another bus signal driving the
bus. The arbitration feature, combined with the predictability of the CPLD, makes the embedded tristate bus the
most practical for real world bus implementation.
An enhanced, multiple cell security scheme is provided
that prevents reading of the JEDEC programming file
when secured. After the device has been secured using
this mechanism, the only way to clear the security is to
execute a bulk-erase instruction.
ispLSI 81080V Description
The ispLSI 81080V device has nine Big Fast Megablocks
for a total of 9 x 120 = 1080 macrocells.
Each Big Fast Megablock has a total of 24 I/O cells and
the Global Routing Plane has a total of 144 I/O cells. This
gives (9 x 24) + 144 = 360 I/Os for the full I/O version,
while the partial I/O version contains 72 Big Fast
Megablock I/Os + 120 global I/Os = 192 I/Os.
The total registers in the device is the sum of macrocells
plus I/O cells, 1080 + 360 = 1440 registers.
4
Specifications ispLSI 81080V
Figure 2. ispLSI 8000V GLB Overview
I/O Big Fast Megablock Input Tracks
AND Array Input
Routing
General Purpose Big Fast Megablock Input Tracks
20
Feedback Inputs
0
43
Product Term
Sharing Array
Macrocell 0
PT 0
PT 1
PT 2
PT 3
From PTSA
PTSA Bypass
Single PT
PT Clock
PT Preset
PT Reset
Shared PT Clock
Bus Input
To Interconnect
0
From Tristate
Bus Track
Macrocell 1
PT 4
PT 5
PT 6
PT 7
From PTSA
PTSA Bypass
Single PT
PT Clock
PT Preset
PT Reset
Shared PT Clock
Bus Input
To Interconnect
1
From Tristate
Bus Track
Macrocell 2
PT 8
PT 9
PT 10
PT 11
From PTSA
PTSA Bypass
Single PT
PT Clock
PT Preset
PT Reset
Shared PT Clock
Bus Input
Fully Populated
AND Array
To Interconnect
2
From Tristate
Bus Track
Macrocell 3
PT 12
PT 13
PT 14
PT 15
From PTSA
PTSA Bypass
Single PT
PT Clock
PT Preset
PT Reset
Shared PT Clock
Bus Input
To interconnect
3
From Tristate
Bus Track
Macrocell 19
PT 76
PT 77
PT 78
PT 79
From PTSA
PTSA Bypass
Single PT
PT Clock
PT Preset
PT Reset
Shared PT Clock
Bus Input
PT 80
To Interconnect
19
From Tristate Bus Track
To Output Control MUX
PT 81
Function Selector (E2 Cell Controlled)
Note: Macrocells 9 and 10 do not support Tristate Bus Feedback.
5
Specifications ispLSI 81080V
Figure 3. ispLSI 8000V Macrocell Overview
Bus Input From Tristate
Bus Track*
Single PT
Feedback to AND Array
PTSA
D
Q
To Big Fast Megablock
or Global Interconnect
PTSA Bypass
PT Clock
Clk En
Global Clock Enable
To Specific
Global Tristate Bus*
Global Clock 0
Global Clock 1
Global Clock 2
R/L
R P
PT Reset
From Macrocell
9 or 10
GRST
PT Preset
Reset pin
GRST
To All Macrocells and I/O Cells
Preset/Reset Input has Global Polarity Control
From PT80
: Function Selector (E2 Cell Controlled)
*Not available for Macrocells 9 and 10.
6
Specifications ispLSI 81080V
Figure 4. ispLSI 8000V I/O Cell
TOE
VCCIO VCCIO
VCCIO
GLOBAL OE0
GLOBAL OE1
GLOBAL OE2
GLOBAL OE3
From Output
Control Bus
Multiplexed Output From
Big Fast Megablock or
Global Track
D
Q
GLOBAL I/O CLOCK ENABLE
From Output
Control Bus
GLOBAL CLOCK0
GLOBAL CLOCK2
QUADRANT I/O CLOCK
Big Fast Megablock I/O Pad
or Global I/O Pad
Slew Open
Rate Drain
CLKEN
To Specific
Big Fast Megablock
or Global Tracks
R/L
To Specific
Global Tristate Bus
From Output
Control Bus
P
R
From Output
Control Bus
Global I/O Cell
Only
GRST
From Output
Control Bus
: Function Selector (E2 Cell Controlled)
7
Specifications ispLSI 81080V
The Global OE signals and Test OE signal are driven
from the dedicated external control input pins.
Output Control Organization
In addition to the data input and output to the I/O cells,
each I/O cell can have up to six different I/O cell control
signals. In addition to the internal OE control, the five
control signals for each I/O cell consist of pin OE control,
clock enable, clock input, asynchronous preset and asynchronous reset. All of the I/O control signals can be driven
either from the dedicated external input pins or from the
internal control bus.
The 16-bit wide output control buses are organized in four
different quadrants as shown in Figure 5. Since each
GLB is capable of generating the output control signals,
each of the output control bus signals can be driven from
a unique GLB. The 54 GLBs can generate a total of 54
unique I/O control signals. Referring to Figure 2, the GLB
generates its output control signal from control product
term (PT81).
The output enable of each I/O cell can be driven by 21
different sources – 16 from the output control bus, four
from the Global OE pins and one from the Test OE pin.
Figure 5 also illustrates how the quadrant clocks are
routed to the appropriate quadrant I/O cells.
Figure 5. Output Control Bus and Quadrant Organization
GLB
Generated
Output
Control
(see Figure 2)
From PT81
Quadrant 3, 16-Bit Wide Output Control Bus
(I/O G0-G5 <0-11>, QIOCLK3)
Quadrant 1, 16-Bit Wide Output Control Bus
(I/O G0-G5 <12-23>, QIOCLK1)
Quadrant 0, 16-Bit Wide Output Control Bus
(I/O B0-B8 <0-11>, QIOCLK0)
Quadrant 2, 16-Bit Wide Output Control Bus
(I/O B0-B8 <12-23>, QIOCLK2)
OE Bus/80180V
8
Specifications ispLSI 81080V
Figure 6. Boundary Scan Register Circuit for I/O Pins
HIGHZ
EXTEST
PROG_MODE
SCANIN
(from previous
cell)
BSCAN
Registers
D
TOE
BSCAN
Latches
Q
D
Normal
Function
OE
Q
0
1
EXTEST
PROG_MODE
Normal
Function
Shift DR
D
Q
D
Q
Clock DR
D
Q
0
1
SCANOUT
(to next cell)
Update DR
Reset*
*Internal power-up reset signal. Not connected to external reset pin.
Figure 7. Boundary Scan Register Circuit for Input-Only Pins
Input Pin
SCANIN
(from previous
cell
D
Shift DR
Clock DR
9
Q
SCANOUT
(to next cell)
I/O Pin
Specifications ispLSI 81080V
Figure 8. Boundary Scan Waveforms and Timing Specifications
TMS
TDI
Tbtsu
Tbtch
Tbth
Tbtcl
Tbtcp
TCK
Tbtvo
Tbtco
TDO
Valid Data
Tbtcpsu
Data to be
captured
Valid Data
Tbtcph
Data Captured
Tbtuov
Tbtuco
Data to be
driven out
Valid Data
SYMBOL
tbtcp
tbtch
tbtcl
tbtsu
tbth
trf
tbtco
tbtoz
tbtvo
tbtcpsu
tbtcph
tbtuco
tbtuoz
tbtuov
Tbtoz
PARAMETER
Tbtuoz
Valid Data
MIN
MAX
UNITS
TCK Clock Pulse Width
100
—
ns
TCK Pulse Width High
50
—
ns
TCK Pulse Width Low
50
—
ns
TDI, TMS Setup Time to TCK
25
—
ns
TDI, TMS Hold Time from TCK
25
—
ns
TCK, TDI, TMS Rise and Fall Time
50
—
mV/ns
TAP Controller, TCK to TDO Valid
—
25
ns
TAP Controller, TCK to TDO High-Impedance
—
25
ns
TAP Controller, TCK to TDO High-Impedance to Valid Output
—
25
ns
BSCAN Test Capture Register Setup Time
25
—
ns
BSCAN Test Capture Register Hold Time
25
—
ns
BSCAN Test Update Register Clock to Valid Output
—
65
ns
BSCAN Test Update Register Clock to High-Impedance
—
65
ns
BSCAN Test Update Register High-Impedance to Valid Output
—
65
ns
Table 2-0010/81080V
10
Specifications ispLSI 81080V
Absolute Maximum Ratings 1,2
Supply Voltage Vcc .................................. -0.5 to +5.4V
Input Voltage Applied ............................... -0.5 to +5.6V
Tri-Stated Output Voltage Applied ........... -0.5 to +5.6V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
2. Compliance with the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM is a requirement.
DC Recommended Operating Condition
SYMBOL
VCC
VCCIO
PARAMETER
Supply Voltage
Commercial
MIN.
TA = 0°C to 70°C
I/O Supply Voltage
MAX.
UNITS
3.0
3.6
V
2.3
3.6
V
Table 2-0005/81080V
Capacitance (TA=25°C,f=1.0 MHz)
TYPICAL
UNITS
10
pf
VCC = 3.3V, VI/O = 2.0V
Clock Capacitance
10
pf
VCC = 3.3V, VCK = 2.0V
Global Input Capacitance
10
pf
VCC = 3.3V, VG = 2.0V
SYMBOL
C1
C2
C3
PARAMETER
I/O Capacitance
TEST CONDITIONS
Table 2-0006/81080V
Erase/Reprogram Specification
PARAMETER
Erase/Reprogram Cycles
MINIMUM
MAXIMUM
UNITS
10000
–
Cycles
Table 2-0008/81080V
11
Specifications ispLSI 81080V
Switching Test Conditions
Input Pulse Levels
Figure 9. Test Load
GND to VCCIOmin
≤ 1.5 ns 10% to 90%
Input Rise and Fall Time
Input Timing Reference Levels
VCCIO
1.5V
Ouput Timing Reference Levels
R1
1.5V
Output Load
See Figure 9
Device
Output
Table 2-0003/81080V
3-state levels are measured 0.5V from
steady-state active level.
Test
Point
R2
Output Load Conditions (See Figure 9)
3.3V
TEST CONDITION
C
D
2.5V
R1
R2
R2
*CL includes Test Fixture and Probe Capacitance.
CL
316Ω 348Ω 511Ω 475Ω 35pF
A
B
R1
CL *
Active High
∞
348Ω
∞
Active Low
316Ω
∞
511Ω
∞
35pF
Active High to Z
at VOH -0.5V
∞
348Ω
∞
475Ω
5pF
Active Low to Z
at VOL +0.5V
316Ω
∞
511Ω
∞
5pF
∞
∞
∞
∞
35pF
Slow Slew
0213A/81080V
475Ω 35pF
Table 2-0004A/81080V
DC Electrical Characteristics for 3.3V Range
Over Recommended Operating Conditions
SYMBOL
VCCIO
VIL
VIH
VOL
VOH
PARAMETER
I/O Supply Voltage
CONDITION
TA = 0°C to + 70°C
Input Low Voltage
Input High Voltage
Output Low Voltage
IOL = 8 mA
Output High Voltage
IOH = -4 mA
MIN.
MAX. UNITS
3.0
3.6
V
-0.3
0.8
V
2.0
5.25
V
–
0.4
V
–
V
2.4
Table 2-0007/81080V
DC Electrical Characteristics for 2.5V Range
Over Recommended Operating Conditions
SYMBOL
PARAMETER
VCCIO
VIL
VIH
I/O Supply Voltage
VOL
Output Low Voltage
VOH
CONDITION
MIN.
MAX.
UNITS
2.3
2.7
V
Input Low Voltage
-0.3
0.7
V
Input High Voltage
1.7
5.25
V
–
0.2
V
TA = 0°C to + 70°C
VCCIO=min, VIN=VIH or VIL, IOL= 100µA
VCCIO=min, VIN=VIH or VIL, IOL= 2mA
Output High Voltage
–
0.7
V
VCCIO=min, VIN=VIH or VIL, IOH= -100µA
2.1
–
V
VCCIO=min, VIN=VIH or VIL, IOH= -2mA
1.7
–
V
Table 2-0007B/81080V
12
Specifications ispLSI 81080V
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
IIL
IIH
4
IPU
IBHL
IBHH
IBHLO
IBHLH
IBHT
ICC1,3,5
1.
2.
3.
4.
5.
CONDITION
PARAMETER
2
MIN.
TYP.
MAX. UNITS
Input or I/O Low Leakage Current
0V ≤ VIN≤ VIL(Max.)
–
–
-10
µA
Input or I/O High Leakage Current
(VCCIO-0.2)V ≤ VIN ≤ VCCIO
–
–
10
µA
VCCIO ≤ VIN ≤ 5.25V
–
–
50
µA
I/O Active Pullup Current
0V ≤ VIN ≤ VIL
–
–
-250
µA
Bus Hold Low Sustaining Current
VIN = VIL(max)
40
–
–
µA
Bus Hold High Sustaining Current
-40
–
–
µA
Bus Hold Low Overdrive Current
VIN = VIH(min)
0V ≤ VIN ≤ VCCIO
–
–
550
µA
Bus Hold High Overdrive Current
0V ≤ VIN ≤ VCCIO
–
–
-550
µA
VIL
–
VIH
V
–
590
–
–
250
–
Bus Hold Trip Points
Operating Power Supply Current
VIL = 0.5V, VIH = 3.0V High Speed Mode
fTOGGLE = 1 MHz
Low Power Mode
Measured at a frequency of 1MHz using 54 20-bit counters.
Typical values are at VCC = 3.3V and TA = 25°C.
Maximum ICC varies widely with specific device configuration and operating frequency.
Pullup is capable of pulling minimum voltage of VOH under no-load conditions.
Unused inputs held at GND.
13
mA
Table 2-0007C/81080V
Specifications ispLSI 81080V
External Switching Characteristics1
Over Recommended Operating Conditions
PARA- TEST
2
4 #
METER COND.
tpd1
tpd2
fmax
tsuq
thq
tcoq
tsug
thg
tcog
tsu1
th1
tco1
tsuceq
thceq
tsuceg
thceg
tgoe
trglb
trio
trw
twh
twl
1.
2.
3.
4.
-125
DESCRIPTION
-90
-60
MIN. MAX. MIN. MAX. MIN. MAX.
UNITS
A
1 Prop Delay, BFM Input to Same BFM Output, 4 PT Bypass
—
8.5
—
10.0
—
15.0
ns
A
2 Prop Delay, Global Input to Global Output
—
14.5
—
16.0
—
24.0
ns
125.0
—
90.0
—
60.0
—
MHz
8.0
—
12.0
—
ns
0.0
—
0.0
—
ns
3
—
3 Clk Frequency, Local Feedback, Same GLB
—
4 I/O Cell Reg, Data Setup Time, Quadrant I/O Clock
5.0
—
5 I/O Cell Reg, Data Hold Time, Quadrant I/O Clock
0.0
—
A
6 I/O Cell Reg, Quadrant Clock to Output Delay
—
4.0
—
6.0
—
9.0
ns
—
7 I/O Cell Reg, Data Setup Time, Global Clock
3.5
—
6.0
—
9.0
—
ns
—
0.0
—
0.0
—
0.0
—
ns
A
8 I/O Cell Reg, Data Hold Time, Global Clock
9 I/O Cell Reg, Global Clock to Output Delay
—
6.0
—
7.5
—
11.0
ns
—
10 GLB Reg Setup, BFM Input to Same BFM GLB, 4 PT Bypass
4.5
—
7.0
—
10.0
—
ns
—
11 GLB Reg Hold Time, BFM Input to Same BFM GLB
0.0
—
0.0
—
0.0
—
ns
A
12 GLB Reg, Global Clock to Same BFM Output Delay
—
8.0
—
10.0
—
15.0
ns
—
13 I/O Cell Reg, CLKEN Setup Time, Quadrant I/O Clock
5.5
—
6.5
—
9.5
—
ns
—
14 I/O Cell Reg, CLKEN Hold Time, Quadrant I/O Clock
0.0
—
0.0
—
0.0
—
ns
—
15 GLB Reg, CLKEN Setup Time, Global Clock
3.5
—
4.5
—
6.5
—
ns
—
16 GLB Reg, CLKEN Hold Time, Global Clock
0.0
—
0.0
—
0.0
—
ns
B/C
17 Global Output Enable/Disable Delay
—
7.0
—
10.0
—
15.0
ns
—
18 Global Reset/Preset Time, GLB Reg
—
14.0
—
15.0
—
22.0
ns
—
19 Global Reset/Preset Time, I/O Cell Reg
—
8.5
—
10.0
—
15.0
ns
—
20 Global Reset/Preset Pulse Duration
5.0
—
6.5
—
9.5
—
ns
—
21 Global or Quadrant Clock Pulse, High Duration
4.0
—
6.0
—
9.0
—
ns
—
22 Global or Quadrant Clock Pulse, Low Duration
4.0
—
6.0
—
9.0
—
ns
Unless noted otherwise, all parameters use PTSA and CLK0.
Refer to Timing Model in this data sheet for further details.
Standard 20-bit counter with local feedback.
Refer to Switching Test Conditions section.
14
Table 2-0030/81080V
Specifications ispLSI 81080V
Internal Timing Parameters
Over Recommended Operating Conditions
PARAMETER
-125
#2
DESCRIPTION
-90
-60
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
23 Input Pad and Input Buffer, Combinatorial Input
–
0.3
–
0.4
–
0.6
ns
24 Input Pad and Input Buffer, Registered Input
–
6.4
–
7.6
–
11.2
ns
25 Output Register/Latch Bypass to Output Buffer
–
0.0
–
0.0
–
0.0
ns
26 Input Register/Latch Bypass to BFM Routing or GRP
–
0.4
–
0.5
–
0.8
ns
27 I/O Cell Latch, Transparent Mode
–
2.0
–
2.4
–
3.6
ns
I/O Cell Delay
tidcom
tidreg
tobp
tibp
tiolat
tioco
tiosu
tioh
tiorst
tiosuce
tiohce
todreg
todcom
todz
tslf
tsls
28 I/O Cell Register/Latch, Clk/Gate to Output
–
0.5
–
1.2
–
1.6
ns
29 I/O Cell Register/Latch, Setup Time
0.5
–
2.4
–
3.9
–
ns
30 I/O Cell Register/Latch, Hold Time
2.5
–
3.2
–
4.7
–
ns
–
1.5
–
1.7
–
2.5
ns
32 I/O Cell Register/Latch, Setup Time for Clk Enable
0.9
–
1.0
–
1.2
–
ns
33 I/O cell Register/Latch, Hold Time for Clk Enable
4.6
–
4.6
–
6.9
–
ns
31 I/O Cell Register/Latch, Reset or Set Time
34 I/O Cell Output Buffer Delay, Registered Output
–
1.6
–
1.9
–
2.9
ns
35 I/O Cell Output Buffer Delay, Combinatorial Output
–
1.6
–
1.9
–
2.9
ns
36 Output Driver Disable Time
–
1.4
–
1.7
–
2.6
ns
37 Slew Rate Adder, Fast Slew Rate
–
0.0
–
0.0
–
0.0
ns
38 Slew Rate Adder, Slow Slew Rate
–
6.2
–
7.3
–
10.9
ns
GLB / Macrocell Delay
tandhs
tandlp
t1pt
t4ptcom
t4ptreg
tptsa
tmbp
tmlat
tmco
tmsu
tmh
tmrst
tmsuce
tmhce
tfloc
tpck
tpcken
tsck
tscken
tprst
trdir
39 AND Array, High Speed Mode
–
2.6
–
2.9
–
4.2
ns
40 AND Array, Low Power Mode
–
6.5
–
7.7
–
11.5
ns
41 Single Product Term Bypass
–
1.9
–
2.2
–
3.4
ns
42 Four Product Term Bypass, Combinatorial Macrocell
–
0.5
–
0.6
–
0.9
ns
43 Four Product Term Bypass, Registered Macrocell
–
1.4
–
1.7
–
2.2
ns
44 Product Term Sharing Array
–
2.4
–
2.7
–
4.1
ns
45 Macrocell Register/Latch Bypass
–
0.0
–
0.0
–
0.0
ns
46 Macrocell Latch, Transparent Mode
–
4.6
–
5.5
–
8.2
ns
47 Macrocell Register/Latch, Clk/Gate to Output
–
0.2
–
0.8
–
0.9
ns
48 Macrocell Register/Latch, Setup Time
2.7
–
4.5
–
6.9
–
ns
49 Macrocell Register/Latch, Hold Time
1.0
–
1.2
–
1.1
–
ns
–
1.4
–
1.5
–
1.6
ns
51 Macrocell Register/Latch, Setup Time for Clk Enable
1.0
–
1.3
–
1.7
–
ns
52 Macrocell Register/Latch, Hold Time for Clk Enable
2.3
–
2.6
–
3.9
–
ns
50 Macrocell Register/Latch, Reset or Set Time
54 Local Feedback to AND Array
55 Single Product Term, Clk
56 Single Product Term, Clk Enable
–
0.1
–
0.1
–
0.6
ns
1.3
1.3
1.6
1.6
2.5
2.5
ns
–
1.7
–
2.0
–
3.1
ns
57 Shared Product Term, Clk
1.7
1.9
2.0
2.3
3.1
3.5
ns
58 Shared Product Term, Clk Enable
1.7
1.9
2.0
2.3
3.1
3.5
ns
59 Single Product Term, Reset or Set Delay
–
1.5
–
1.7
–
2.6
ns
60 Macrocell Register, Direct Input from GRP
–
7.2
–
8.4
–
12.7
ns
15
Specifications ispLSI 81080V
Internal Timing Parameters
Over Recommended Operating Conditions
PARAMETER
-125
#2
DESCRIPTION
-90
-60
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
0.4
1.0
0.6
1.3
0.8
1.9
ns
62 GRP Delay, Signal from I/O Cell
–
1.8
–
1.9
–
2.8
ns
63 Internal Tristate Bus Enable/Disable, I/O Cell Buffer
–
4.3
–
4.9
–
7.3
ns
64 BFM Routing Delay, Signal from Macrocell
–
0.6
–
0.7
–
1.1
ns
65 GRP Delay, Signal from Macrocell
–
2.6
–
3.0
–
4.5
ns
BFM / Global Routing Pool Delay
tbfmi
tgrpi
tgrpiz
tbfmm
tgrpm
tgrpmz
tbfmg
tgrpb
tbcom
tbreg
tgcom
tgreg
61 BFM Routing Delay, Signal from I/O Cell
66 Internal Tristate Bus Enable/Disable, Macrocell Buffer
–
3.6
–
4.3
–
6.5
ns
67 BFM Routing Delay, Signal from GRP
–
3.3
–
3.3
–
4.9
ns
68 GRP Delay, Signal from BFM Routing
–
1.3
–
1.5
–
2.3
ns
69 BFM Routing to I/O Cell, Combinatorial Path
–
1.5
–
1.7
–
2.6
ns
70 BFM Routing to I/O Cell, Registered Path
–
2.3
–
2.6
–
4.0
ns
71 GRP to I/O Cell, Combinatorial Path
–
0.8
–
0.8
–
1.2
ns
72 GRP to I/O Cell, Registered Path
–
1.6
–
1.7
–
2.6
ns
73 Product Term as I/O Cell Register Clock
–
4.1
–
4.7
–
7.2
ns
74 Product Term as I/O Cell Register Clock Enable
–
4.6
–
5.3
–
8.1
ns
I/O Control Bus Delay
tpiock
tpiocken
tpoe
tpiorst
tpioz
75 Product Term as Output Buffer Enable/Disable
–
5.6
–
6.5
–
9.9
ns
76 Product Term as I/O Cell Register Reset or Set Delay
–
4.3
–
5.0
–
7.6
ns
77 Internal Tristate Bus Control Signal for I/O Cell Buffer
–
3.3
–
3.8
–
5.8
ns
Global Control Delay
tgck
tgcken
tgiock
tgiocken
tqck
tgoe
ttoe
tgmrst
tgiorst
78 Global Macrocell Register Clk
3.9
4.1
4.3
4.9
6.6
7.5
ns
79 Global Macrocell Register Clk Enable
6.4
6.4
7.5
7.5
11.4
11.4
ns
80 Global I/O Register Clk
3.4
3.9
4.0
4.4
6.1
6.5
ns
81 Global I/O Register Clk Enable
6.5
6.5
7.5
7.5
11.4
11.4
ns
82 Quadrant I/O Register Clk
1.9
1.9
2.0
2.9
3.1
4.5
ns
83 Global Output Enable
–
5.6
–
8.3
–
12.4
ns
84 Test Output Enable
–
8.5
–
10.1
–
15.2
ns
85 Global GLB Register Reset
–
7.6
–
7.8
–
11.8
ns
86 Global I/O Cell Register Reset
–
5.4
–
6.4
–
9.6
ns
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
16
Specifications ispLSI 81080V
ispLSI 81080V Timing Model
#69, tbcom
#70, tbreg
#71, tgcom
#72, tgreg
Input Buffer and I/O Cell Register
I/O register delays
I/O
pad
Input buffer
delays
#23, tidcom
#24, tidreg
#25, tobp
#26, tibp
#27, tiolat
#28, tioco
#29, tiosu
#30, tioh
#31, tiorst
#32, tiosuce
#33, tiohce
Output path
Output
buffer
delays
Output routing
#34, todreg
#35, todcom
#36, todz
Input path
BFM Routing Pool
#61, tbfmi #67, tbfmg
#64, tbfmm
z
GLB/
Macrocell
Local feedback
#54, tfloc
Macrocell
Register
PTSA
AND array
#39,
tandhs
#40,
tandlp
#41, t1pt
#42, t4ptcom
#43, t4ptreg
#44, tptsa
Global
Routing
Plane
#45, tmbp
#46, tmlat
#47, tmco
#48, tmsu
#49, tmh
#50, tmrst
#51, tmsuce
#52, tmbce
PT Mcell controls
#55, tpck
#56, tpcken
#57, tsck
#58, tscken
#59, tprst
#62, tgrpi
#63, tgrpiz
#65, tgrpm
#66, tgrpmz
#68, tgrpb
Bus direct
#60, trdir
PT I/O control bus
Global control
delay
Input
pad
#78, tgck
#79, tgcken
#80, tgiock
#81, tgiocken
#82, tqck
#83, tgoe
#84, ttoe
#85, tgmrst
#86, tgiorst
#73, tpiock
#74, tpiocken
#75, tpoe
#76, tpiorst
#77, tpioz
8840V_Model.eps
17
Output
slew rate
adders
#37, tslf
#38, tsls
I/O
pad
Specifications ispLSI 81080V
Example Timing Calculations
tpd1
= (BFM Input Path Delay) + (GLB Delay) + (Output Path Delay)
= (tidcom + tibp + tbfmi max) + (tandhs + t4ptcom + tmbp) + (tbfmm + tbcom + tobp + todcom + tslf)
= (#23 + #26 + #61) + (#39 + #42 + #45) + (#64 + #69 + #25 + #35 + #37)
= (0.3 + 0.4 + 1.0) + (2.6 + 0.5 + 0.0) + (0.6 + 1.5 + 0.0 + 1.6 + 0.0)
= 8.5 ns
tpd (within BFM)
= (BFM Delay) + (GLB Delay)
= (tbfmm) + (tandhs + t4ptcom + tmbp)
= (#64) + (#39 + #42 + #45)
= (0.6) + (2.6 + 0.5 + 0.0)
= 3.7 ns
tpd (between BFMs)
= (GRP Delay) + (BFM Delay) + (GLB Delay)
= (tgrpm) + (tbfmg) + (tandhs + t4ptcom + tmbp)
= (#65) + (#67) + (#39 + #42 + #45)
= (2.6) + (3.3) + (2.6 + 0.5 + 0.0)
= 9.0 ns
BFM I/O to internal tri-state Enable/Disable
= (BFM Input Path Delay) + (GLB Delay, 1PT) + (Tri-state Control Delay)
= (tidcom + tibp + tbfmi max) + (tandhs + t1pt + tmbp) + (tgrpmz)
= (#23 + #26 + #61) + (#39 + #41 + #45) + (#66)
= (0.3 + 0.4 + 1.0) + (2.6 + 1.9 + 0.0) + (3.6)
= 9.8 ns
tsu1
= (BFM Input Path Delay) + (GLB Setup Time) - (Min. Global Clock Delay)
= (tidcom + tibp + tbfmi max) + (tandhs + t4ptreg + tmsu) – (tgck min)
= (#23 + #26 + #61) + (#39 + #43 + #48) – (#78)
= (0.3 + 0.4 + 1.0) + (2.6 + 1.4 + 2.7) – (3.9)
= 4.5 ns
1/Fmax = (Global Clk to MC Output) + (Local Feedback) + (GLB Setup Time)
= (tmco) + (tfloc) + (tandhs + tptsa + tmsu)
= (#47) + (#54) + (#39 + #44 + #48)
= (0.2) + (0.1) + (2.6 + 2.4 + 2.7)
= 8.0 ns
Fmax
= 125 MHz
Note: Calculations are based upon timing specifications for the ispLSI 81080V-125L
18
Specifications ispLSI 81080V
Power Consumption
Power consumption in the ispLSI 81080V device depends on two primary factors: the speed at which the
device is operating and the number of product terms
used. The product terms have a fuse-selectable speed/
power tradeoff setting. Each group of four product terms
has a single speed/power tradeoff control fuse that acts
on the complete group of four. The fast “high-speed”
setting operates product terms at their normal full power
consumption. For portions of the logic that can tolerate
longer propagation delays, selecting the slower “lowpower” setting will significantly reduce the power
dissipation for these product terms. Figure 10 shows the
relationship between power and operating speed.
Figure 10. Typical Device Power Consumption vs fmax
1300
1200
1100
1000
ICC (mA)
900
800
ispLSI 81080V
700
600
Turbo
Non-Turbo
500
400
300
200
0
10
20
30
40
50
60
70
80
90 100 110 120 130
fmax (MHz)
Notes: Configuration of 54 20-bit counters
Typical current at 3.3V, 25¡ C
ICC can be estimated for the ispLSI 81080V using the following equation:
ICC = 45.0 + (# of Turbo PTs * 0.25) + (# of Non-Turbo PTs * 0.11) + (# of Macrocells Used * Fmax * AF * .043)
# of Turbo PTs = Number of Turbo Product Terms Used in Design
# of Non-Turbo PTs = Number of Non-Turbo Product Terms Used in Design
fmax = Maximum Operating Frequency
AF (Activity Factor) =
Average Macrocell Toggle Frequency
Fmax
Note: An Activity Factor of 1.0 means all macrocell registers toggle at fmax. An Activity Factor of 0.5 means the
average macrocell register toggles at half of fmax.
The ICC estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption of two GLB loads
on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions
and the program in the device, the actual ICC should be verified.
0127/81080V
19
Specifications ispLSI 81080V
Signal Descriptions
Signal Name
CLK0, CLK1,
CLK2
Description
Dedicated clock input for the GLB registers only. These clock inputs are connected to one of the clock
inputs of all GLB registers in the device.
CLKEN
Dedicated clock enable input for the GLB registers only. This input is available as a clock enable for
each GLB register in the device. Use of the clock enable input eliminates the need for the user to gate
the clock to the register.
GND
Ground (GND)
GOE0, GOE1,
GOE2, GOE3
Global Output Enable inputs.
SET/RESET
Dedicated reset/preset pin connected to ALL registers in the device, GLB registers and I/O registers.
Each register can independently choose to be reset or preset when this signal goes active. The active
polarity is user-selectable.
IOCLKEN
Dedicated clock enable input for the I/O registers only. This input is available as a clock enable input for
all I/O registers in the device. Use of the clock enable input eliminates the need for the user to tie the
clock to the I/O register.
I/O
Input/Output – These are the general purpose I/O used by the logic array.
EPEN
Embedded Port Enable Pin – When this pin is high, the port is enabled. When this pin is low, the
state machine is held at reset asynchronously and TCK, TMS and TDI are ignored.
TMS
Input – This signal is the Test Mode Select input signal.
QIOCLK0,
QIOCLK1,
QIOCLK2,
QIOCLK3
Dedicated clock inputs for the I/O registers only. These clock inputs are connected to the I/O registers
on the same side of the device only, they are not connected to all of the I/O registers. Use of these
quadrant I/O clocks gives the fastest tco from the device.
TCK
Input – This signal is the Test Clock input signal.
TDI
Input – This signal is the Test Data input signal.
TDO
Output – This signal is the Test Data Out Output Signal.
TOE
Test Output Enable. Tristates all I/O pins when a logic low is driven.
VCC
Vcc
VCCIO
Power supply for the output drivers. The internal logic of the device is connected to VCC which is
always 3.3V. The output drivers are connected to VCCIO which can be equal to VCC or 2.5V. This
allows the output drivers to be powered from 2.5V, for example, to interface directly with another 2.5V
device.
NC1
No connect.
1. NC pins are not to be connected to any active signals, VCC or GND.
20
Specifications ispLSI 81080V
Signal Locations
272-Ball BGA
Signal Name
QIOCLK0, QIOCLK1,
QIOCLK2, QIOCLK3
Y8, M20, C8, N2
492-Ball BGA
AE14, P22, A15, N3
CLK0, CLK1, CLK2
Y9, P18, D8
AC15, R24, B15
CLKEN
V9
AB17
IOCLKEN
B9
E16
EPEN
C17
B26
TCK
A4
A2
TDI
U5
AF1
TDO
C4
B3
TMS
W4
AC4
GOE0, GOE1,
GOE2, GOE3
Y10, M19, C9, N1
AF15, P23, D16, N5
TOE
L3
L5
SET/RESET
P3
P2
VCC
D9, D10, D11, D12, J4, J17, K4, K17, L4, L17,
M4, M17, U9, U10, U11, U12
E9, E12, E15, E18, F5, F10, F17, F22, G5, G22,
K5, K22, L22, M5, N22, P5, R22, T5, U5, U22,
Y5, Y22, AA5, AA10, AA17, AA22, AB9, AB12,
AB15, AB18
VCCIO
A7, A8, A20, B16, C5, C12, E4, G20, H4, M1,
N17, U2, U20, V2, V6, W7, W8, W16, W19, Y13
E8, E13, E19, E20, F7, F8, F20, J6, J21, K3,
L24, N1, P24, T3, U25, V6, Y23, AA7, AA8,
AA20, AB8, AB14, AB19, AB20
GND
D4, D16, D17, J9, J10, J11, J12, K9, K10, K11,
K12, L9, L10, L11, L12, M9, M10, M11, M12,
U4, U17
E5, E11, E14, E22, F6, F21, L11, L12, L13, L14,
L15, L16, M11, M12, M13, M14, M15, M16, N11,
N12, N13, N14, N15, N16, P11, P12, P13, P14,
P15, P16, R11, R12, R13, R14, R15, R16, T11,
T12, T13, T14, T15, T16, AA6, AA21, AB5,
AB13, AB16, AB22
NC1
A9, V17, W9
A16, C2, E17, G21, Y21, AA9, AB4, AB10,
AD15, AF25
1. NC pins are not to be connected to any active signals, VCC or GND.
21
Specifications ispLSI 81080V
I/O Pin Locations (272-Ball BGA Package)
Signal
I/O G0 <0>
I/O G0 <1>
I/O G0 <2>
I/O G0 <3>
I/O G0 <4>
I/O G0 <5>
I/O G0 <6>
I/O G0 <7>
I/O G0 <8>
I/O G0 <9>
I/O G0 <10>
I/O G0 <11>
I/O G0 <12>
I/O G0 <13>
I/O G0 <14>
I/O G0 <15>
I/O G0 <16>
I/O G0 <17>
I/O G0 <18>
I/O G0 <19>
I/O G0 <20>
I/O G0 <21>
I/O G0 <22>
I/O G0 <23>
I/O G2 <0>
I/O G2 <1>
I/O G2 <2>
I/O G2 <3>
I/O G2 <4>
I/O G2 <5>
I/O G2 <6>
I/O G2 <7>
I/O G2 <8>
I/O G2 <9>
I/O G2 <10>
I/O G2 <11>
I/O G2 <12>
I/O G2 <13>
I/O G2 <14>
BGA
V4
Y3
Y2
W3
Y1
W2
W1
V3
V1
U3
R4
T4
U19
R17
V20
V19
U18
V18
T17
W20
Y20
Y19
W18
Y18
U1
T3
T2
T1
R3
R2
R1
P4
P2
N4
N3
P1
N18
N19
N20
Signal
I/O G2 <15>
I/O G2 <16>
I/O G2 <17>
I/O G2 <18>
I/O G2 <19>
I/O G2 <20>
I/O G2 <21>
I/O G2 <22>
I/O G2 <23>
I/O G3 <0>
I/O G3 <1>
I/O G3 <2>
I/O G3 <3>
I/O G3 <4>
I/O G3 <5>
I/O G3 <6>
I/O G3 <7>
I/O G3 <8>
I/O G3 <9>
I/O G3 <10>
I/O G3 <11>
I/O G3 <12>
I/O G3 <13>
I/O G3 <14>
I/O G3 <15>
I/O G3 <16>
I/O G3 <17>
I/O G3 <18>
I/O G3 <19>
I/O G3 <20>
I/O G3 <21>
I/O G3 <22>
I/O G3 <23>
I/O G4 <0>
I/O G4 <1>
I/O G4 <2>
I/O G4 <3>
I/O G4 <4>
I/O G4 <5>
BGA
P19
P17
P20
R20
R19
R18
T20
T19
T18
H2
H1
J3
J2
J1
K3
K2
K1
L2
L1
M2
M3
M18
L20
L19
L18
K20
K19
K18
J20
H20
J19
H19
J18
G2
G1
H3
G3
G4
F3
Signal
BGA
I/O G4 <6>
I/O G4 <7>
I/O G4 <8>
I/O G4 <9>
I/O G4 <10>
I/O G4 <11>
I/O G4 <12>
I/O G4 <13>
I/O G4 <14>
I/O G4 <15>
I/O G4 <16>
I/O G4 <17>
I/O G4 <18>
I/O G4 <19>
I/O G4 <20>
I/O G4 <21>
I/O G4 <22>
I/O G4 <23>
I/O G5 <0>
I/O G5 <1>
I/O G5 <2>
I/O G5 <3>
I/O G5 <4>
I/O G5 <5>
I/O G5 <6>
I/O G5 <7>
I/O G5 <8>
I/O G5 <9>
I/O G5 <10>
I/O G5 <11>
I/O G5 <12>
I/O G5 <13>
I/O G5 <14>
I/O G5 <15>
I/O G5 <16>
I/O G5 <17>
I/O G5 <18>
I/O G5 <19>
I/O G5 <20>
22
F1
F2
F4
E1
E2
E3
D20
F17
E19
G17
G18
F18
E20
F19
H17
F20
H18
G19
A3
B2
B3
A2
A1
B1
D3
D2
C3
C2
D1
C1
D19
E18
C20
B20
A19
C19
D18
B19
C18
Signal
I/O G5 <21>
I/O G5 <22>
I/O G5 <23>
I/O B1 <0>
I/O B1 <1>
I/O B1 <2>
I/O B1 <3>
I/O B1 <4>
I/O B1 <5>
I/O B1 <6>
I/O B1 <7>
I/O B1 <8>
I/O B1 <9>
I/O B1 <10>
I/O B1 <11>
I/O B1 <12>
I/O B1 <13>
I/O B1 <14>
I/O B1 <15>
I/O B1 <16>
I/O B1 <17>
I/O B1 <18>
I/O B1 <19>
I/O B1 <20>
I/O B1 <21>
I/O B1 <22>
I/O B1 <23>
I/O B5 <0>
I/O B5 <1>
I/O B5 <2>
I/O B5 <3>
I/O B5 <4>
I/O B5 <5>
I/O B5 <6>
I/O B5 <7>
I/O B5 <8>
I/O B5 <9>
I/O B5 <10>
I/O B5 <11>
BGA
E17
B18
A18
Y4
V5
W5
Y5
U6
U7
W6
V7
Y6
Y7
U8
V8
B8
C7
D7
B7
B6
C6
A6
D6
B5
A5
D5
B4
V10
W10
Y11
W11
V11
Y12
W12
V12
W13
U13
V13
Y14
Signal
I/O B5 <12>
I/O B5 <13>
I/O B5 <14>
I/O B5 <15>
I/O B5 <16>
I/O B5 <17>
I/O B5 <18>
I/O B5 <19>
I/O B5 <20>
I/O B5 <21>
I/O B5 <22>
I/O B5 <23>
I/O B7 <0>
I/O B7 <1>
I/O B7 <2>
I/O B7 <3>
I/O B7 <4>
I/O B7 <5>
I/O B7 <6>
I/O B7 <7>
I/O B7 <8>
I/O B7 <9>
I/O B7 <10>
I/O B7 <11>
I/O B7 <12>
I/O B7 <13>
I/O B7 <14>
I/O B7 <15>
I/O B7 <16>
I/O B7 <17>
I/O B7 <18>
I/O B7 <19>
I/O B7 <20>
I/O B7 <21>
I/O B7 <22>
I/O B7 <23>
BGA
B14
D13
B13
A13
A12
B12
B11
A11
C11
B10
A10
C10
W14
V14
U14
Y15
W15
V15
U15
Y16
V16
U16
W17
Y17
B17
A17
C16
D15
C15
A16
B15
D14
C14
A15
A14
C13
Specifications ispLSI 81080V
I/O Pin Locations (492-Ball BGA Package)
Signal
I/O G0 <0>
I/O G0 <1>
I/O G0 <2>
I/O G0 <3>
I/O G0 <4>
I/O G0 <5>
I/O G0 <6>
I/O G0 <7>
I/O G0 <8>
I/O G0 <9>
I/O G0 <10>
I/O G0 <11>
I/O G0 <12>
I/O G0 <13>
I/O G0 <14>
I/O G0 <15>
I/O G0 <16>
I/O G0 <17>
I/O G0 <18>
I/O G0 <19>
I/O G0 <20>
I/O G0 <21>
I/O G0 <22>
I/O G0 <23>
I/O G1 <0>
I/O G1 <1>
I/O G1 <2>
I/O G1 <3>
I/O G1 <4>
I/O G1 <5>
I/O G1 <6>
I/O G1 <7>
I/O G1 <8>
I/O G1 <9>
I/O G1 <10>
I/O G1 <11>
I/O G1 <12>
I/O G1 <13>
I/O G1 <14>
I/O G1 <15>
I/O G1 <16>
I/O G1 <17>
I/O G1 <18>
I/O G1 <19>
I/O G1 <20>
I/O G1 <21>
I/O G1 <22>
I/O G1 <23>
I/O G2 <0>
I/O G2 <1>
I/O G2 <2>
I/O G2 <3>
I/O G2 <4>
I/O G2 <5>
I/O G2 <6>
I/O G2 <7>
I/O G2 <8>
I/O G2 <9>
I/O G2 <10>
I/O G2 <11>
I/O G2 <12>
I/O G2 <13>
I/O G2 <14>
I/O G2 <15>
I/O G2 <16>
I/O G2 <17>
I/O G2 <18>
I/O G2 <19>
I/O G2 <20>
I/O G2 <21>
I/O G2 <22>
I/O G2 <23>
BGA
AA4
AA3
AA2
AA1
Y4
Y3
Y2
Y1
W4
W3
W2
U6
U21
Y26
Y25
Y24
V21
AA26
AA25
AA24
AA23
AB26
AB25
AB24
T2
W5
U1
U2
U3
U4
V1
V5
V2
V3
V4
W1
W23
W24
W25
W26
V22
V23
V24
V25
V26
W22
U23
U24
T4
T1
W6
R2
R1
R3
R4
R5
P1
P3
P4
N4
P26
P25
R23
T22
R26
R25
T26
T23
W21
T24
T25
U26
Signal
I/O G3 <0>
I/O G3 <1>
I/O G3 <2>
I/O G3 <3>
I/O G3 <4>
I/O G3 <5>
I/O G3 <6>
I/O G3 <7>
I/O G3 <8>
I/O G3 <9>
I/O G3 <10>
I/O G3 <11>
I/O G3 <12>
I/O G3 <13>
I/O G3 <14>
I/O G3 <15>
I/O G3 <16>
I/O G3 <17>
I/O G3 <18>
I/O G3 <19>
I/O G3 <20>
I/O G3 <21>
I/O G3 <22>
I/O G3 <23>
I/O G4 <0>
I/O G4 <1>
I/O G4 <2>
I/O G4 <3>
I/O G4 <4>
I/O G4 <5>
I/O G4 <6>
I/O G4 <7>
I/O G4 <8>
I/O G4 <9>
I/O G4 <10>
I/O G4 <11>
I/O G4 <12>
I/O G4 <13>
I/O G4 <14>
I/O G4 <15>
I/O G4 <16>
I/O G4 <17>
I/O G4 <18>
I/O G4 <19>
I/O G4 <20>
I/O G4 <21>
I/O G4 <22>
I/O G4 <23>
I/O G5 <0>
I/O G5 <1>
I/O G5 <2>
I/O G5 <3>
I/O G5 <4>
I/O G5 <5>
I/O G5 <6>
I/O G5 <7>
I/O G5 <8>
I/O G5 <9>
I/O G5 <10>
I/O G5 <11>
I/O G5 <12>
I/O G5 <13>
I/O G5 <14>
I/O G5 <15>
I/O G5 <16>
I/O G5 <17>
I/O G5 <18>
I/O G5 <19>
I/O G5 <20>
I/O G5 <21>
I/O G5 <22>
I/O G5 <23>
BGA
Signal
BGA
Signal
BGA
Signal
BGA
K2
K1
L2
H6
L3
L4
L1
M2
M1
M3
M4
N2
N23
N24
N26
N25
M22
M23
M24
M26
H21
M25
L26
L23
K4
H5
J1
J2
J3
J4
H1
J5
H2
H3
H4
K6
H26
J23
J24
J25
J22
J26
K23
K24
K25
H22
K26
L25
E4
E3
E2
E1
F4
F3
F2
F1
G4
G3
G2
G1
K21
H25
H24
H23
G26
G25
G24
G23
F26
F25
F24
F23
I/O B0 <0>
I/O B0 <1>
I/O B0 <2>
I/O B0 <3>
I/O B0 <4>
I/O B0 <5>
I/O B0 <6>
I/O B0 <7>
I/O B0 <8>
I/O B0 <9>
I/O B0 <10>
I/O B0 <11>
I/O B0 <12>
I/O B0 <13>
I/O B0 <14>
I/O B0 <15>
I/O B0 <16>
I/O B0 <17>
I/O B0 <18>
I/O B0 <19>
I/O B0 <20>
I/O B0 <21>
I/O B0 <22>
I/O B0 <23>
I/O B1 <0>
I/O B1 <1>
I/O B1 <2>
I/O B1 <3>
I/O B1 <4>
I/O B1 <5>
I/O B1 <6>
I/O B1 <7>
I/O B1 <8>
I/O B1 <9>
I/O B1 <10>
I/O B1 <11>
I/O B1 <12>
I/O B1 <13>
I/O B1 <14>
I/O B1 <15>
I/O B1 <16>
I/O B1 <17>
I/O B1 <18>
I/O B1 <19>
I/O B1 <20>
I/O B1 <21>
I/O B1 <22>
I/O B1 <23>
I/O B2 <0>
I/O B2 <1>
I/O B2 <2>
I/O B2 <3>
I/O B2 <4>
I/O B2 <5>
I/O B2 <6>
I/O B2 <7>
I/O B2 <8>
I/O B2 <9>
I/O B2 <10>
I/O B2 <11>
I/O B2 <12>
I/O B2 <13>
I/O B2 <14>
I/O B2 <15>
I/O B2 <16>
I/O B2 <17>
I/O B2 <18>
I/O B2 <19>
I/O B2 <20>
I/O B2 <21>
I/O B2 <22>
I/O B2 <23>
Y6
AB1
AB2
AB3
AC1
AC2
AC3
AD1
AD2
AD3
AE1
AB6
E6
A1
C3
D4
G6
F9
B2
B1
D3
C1
D2
D1
AE2
AF2
AE3
AF3
AD4
AE4
AF4
AC5
AD5
AE5
AB7
AF5
B6
E7
C6
D6
A5
B5
C5
D5
A4
B4
C4
A3
AC6
AD6
AE6
AF6
AC7
AD7
AE7
AF7
AC8
AD8
AE8
AF8
B9
C9
D9
A8
B8
C8
D8
A7
B7
C7
D7
A6
I/O B3 <0>
I/O B3 <1>
I/O B3 <2>
I/O B3 <3>
I/O B3 <4>
I/O B3 <5>
I/O B3 <6>
I/O B3 <7>
I/O B3 <8>
I/O B3 <9>
I/O B3 <10>
I/O B3 <11>
I/O B3 <12>
I/O B3 <13>
I/O B3 <14>
I/O B3 <15>
I/O B3 <16>
I/O B3 <17>
I/O B3 <18>
I/O B3 <19>
I/O B3 <20>
I/O B3 <21>
I/O B3 <22>
I/O B3 <23>
I/O B4 <0>
I/O B4 <1>
I/O B4 <2>
I/O B4 <3>
I/O B4 <4>
I/O B4 <5>
I/O B4 <6>
I/O B4 <7>
I/O B4 <8>
I/O B4 <9>
I/O B4 <10>
I/O B4 <11>
I/O B4 <12>
I/O B4 <13>
I/O B4 <14>
I/O B4 <15>
I/O B4 <16>
I/O B4 <17>
I/O B4 <18>
I/O B4 <19>
I/O B4 <20>
I/O B4 <21>
I/O B4 <22>
I/O B4 <23>
I/O B5 <0>
I/O B5 <1>
I/O B5 <2>
I/O B5 <3>
I/O B5 <4>
I/O B5 <5>
I/O B5 <6>
I/O B5 <7>
I/O B5 <8>
I/O B5 <9>
I/O B5 <10>
I/O B5 <11>
I/O B5 <12>
I/O B5 <13>
I/O B5 <14>
I/O B5 <15>
I/O B5 <16>
I/O B5 <17>
I/O B5 <18>
I/O B5 <19>
I/O B5 <20>
I/O B5 <21>
I/O B5 <22>
I/O B5 <23>
AC9
AD9
AE9
AF9
AC10
AD10
AE10
AF10
AE11
AD11
AB11
AC11
A12
E10
B12
A11
D11
C11
B11
A10
B10
C10
D10
A9
AF11
AE12
AF12
AD12
AC12
AE13
AF13
AD13
AC13
AC14
AD14
AF14
C15
D15
B14
A14
C14
D14
D13
C13
A13
B13
D12
C12
AE15
AF16
AC16
AD16
AE16
AF17
AE17
AD17
AC17
AF18
AE18
AD18
B19
A19
D18
C18
B18
A18
D17
C17
B17
A17
B16
C16
I/O B6 <0>
I/O B6 <1>
I/O B6 <2>
I/O B6 <3>
I/O B6 <4>
I/O B6 <5>
I/O B6 <6>
I/O B6 <7>
I/O B6 <8>
I/O B6 <9>
I/O B6 <10>
I/O B6 <11>
I/O B6 <12>
I/O B6 <13>
I/O B6 <14>
I/O B6 <15>
I/O B6 <16>
I/O B6 <17>
I/O B6 <18>
I/O B6 <19>
I/O B6 <20>
I/O B6 <21>
I/O B6 <22>
I/O B6 <23>
I/O B7 <0>
I/O B7 <1>
I/O B7 <2>
I/O B7 <3>
I/O B7 <4>
I/O B7 <5>
I/O B7 <6>
I/O B7 <7>
I/O B7 <8>
I/O B7 <9>
I/O B7 <10>
I/O B7 <11>
I/O B7 <12>
I/O B7 <13>
I/O B7 <14>
I/O B7 <15>
I/O B7 <16>
I/O B7 <17>
I/O B7 <18>
I/O B7 <19>
I/O B7 <20>
I/O B7 <21>
I/O B7 <22>
I/O B7 <23>
I/O B8 <0>
I/O B8 <1>
I/O B8 <2>
I/O B8 <3>
I/O B8 <4>
I/O B8 <5>
I/O B8 <6>
I/O B8 <7>
I/O B8 <8>
I/O B8 <9>
I/O B8 <10>
I/O B8 <11>
I/O B8 <12>
I/O B8 <13>
I/O B8 <14>
I/O B8 <15>
I/O B8 <16>
I/O B8 <17>
I/O B8 <18>
I/O B8 <19>
I/O B8 <20>
I/O B8 <21>
I/O B8 <22>
I/O B8 <23>
AC18
AF19
AE19
AA19
AD19
AC19
AF20
AE20
AD20
AC20
AF21
AE21
A22
D21
C21
B21
A21
D20
C20
B20
A20
F19
D19
C19
AD21
AC21
AF22
AE22
AD22
AC22
AF23
AE23
AD23
AF24
AE24
AD24
A26
D23
B25
A25
B24
A24
C23
B23
A23
D22
C22
B22
AB21
AF26
AE25
AC23
AE26
AD25
AC24
AD26
AB23
AC25
AC26
AA18
E26
E25
E24
E23
D26
D25
D24
C26
C25
C24
E21
F18
23
Specifications ispLSI 81080V
Signal Configuration
ispLSI 81080V 272-Ball BGA Signal Diagram
20
19
18
17
16
15
14
13
12
11
10
I/O G5 I/O G5 I/O B7 I/O B7 I/O B7 I/O B7 I/O B5 I/O B5 I/O B5 I/O B5
<16> <23> <13> <17> <21> <22> <15> <16> <19> <22>
9
8
7
6
5
3
2
1
I/O G5 I/O G5 I/O G5
<0>
<3>
<4>
A
I/O B1 I/O B1 I/O B1 I/O B1 I/O B1 I/O G5 I/O G5 I/O G5
<1>
<5>
<12> <15> <16> <20> <23> <2>
B
I/O B1 I/O B1
I/O G5 I/O G5 I/O G5
VCCIO TDO
<13> <17>
<8>
<9> <11>
C
I/O G5 I/O G5 I/O G5
I/O B1 I/O B1 I/O B1
GND
<6>
<7> <10>
<14> <19> <22>
D
I/O G4 I/O G4 I/O G4
<11> <10> <9>
E
ispLSI 81080V
I/O G4 I/O G4 I/O G4 I/O G4
<8>
<5>
<7>
<6>
F
Bottom View
I/O G4 I/O G4 I/O G4 I/O G4
<3>
<0>
<1>
<4>
G
I/O G4 I/O G3 I/O G3
<2>
<0>
<1>
H
GND
VCC I/O G3 I/O G3 I/O G3
<2>
<3>
<4>
J
GND GND
GND
VCC I/O G3 I/O G3 I/O G3
<6>
<7>
<5>
K
GND
GND GND
GND
VCC
TOE I/O G3 I/O G3
<8>
<9>
L
GND
GND GND
GND
VCC I/O G3 I/O G3 VCCIO
<11> <10>
M
I/O G2 I/O G2 I/O G2
VCCIO
<14> <13> <12>
I/O G2 I/O G2
<9> <10>
GOE
3
N
P
I/O G2 I/O G2 CLK 1 I/O G2
<17> <15>
<16>
I/O G2 SET/ I/O G2 I/O G2
<7> RESET <8> <11>
P
R
I/O G2 I/O G2 I/O G2 I/O G0
<18> <19> <20> <13>
I/O G0 I/O G2 I/O G2 I/O G2
<10> <4>
<5>
<6>
R
T
I/O G2 I/O G2 I/O G2 I/O G0
<21> <22> <23> <18>
I/O G0 I/O G2 I/O G2 I/O G2
<11> <1>
<2>
<3>
T
U
VCCIO
I/O G0
I/O G2
VCCIO
<9>
<0>
U
V
I/O G0 I/O G0 I/O G0 NC1
<14> <15> <17>
I/O B7 I/O B7 I/O B7 I/O B5 I/O B5 I/O B5 I/O B5
I/O B1 I/O B1 VCCIO I/O B1 I/O G0 I/O G0 VCCIO I/O G0
CLKEN
<8>
<5>
<1> <10> <7>
<4>
<0>
<1>
<0>
<7>
<8>
<11>
<7>
V
W
I/O G0 VCCIO I/O G0 I/O B7 VCCIO I/O B7 I/O B7 I/O B5 I/O B5 I/O B5 I/O B5
<19>
<22> <10>
<4>
<0>
<8>
<6>
<3>
<1>
Y
I/O G0 I/O G0 I/O G0 I/O B7 I/O B7 I/O B7 I/O B5
I/O B5 I/O B5 GOE CLK 0
VCCIO
<20> <21> <23> <11>
<7>
<3> <11>
<5>
<2>
0
A
VCCIO
B
I/O G5 I/O G5 I/O G5 I/O B7
I/O B7 I/O B5 I/O B5 I/O B5 I/O B5 I/O B5
VCCIO
<15> <19> <22> <12>
<18> <12> <14> <17> <18> <21>
C
I/O G5 I/O G5 I/O G5
I/O B7 I/O B7 I/O B7 I/O B7
I/O B5 I/O B5 GOE
EPEN
VCCIO
2
<14> <17> <20>
<14> <16> <20> <23>
<20> <23>
D
I/O G4 I/O G5 I/O G5
GND
<12> <12> <18>
E
I/O G4 I/O G4 I/O G5 I/O G5
<18> <14> <13> <21>
F
I/O G4 I/O G4 I/O G4 I/O G4
<21> <19> <17> <13>
G
VCCIO
H
I/O G3 I/O G3 I/O G4 I/O G4
<20> <22> <22> <20>
J
I/O G3 I/O G3 I/O G3 VCC
<19> <21> <23>
GND
GND GND
K
I/O G3 I/O G3 I/O G3
VCC
<16> <17> <18>
GND
L
I/O G3 I/O G3 I/O G3
VCC
<13> <14> <15>
M
QIOCLK
1
GOE I/O G3 VCC
1
<12>
N
20
GND
I/O B7 I/O B7 I/O B5
<15> <19> <13>
VCC
17
QIOCLK
2
VCC CLK 2
TCK
VCCIO
I/O G0 I/O G0
I/O B7 I/O B7 I/O B7 I/O B5
VCC
GND
<12> <16>
<9>
<6>
<2>
<9>
18
VCC
IOCLKEN
VCCIO VCCIO
VCCIO
I/O G4 I/O G4 I/O G4
<23> <16> <15>
19
VCC
NC1
I/O B1 I/O B1
<18> <21>
4
16
15
14
13
12
VCC
11
VCC
10
VCC
NC1
9
I/O B1 I/O B1 I/O B1
<10> <5>
<4>
TDI
VCCIO VCCIO I/O B1 I/O B1
TMS I/O G0 I/O G0 I/O G0
<3>
<5>
<6>
W
I/O B1 I/O B1 I/O B1 I/O B1 I/O G0 I/O G0 I/O G0
<4>
<9>
<8>
<3>
<0>
<1>
<2>
Y
<6>
QIOCLK
0
8
GND
QIOCLK
3
7
6
<2>
5
4
3
2
1
272 BGA/81080v.eps
1. NCs are not to be connected to any active signals, Vcc or GND.
Note: Ball A1 indicator dot on top side of package.
24
Specifications ispLSI 81080V
Signal Configuration
ispLSI 81080V 492-Ball BGA Signal Diagram
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
A
I/O B7 I/O B7 I/O B7 I/O B7 I/O B6 I/O B6 I/O B6 I/O B5 I/O B5 I/O B5
<12> <15> <17> <20> <12> <16> <20> <13> <17> <21>
B
I/O B7 I/O B7 I/O B7 I/O B7 I/O B6 I/O B6 I/O B5 I/O B5 I/O B5 I/O B5
I/O B4 I/O B4 I/O B3 I/O B3 I/O B3 I/O B2 I/O B2 I/O B2 I/O B1 I/O B1 I/O B1
TDO
EPEN
CLK2
<14> <16> <19> <23> <15> <19> <12> <16> <20> <22>
<14> <21> <14> <18> <20> <12> <16> <20> <12> <17> <21>
C
I/O B8 I/O B8 I/O B8 I/O B7 I/O B7 I/O B6 I/O B6 I/O B6 I/O B5 I/O B5 I/O B5 I/O B4 I/O B4 I/O B4 I/O B4 I/O B3 I/O B3 I/O B2 I/O B2 I/O B2 I/O B1 I/O B1 I/O B1 I/O B0
<19> <20> <21> <18> <22> <14> <18> <23> <15> <19> <23> <12> <16> <19> <23> <17> <21> <13> <17> <21> <14> <18> <22> <14>
QIOCLK
2
1
NC
2
1
I/O B4 I/O B4 I/O B3 I/O B3 I/O B3 I/O B3 I/O B2 I/O B2 I/O B2 I/O B1 I/O B1 I/O B1 TCK I/O B0
<15> <20> <12> <15> <19> <23> <15> <19> <23> <16> <20> <23>
<13>
A
I/O B0 I/O B0
<18> <19>
B
I/O B0
<21>
C
D
I/O B8 I/O B8 I/O B8 I/O B7 I/O B7 I/O B6 I/O B6 I/O B6 I/O B5 I/O B5
I/O B4 I/O B4 I/O B4 I/O B4 I/O B3 I/O B3 I/O B2 I/O B2 I/O B2 I/O B1 I/O B1 I/O B0 I/O B0 I/O B0 I/O B0
GOE 2
<16> <17> <18> <13> <21> <13> <17> <22> <14> <18>
<13> <17> <18> <22> <16> <22> <14> <18> <22> <15> <19> <15> <20> <22> <23>
D
E
I/O B8 I/O B8 I/O B8 I/O B8
I/O B8
GND
VCCIO VCCIO VCC
<12> <13> <14> <15>
<22>
I/O B3
I/O B1 I/O B0
I/O G5 I/O G5 I/O G5 I/O G5
VCC VCCIO
GND
<13>
<13> <12>
<0>
<1>
<2>
<3>
E
F
I/O G5 I/O G5 I/O G5 I/O G5
VCC
<20> <21> <22> <23>
GND VCCIO
I/O G5 I/O G5 I/O G5 I/O G5
<5>
<6>
<7>
<4>
F
G
I/O G5 I/O G5 I/O G5 I/O G5
VCC
<16> <17> <18> <19>
NC1
I/O B0
I/O G5 I/O G5 I/O G5 I/O G5
VCC
<16>
<8>
<9> <10> <11>
G
H
I/O G4 I/O G5 I/O G5 I/O G5 I/O G4 I/O G3
<12> <13> <14> <15> <21> <20>
I/O G3 I/O G4 I/O G4 I/O G4 I/O G4 I/O G4
<8>
<6>
<3>
<1> <10> <9>
H
J
I/O G4 I/O G4 I/O G4 I/O G4 I/O G4
VCCIO
<17> <15> <14> <13> <16>
I/O G4 I/O G4 I/O G4 I/O G4 I/O G4
VCCIO
<5>
<4>
<3>
<2>
<7>
J
K
I/O G5
I/O G4 I/O G4 I/O G4 I/O G4
VCC
<12>
<22> <20> <19> <18>
I/O G4 VCC I/O G4 VCCIO I/O G3 I/O G3
<0>
<1>
<11>
<0>
K
L
I/O G3 I/O G4
I/O G3
VCCIO
VCC
<22> <23>
<23>
GND
GND
GND
GND
GND
GND
TOE I/O G3 I/O G3 I/O G3 I/O G3
<5>
<4>
<2>
<6>
L
M
I/O G3 I/O G3 I/O G3 I/O G3 I/O G3
<19> <21> <18> <17> <16>
GND
GND
GND
GND
GND
GND
VCC I/O G3 I/O G3 I/O G3 I/O G3
<8>
<10> <9>
<7>
M
N
I/O G3 I/O G3 I/O G3 I/O G3
VCC
<14> <15> <13> <12>
GND
GND
GND
GND
GND
GND
GOE 3 I/O G2 QIOCLK I/O G3 VCCIO
3
<11>
<11>
N
P
I/O G2 I/O G2
VCCIO GOE 1 QIOCLK
<12> <13>
1
GND
GND
GND
GND
GND
GND
I/O G2 I/O G2 SET/ I/O G2
<10> <9> RESET <8>
P
R
I/O G2 I/O G2
I/O G2
CLK 1
VCC
<16> <17>
<14>
GND
GND
GND
GND
GND
GND
I/O G2 I/O G2 I/O G2 I/O G2 I/O G2
<7>
<6>
<5>
<3>
<4>
R
T
I/O G2 I/O G2 I/O G2 I/O G2 I/O G2
<18> <22> <21> <19> <15>
GND
GND
GND
GND
GND
GND
I/O G2
I/O G1 I/O G2
VCCIO
<0>
<0>
<1>
T
U
I/O G1 I/O G1
I/O G0
I/O G2
VCCIO
VCC
<23> <22>
<12>
<23>
I/O G0
I/O G1 I/O G1 I/O G1 I/O G1
VCC
<11>
<5>
<4>
<3>
<2>
U
V
I/O G1 I/O G1 I/O G1 I/O G1 I/O G1 I/O G0
<20> <19> <18> <17> <16> <16>
ispLSI 81080V
I/O G1 I/O G1 I/O G1 I/O G1 I/O G1
<8>
<6>
<7> <10> <9>
V
W
I/O G1 I/O G1 I/O G1 I/O G1 I/O G1 I/O G2
<15> <14> <13> <12> <21> <20>
Bottom View
I/O G2 I/O G1 I/O G0 I/O G0 I/O G0 I/O G1
<9> <10> <11>
<2>
<1>
<8>
W
Y
I/O G0 I/O G0 I/O G0
VCCIO VCC
<13> <14> <15>
NC1
I/O B0
I/O G0 I/O G0 I/O G0 I/O G0
VCC
<5>
<6>
<7>
<0>
<4>
Y
AA
I/O G0 I/O G0 I/O G0 I/O G0
VCC
<17> <18> <19> <20>
GND VCCIO
AB
I/O G0 I/O G0 I/O G0 I/O G8 GND I/O B8 VCCIO VCCIO VCC CLKEN GND
<21> <22> <23> <8>
<0>
AC
I/O B4 I/O B4 I/O B4 I/O B3 I/O B3 I/O B3 I/O B2 I/O B2 I/O B2 I/O B1
I/O B8 I/O B8 I/O B8 I/O B8 I/O B7 I/O B7 I/O B6 I/O B6 I/O B6 I/O B5 I/O B5
CLK 0
<5>
<1>
<9>
<5>
<0>
<8>
<2>
<9>
<8>
<4> <11> <4>
<0>
<8>
<4>
<0>
<7>
<10> <9>
<6>
<3>
AD
I/O B8 I/O B8 I/O B7 I/O B7 I/O B7 I/O B7 I/O B6 I/O B6 I/O B5 I/O B5 I/O B5
<4>
<0>
<8>
<4> <11> <7>
<3>
<7>
<5> <11> <8>
NC1
IOCLKEN
VCC
GND VCCIO VCC
GND
I/O B6 I/O B8
VCC
<21> <23>
VCC
I/O R0
VCCIO VCCIO GND
<17>
VCC
VCC
VCC
VCCIO
NC1
VCC
NC1 VCCIO VCCIO GND
VCC
I/O G0 I/O G0 I/O G0 I/O G0
<0>
<1>
<2>
<3>
AA
NC1
VCC VCCIO I/O B1 I/O B0 GND
<10> <11>
NC1 I/O B0 I/O B0 I/O B0
<3>
<2>
<1>
AB
I/O B0 I/O B0 I/O B0
<6>
<5>
<4>
AC
I/O B4 I/O B4 I/O B4 I/O B3 I/O B3 I/O B3 I/O B2 I/O B2 I/O B2 I/O B1 I/O B1 I/O B0 I/O B0 I/O B0
<10> <7>
<3>
<9>
<5>
<1>
<9>
<5>
<1>
<8>
<4>
<9>
<8>
<7>
AD
AE
I/O B8 I/O B8 I/O B7 I/O B7 I/O B7 I/O B6 I/O B6 I/O B6 I/O B5 I/O B5 I/O B5 I/O B5 QIOCLK I/O B4 I/O B4 I/O B3 I/O B3 I/O B3 I/O B2 I/O B2 I/O B2 I/O B1 I/O B1 I/O B1 I/O B1 I/O B0
0
<3> <11> <7>
<2> <10> <6>
<4>
<0>
<5>
<1>
<8>
<6>
<2> <10> <6>
<2>
<9>
<5>
<2>
<0> <10>
<4>
<2> <10> <7>
AE
AF
I/O B8
<1>
AF
NC1
I/O B6 I/O B8
VCC
<3> <11>
VCC VCCIO GND
NC1
VCC I/O B3
<10>
TMS
I/O B7 I/O B7 I/O B7 I/O B6 I/O B6 I/O B6 I/O B5 I/O B5 I/O B5 GOE 0 I/O B4 I/O B4 I/O B4 I/O B4 I/O B3 I/O B3 I/O B2 I/O B2 I/O B2 I/O B1 I/O B1 I/O B1 I/O B1
<9>
<6>
<2> <10> <6>
<1>
<9>
<5>
<1>
<11> <6>
<2>
<0>
<7>
<3> <11> <7>
<3> <11> <6>
<3>
<1>
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
1. NC pins are not to be connected to any active signals, VCC or GND.
Note: Ball A1 indicator dot on top side of package.
25
9
8
7
6
5
4
3
2
TDI
1
Specifications ispLSI 81080V
Part Number Description
ispLSI 81080V - XXX
X
XXXX
X
Device Family
Grade
Blank = Commercial
Device Number
Package
B272 = 272-Ball BGA
(Thermally Enhanced)
B492 = 492-Ball BGA
Speed
125 = 125 MHz fmax
90 = 90 MHz fmax
60 = 60 MHz fmax
Power
L = Low
0212/81080V
Ordering Information
COMMERCIAL
FAMILY
ispLSI
fmax (MHz)
tpd (ns)
ORDERING NUMBER
PACKAGE
125
8.5
ispLSI 81080V-125LB272
272-Ball BGA
125
8.5
ispLSI 81080V-125LB492
492-Ball BGA
90
10
ispLSI 81080V-90LB272
272-Ball BGA
90
10
ispLSI 81080V-90LB492
492-Ball BGA
60
15
ispLSI 81080V-60LB272
272-Ball BGA
60
15
ispLSI 81080V-60LB492
492-Ball BGA
Table 2-0041/81080V
26