LATTICE ISPLSI8840

ispLSI 8840
®
In-System Programmable
SuperBIG™ High Density PLD
• ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Features
• SuperBIG HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 5V Power Supply
— 45,000 PLD Gates/840 Macrocells
— Up to 312 I/O Pins Supporting 3.3V/5V I/O
— 1152 Registers
— High-Speed Global and Big Fast Megablock (BFM)
Interconnect
— Wide 20-Macrocell Generic Logic Block (GLB) for
High Performance
— Wide Input Gating (44 Inputs per GLB) for Fast
Counters, State Machines, Address Decoders, Etc.
— PCB-Efficient Ball Grid Array (BGA) Package
Options
2
Functional Block Diagram
12
I/O
12
I/O
12
I/O
12
I/O
12
I/O
12
I/O
12
I/O
Big Fast Megablock 0
12
I/O
12
I/O
Big Fast Megablock 1
12
I/O
12
I/O
Big Fast Megablock 2
12
I/O
®
• HIGH-PERFORMANCE E CMOS TECHNOLOGY
— fmax = 110 MHz Maximum Operating Frequency
— tpd = 8.5 ns Propagation Delay
— TTL Compatible Inputs and 3.3V/5V Outputs
— PCI Compatible Inputs, Outputs and Speed Grades
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Programmable Speed/Power Logic Path
Optimization
Global Routing Plane
12
I/O
Big Fast Megablock 3
12
I/O
• IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
12
I/O
Big Fast Megablock 4
12
I/O
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND
5V IN-SYSTEM PROGRAMMABLE
12
I/O
Big Fast Megablock 5
12
I/O
12
I/O
Big Fast Megablock 6
12
I/O
• ARCHITECTURE FEATURES
— Enhanced Pin-Locking Architecture, Symmetrical
Generic Logic Blocks Connected by Hierarchical
Big Fast Megablock and Global Routing Planes
— Product Term Sharing Array Supports up to 28
Product Terms per Macrocell Output
— Macrocells Support Concurrent Combinatorial and
Registered Functions
— Embedded Tristate Bus Can Be Used as an Internal
Tristate Bus or as an Extension of an External
Tristate Bus
— Macrocell and I/O Registers Feature Multiple Control
Options, Including Set, Reset and Clock Enable
— I/O Pins Support Programmable Bus Hold, Pull-Up,
Open-Drain and Slew Rate Options
— Separate VCCIO Power Supply for Output Drivers
Supports 5V or 3.3V Outputs
— I/O Cell Register Programmable as Input Register for
Fast Setup Time or Output Register for Fast Clock to
Output Time
Boundary
Scan
12
I/O
12
I/O
12
I/O
12
I/O
12
I/O
12
I/O
8840 block
ispLSI 8000 Family Description
The ispLSI 8000 Family of Register-Intensive, SuperBIG
In-System Programmable Logic Devices is based on Big
Fast Megablocks of 120 registered macrocells and a
Global Routing Plane (GRP) structure interconnecting
the Big Fast Megablocks. Each Big Fast Megablock
contains 120 registered macrocells arranged in six groups
of 20, a group of 20 being referred to as a Generic Logic
Block, or GLB. Within the Big Fast Megablock, a Big Fast
Megablock Routing Pool (BRP) interconnects the six
GLBs to each other and to 24 Big Fast Megablock I/O
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
8840_07
1
January 2000
Specifications ispLSI 8840
Functional Block Diagram
Figure 1. ispLSI 8840 Functional Block Diagram (Perspective)
Big Fast Megablock Routing Pool (BRP)
Big Fast Megablock Routing Pool (BRP)
Big Fast Megablock Routing Pool (BRP)
Big Fast Megablock Routing Pool (BRP)
Global Routing Plane (GRP) with Tristate Bus Lines
2
Specifications ispLSI 8840
ispLSI 8000 Family Description (Continued)
and the Global Routing Plane between the Big Fast
Megablocks. The Big Fast Megablock Routing Pool contains general purpose tracks which interconnect the six
GLBs within the Big Fast Megablock and dedicated
tracks for the signals from the Big Fast Megablock I/O
cells. The Global Routing Plane contains general purpose tracks that interconnect the Big Fast Megablocks
and also carry the signals from the I/Os connected to the
Global Routing Plane.
cells with optional I/O registers. The Global Routing
Plane which interconnects the Big Fast Megablocks has
an additional 144 global I/Os with optional I/O registers.
Outputs from the GLBs in a Big Fast Megablock can drive
both the Big Fast Megablock Routing Pool within the Big
Fast Megablock and the Global Routing Plane between
the Big Fast Megablocks. Switching resources are provided to allow signals in the Global Routing Plane to drive
any or all the Big Fast Megablocks in the device. This
mechanism allows fast, efficient connections, both within
the Big Fast Megablocks and between them.
Control signals for the I/O cell registers are generated
using an extra product term within each GLB, or using
dedicated input pins. Each GLB has two extra product
terms beyond the 80 available for the macrocell logic.
The first additional product term is used as an optional
shared product term clock for all the macrocells within the
GLB. The second additional product term is then routed
to an I/O Control Bus using a separate routing structure
from the Big Fast Megablock Routing Pool and Global
Routing Plane. Use of a separate control bus routing
structure allows the I/O registers to have many control
signals with no impact on the interconnection of the GLBs
and Big Fast Megablocks. The I/O Control Bus is split into
four quadrants, each servicing the I/O cell control requirements for one edge of the device. Signals in the
control bus can be independently selected by any or all
I/O cells to act as clock, clock enable, output enable,
reset or preset.
Each GLB contains 20 macrocells and a fully populated,
programmable AND-array with 82 logic product terms.
The GLB has 44 inputs from the Big Fast Megablock
Routing Pool which are available in both true and complement form for every product term. Up to 20 of these inputs
can be switched to provide local feedback into the GLB
for logic functions that require it. The 80 general-purpose
product terms can be grouped into 20 sets of four and
sent into a Product Term Sharing Array (PTSA) which
allows sharing up to a maximum of 28 product terms for
a single function. Alternatively, the PTSA can be bypassed for functions of four product terms or less.
The 20 registered macrocells in the GLB are driven by the
20 outputs from the PTSA or the PTSA bypass. Each
macrocell contains a programmable XOR gate, a programmable register/latch/toggle flip-flop and the
necessary clocks and control logic to allow combinatorial
or registered operation. Each macrocell has two outputs,
one output can be fed back inside the GLB to the ANDarray, while the other output drives both the Big Fast
Megablock Routing Pool and the Global Routing Plane.
This dual output capability from the macrocell allows
efficient use of the hardware resources. One output can
be a registered function for example, while the other
output can be an unrelated combinatorial function.
Each Big Fast Megablock has 24 I/O cells. The Global
Routing Pool has 144 I/O cells. Each I/O cell can be
configured as a combinatorial input, combinatorial output, registered input, registered output or bidirectional
I/O. I/O cell registers can be clocked from one of several
global, local or product term clocks which are selected
from the I/O control bus. A global and product term clock
enable is also provided, eliminating the need for the user
to gate the clock to the I/O cell registers. Reset and preset
for the I/O cell register is provided from both global and
product term signals. The polarity of all of these control
signals is selectable on an individual I/O cell basis. The
I/O cell register can be programmed to operate as a Dtype register or a D-type latch.
Macrocell registers can be clocked from one of several
global, local or product term clocks available on the
device. A global, local and product term clock enable is
also provided, eliminating the need to gate the clock to
the macrocell registers. Reset and preset for the macrocell
register is provided from both global and product term
signals. The polarity of all of these control signals is
selectable on an individual macrocell basis. The macrocell register can be programmed to operate as a D-type
register, a D-type flow-through latch or a T-type flip flop.
Inputs and outputs are PCI compatible. The input threshold is fixed at TTL levels. The output driver can source
4mA and sink 8mA. The output drivers have a separate
VCCIO power supply which is independent of the main
VCC supply for the device. This feature allows the output
drivers to run from either 5V or 3.3V while the device logic
is always powered from 5V. The output drivers also
provide individually programmable edge rates and open
The 20 outputs from the GLB can drive both the Big Fast
Megablock Routing Pool within the Big Fast Megablock
3
Specifications ispLSI 8840
participate in driving the embedded tristate bus. The
remaining two macrocells per GLB are used to generate
the internal tristate driver control signals on each data
byte (with parity). The embedded tristate bus can also be
configured as an extension of an external tristate bus
using the bidirectional capability of the I/O cells connected to the Global Routing Plane. The Global Routing
Plane I/Os 0-8 and 15-23 from each group (I/OGx as
defined in the I/O Pin Location Table) can connect to the
internal tristate bus as well as the unidirectional/nontristate global routing channels. I/Os 9-14 connect only to
the global routing channel.
ispLSI 8000 Family Description (Continued)
drain capability. A programmable pullup resistor is provided to tie off unused inputs and a programmable
bus-hold latch is available to hold tristate outputs in their
last valid state until the bus is driven again by another
device.
The ispLSI 8000 Family features 5V, non-volatile insystem programmability for both the logic and the
interconnect structures, providing the means to develop
truly reconfigurable systems. Programming is achieved
through the industry standard IEEE 1149.1-compliant
Boundary Scan interface using either the JTAG protocol
or Lattice proprietary ISP protocol. Boundary Scan test is
also supported through the same interface.
The embedded tristate bus has internal bus hold and
arbitration features in order to make the function more
“user friendly”. The bus hold feature keeps the internal
bus at the previously driven logic state when the bus is
not driven to eliminate bus float. The bus arbitration is
performed on a “first come, first served” priority. In other
words, once a logic block drives the bus, other logic
blocks cannot drive the bus until the first releases the bus.
This arbitration feature prevents internal bus contention
when there is an overlap between two bus enable signals. Typically, it takes about 3ns to resolve one bus
signal coming off the bus to another bus signal driving the
bus. The arbitration feature combined with the predictability of CPLD, makes the embedded tristate bus the
most practical for the real world bus implementations.
An enhanced, multiple cell security scheme is provided
that prevents reading of the JEDEC programming file
when secured. After the device has been secured using
this mechanism, the only way to clear the security is to
execute a bulk-erase instruction.
ispLSI 8840 Description
The ispLSI 8840 device has seven Big Fast Megablocks
for a total of 7 x 120 = 840 macrocells.
Each Big Fast Megablock has a total of 24 I/O cells and
the Global Routing Plane has a total of 144 I/O cells. This
gives (7 x 24) + 144 = 312 I/Os.
The total registers in the device is the sum of macrocells
plus I/O cells, 840 + 312 = 1152 registers.
Embedded Tristate Bus
There is a 108-line embedded internal tristate bus as part
of the Global Routing Plane (GRP), enabling multiple
GLBs to drive the same tracks. This bus can be partitioned into various bus widths such as twelve 9-line
buses, six 18-line buses or three 36-line buses. The
GLBs can dynamically share a subset of the Global
Routing Plane tracks. This feature eliminates the need to
convert tristate buses to wide multiplexers on the programmable device. Up to 18 macrocells per GLB can
4
Specifications ispLSI 8840
Figure 2. ispLSI 8000 GLB Overview
I/O Big Fast Megablock Input Tracks
AND Array Input
Routing
General Purpose Big Fast Megablock Input Tracks
20
Feedback Inputs
0
43
Product Term
Sharing Array
Macrocell 0
PT 0
PT 1
PT 2
PT 3
From PTSA
PTSA Bypass
Single PT
PT Clock
PT Preset
PT Reset
Shared PT Clock
Bus Input
To Interconnect
0
From Tristate
Bus Track
Macrocell 1
PT 4
PT 5
PT 6
PT 7
From PTSA
PTSA Bypass
Single PT
PT Clock
PT Preset
PT Reset
Shared PT Clock
Bus Input
To Interconnect
1
From Tristate
Bus Track
Macrocell 2
PT 8
PT 9
PT 10
PT 11
From PTSA
PTSA Bypass
Single PT
PT Clock
PT Preset
PT Reset
Shared PT Clock
Bus Input
Fully Populated
AND Array
To Interconnect
2
From Tristate
Bus Track
Macrocell 3
PT 12
PT 13
PT 14
PT 15
From PTSA
PTSA Bypass
Single PT
PT Clock
PT Preset
PT Reset
Shared PT Clock
Bus Input
To interconnect
3
From Tristate
Bus Track
Macrocell 19
PT 76
PT 77
PT 78
PT 79
From PTSA
PTSA Bypass
Single PT
PT Clock
PT Preset
PT Reset
Shared PT Clock
Bus Input
PT 80
To Interconnect
19
From Tristate Bus Track
To Output Control MUX
PT 81
Function Selector (E2 Cell Controlled)
Note: Macrocells 9 and 10 do not support Tristate Bus Feedback.
5
Specifications ispLSI 8840
Figure 3. ispLSI 8000 Macrocell Overview
Bus Input From Tristate
Bus Track*
Single PT
Feedback to AND Array
PTSA
D
Q
To Big Fast Megablock
or Global Interconnect
PTSA Bypass
PT Clock
Clk En
Global Clock Enable
To Specific
Global Tristate Bus*
Global Clock 0
Global Clock 1
Global Clock 2
R/L
R P
PT Reset
From Macrocell
9 or 10
Macrocells 0-8
and 11-19
GRST
PT Preset
Reset pin
GRST
To All Macrocells and I/O Cells
Preset/Reset Input has Global Polarity Control
From PT80
: Function Selector (E2 Cell Controlled)
*Not available for Macrocells 9 and 10.
6
Specifications ispLSI 8840
Figure 4. ispLSI 8000 I/O Cell
TOE
VCCIO VCCIO
VCCIO
GLOBAL OE0
GLOBAL OE1
GLOBAL OE2
GLOBAL OE3
From Output
Control Bus
Multiplexed Output From
Big Fast Megablock or
Global Track
D
Q
GLOBAL I/O CLOCK ENABLE
From Output
Control Bus
GLOBAL I/O CLOCK0
GLOBAL I/O CLOCK1
QUADRANT I/O CLOCK
Big Fast Megablock I/O Pad
or Global I/O Pad
Slew Open
Rate Drain
CLKEN
To Specific
Big Fast Megablock
or Global Tracks
R/L
To Specific
Global Tristate Bus
From Output
Control Bus
P
R
From Output
Control Bus
Global I/O Cell
Only
GRST
From Output
Control Bus
: Function Selector (E2 Cell Controlled)
7
Specifications ispLSI 8840
The Global OE signals and Test OE signal are driven
from the dedicated external control input pins.
Output Control Organization
In addition to the data input and output to the I/O cells,
each I/O cell can have up to six different I/O cell control
signals. In addition to the internal OE control, the five
control signals for each I/O cell consist of pin OE control,
clock enable, clock input, asynchronous preset and asynchronous reset. All of the I/O control signals can be driven
either from the dedicated external input pins or from the
internal control bus.
The 16-bit wide output control buses are organized in four
different quadrants as shown in Figure 5. Since each
GLB is capable of generating the output control signals,
each of the output control bus signals can be driven from
a unique GLB. The 42 GLBs can generate a total of 42
unique I/O control signals. Referring to Figure 2, the GLB
generates its output control signal from control product
term (PT81).
The output enable of each I/O cell can be driven by 21
different sources – 16 from the output control bus, four
from the Global OE pins and one from the Test OE pin.
Figure 5 also illustrates how the quadrant clocks are
routed to the appropriate quadrant I/O cells.
Figure 5. Output Control Bus and Quadrant Organization
GLB
Generated
Output
Control
(see Figure 2)
From PT81
Quadrant 3, 16-Bit Wide Output Control Bus
(I/O G0-G5 <0-11>, QIOCLK3)
Quadrant 1, 16-Bit Wide Output Control Bus
(I/O G0-G5 <12-23>, QIOCLK1)
Quadrant 0, 16-Bit Wide Output Control Bus
(I/O B0-B6 <0-11>, QIOCLK0)
Quadrant 2, 16-Bit Wide Output Control Bus
(I/O B0-B6 <12-23>, QIOCLK2)
OE Bus.eps
8
Specifications ispLSI 8840
Figure 6. Boundary Scan Register Circuit for I/O Pins
HIGHZ
EXTEST
PROG_MODE
SCANIN
(from previous
cell)
BSCAN
Registers
D
TOE
BSCAN
Latches
Q
D
Normal
Function
OE
Q
0
1
EXTEST
PROG_MODE
Normal
Function
Shift DR
D
Q
D
Q
Clock DR
D
Q
0
1
SCANOUT
(to next cell)
Update DR
Reset*
*Internal power-up reset signal. Not connected to external reset pin.
Figure 7. Boundary Scan Register Circuit for Input-Only Pins
Input Pin
SCANIN
(from previous
cell
D
Shift DR
Clock DR
9
Q
SCANOUT
(to next cell)
I/O Pin
Specifications ispLSI 8840
Figure 8. Boundary Scan Waveforms and Timing Specifications
TMS
TDI
Tbtsu
Tbtch
Tbth
Tbtcl
Tbtcp
TCK
Tbtvo
Tbtco
TDO
Valid Data
Tbtcsu
Data to be
captured
Valid Data
Tbtch
Data Captured
Tbtuov
Tbtuco
Data to be
driven out
Valid Data
Tbtuoz
Valid Data
MIN
MAX
UNITS
TCK Clock Pulse Width
0.1
400
µs
TCK Pulse Width High
0.05
200
µs
TCK Pulse Width Low
0.05
200
µs
TDI, TMS Setup Time to TCK
25
—
ns
TDI, TMS Hold Time from TCK
25
—
ns
TCK, TDI, TMS Rise and Fall Time
50
—
mV/ns
TAP Controller, TCK to TDO Valid
—
25
ns
TAP Controller, TCK to TDO High-Impedance
—
25
ns
TAP Controller, TCK to TDO High-Impedance to Valid Output
—
25
ns
BSCAN Test Capture Register Setup Time
20
—
ns
BSCAN Test Capture Register Hold Time
25
—
ns
BSCAN Test Update Register Clock to Valid Output
—
25
ns
BSCAN Test Update Register Clock to High-Impedance
—
25
ns
BSCAN Test Update Register High-Impedance to Valid Output
—
25
SYMBOL
tbtcp
tbtch
tbtcl
tbtsu
tbth
trf
tbtco
tbtoz
tbtvo
tbtcsu
tbtch
tbtuco
tbtuoz
tbtuov
Tbtoz
PARAMETER
ns
Table 2-0010/8840
10
Specifications ispLSI 8840
Absolute Maximum Ratings 1,2
Supply Voltage Vcc .................................. -0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to VCC +1.0V
Tri-Stated Output Voltage Applied .... -2.5 to VCC +1.0V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 140°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
2. Compliance with the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM is a requirement.
DC Recommended Operating Condition
PARAMETER
SYMBOL
VCC
VCCIO
VIH
VIL
VOH
VOL
Supply Voltage
Commercial
TA = 0°C to 70°C
MIN.
MAX.
UNITS
4.75
5.25
V
Output Supply Voltage
3.0
5.25
V
Input High Voltage
2.0
VCC +1
V
Input Low Voltage
0.0
0.8
V
Output High Voltage
2.4
—
V
Output Low Voltage
—
0.4
V
Table 2-0005/8840
Capacitance (TA=25°C,f=1.0 MHz)
TYPICAL
UNITS
I/O Capacitance
10
pf
VCC = 5.0V, VI/O = 2.0V
Clock Capacitance
10
pf
VCC = 5.0V, VCK = 2.0V
Global Input Capacitance
10
pf
VCC = 5.0V, VG = 2.0V
SYMBOL
C1
C2
C3
PARAMETER
TEST CONDITIONS
Table 2-0006/8840
Erase/Reprogram Specification
PARAMETER
ispLSI Erase/Reprogram Cycles
MINIMUM
MAXIMUM
UNITS
10000
–
Cycles
Table 2-0008/3320
11
Specifications ispLSI 8840
Switching Test Conditions
Input Pulse Levels
Figure 9. Test Load
GND to 3.0V
≤ 1.5 ns 10% to 90%
Input Rise and Fall Time
Input Timing Reference Levels
1.5V
Ouput Timing Reference Levels
1.5V
Output Load
+ 5V (VCC and VCCIO)
R1
See Figure 2
Device
Output
Table 2-0003/8840
3-state levels are measured 0.5V from
steady-state active level.
Test
Point
R2
Output Load Conditions (See Figure 9)
TEST CONDITION
R1
R2
CL
470Ω
390Ω
35pF
Active High
∞
390Ω
35pF
Active Low
470Ω
390Ω
35pF
Active High to Z
at VOH -0.5V
∞
390Ω
5pF
Active Low to Z
at VOL +0.5V
470Ω
390Ω
5pF
A
B
C
CL*
*CL includes Test Fixture and Probe Capacitance.
0213A/8840
Table 2-0004A/8840
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
VOL
VOH
IIL
IIH
CONDITION
PARAMETER
3
MIN.
TYP.
MAX. UNITS
–
–
0.4
V
2.4
–
–
V
Output Low Voltage
IOL = 8 mA
Output High Voltage
IOH = -4 mA
Input or I/O Low Leakage Current
0.0V ≤ VIN ≤ 0.8V
–
–
-10
µA
3.5V ≤ VIN ≤ VCC
VCCIO = 5V
–
–
10
µA
(VCCIO - 0.2) ≤ VIN ≤ VCCIO
VCCIO = 3.3V
–
–
10
µA
VCCIO < VIN ≤ 5.25V
VIN >VCCIO
–
–
10
µA
Input or I/O High Leakage Current
IPU
IBHL
IBHH
IBHLO
IBHHO
VBHT
IOS 1
Active Pullup Current, Input or I/O
0V ≤ VIN ≤ 2.0V
-10
–
-250
µA
Bus-Hold Low Sustaining Current
VIN = 0.8V
50
–
–
µA
Bus-Hold High Sustaining Current
VIN = 2.0V
-50
–
–
µA
Bus-Hold Low, Overdrive Current
0V ≤ VIN ≤ VCCIO
–
–
550
µA
Bus-Hold High, Overdrive Current
0V ≤ VIN ≤ VCCIO
–
–
-550
µA
0.8
–
2.0
V
VCC = 5V, VOUT = 0.5V
–
–
-200
mA
ICC 2,4
Operating Power Supply Current
VIL = 0.0V, VIH = 3.0V High Speed Mode
–
630
–
mA
fCLOCK = 1MHz
–
340
–
mA
Bus-Hold Trip Point (1.4V Nominal)
Output Short Circuit Current
Low Power Mode
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems
by tester ground degradation. Characterized but not 100% tested.
2. Measured using 42 20-bit counters.
3. Typical values are at VCC = 5V and TA = 25°C.
4. Maximum I CC varies widely with specific device configuration and operating frequency.
12
Table 2-0007/8840
Specifications ispLSI 8840
External Switching Characteristics1
Over Recommended Operating Conditions
PARA- TEST
2
4 #
METER COND.
tpd1
tpd2
fmax
tsuq
thq
tcoq
tsug
thg
tcog
tsu1
th1
tco1
tsuceq
thceq
tsuceg
thceg
tgoe
trglb
trio
trw
twh
twl
1.
2.
3.
4.
-110
DESCRIPTION
-90
-60
MIN. MAX. MIN. MAX. MIN. MAX.
UNITS
A
1 Prop Delay, BFM Input to Same BFM Output, 4 PT Bypass
–
8.5
–
10.0
–
15.0
ns
A
2 Prop Delay, Global Input to Global Output
–
13.5
–
16.0
–
24.0
ns
110
–
90.0
–
60.0
–
MHz
8.0
–
12.0
–
ns
0.0
–
0.0
–
ns
3
–
3 Clk Frequency, Local Feedback, Same GLB
–
4 I/O Cell Reg, Data Setup Time, Quadrant I/O Clock
6.0
–
5 I/O Cell Reg, Data Hold Time, Quadrant I/O Clock
0.0
–
A
6 I/O Cell Reg, Quadrant Clock to Output Delay
–
4.5
–
6.0
–
9.0
ns
–
7 I/O Cell Reg, Data Setup Time, Global I/O Clock
4.5
–
6.0
–
9.0
–
ns
–
0.0
–
0.0
–
0.0
–
ns
A
8 I/O Cell Reg, Data Hold Time, Global I/O Clock
9 I/O Cell Reg, Global Clock to Output Delay
–
6.0
–
7.5
–
11.0
ns
–
10 GLB Reg Setup, BFM Input to Same BFM GLB, 4 PT Bypass
5.0
–
7.0
–
10.0
–
ns
–
11 GLB Reg Hold Time, BFM Input to Same BFM GLB
0.0
–
0.0
–
0.0
–
ns
A
12 GLB Reg, Global Clock to Same BFM Output Delay
–
8.0
–
10.0
–
15.0
ns
–
13 I/O Cell Reg, CLKEN Setup Time, Quadrant I/O Clock
5.0
–
6.5
–
9.5
–
ns
–
14 I/O Cell Reg, CLKEN Hold Time, Quadrant I/O Clock
0.0
–
0.0
–
0.0
–
ns
–
15 GLB Reg, CLKEN Setup Time, Global Clock
3.5
–
4.5
–
6.5
–
ns
–
16 GLB Reg, CLKEN Hold Time, Global Clock
0.0
–
0.0
–
0.0
–
ns
B/C
17 Global Output Enable/Disable Delay
–
8.0
–
10.0
–
15.0
ns
–
18 Global Reset/Preset Time, GLB Reg
–
12.0
–
15.0
–
22.0
ns
–
19 Global Reset/Preset Time, I/O Cell Reg
–
8.0
–
10.0
–
15.0
ns
–
20 Global Reset/Preset Pulse Duration
5.0
–
6.5
–
9.5
–
ns
–
21 Global or Quadrant Clock Pulse, High Duration
4.0
–
6.0
–
9.0
–
ns
–
22 Global or Quadrant Clock Pulse, Low Duration
4.0
–
6.0
–
9.0
–
ns
Unless noted otherwise, all parameters use PTSA and CLK0.
Refer to Timing Model in this data sheet for further details.
Standard 20-bit counter with local feedback.
Refer to Switching Test Conditions section.
13
Table 2-0030/8840
Specifications ispLSI 8840
Internal Timing Parameters
Over Recommended Operating Conditions
PARAMETER
-110
#2
DESCRIPTION
-90
-60
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
23 Input Pad and Input Buffer, Combinatorial Input
–
0.1
–
0.1
–
0.2
ns
24 Input Pad and Input Buffer, Registered Input
–
8.0
–
9.4
–
13.9
ns
25 Output Register/Latch Bypass to Output Buffer
–
0.0
–
0.0
–
0.0
ns
26 Input Register/Latch Bypass to BFM Routing or GRP
–
0.2
–
0.2
–
0.4
ns
27 I/O Cell Latch, Transparent Mode
–
2.0
–
2.4
–
3.6
ns
28 I/O Cell Register/Latch, Clk/Gate to Output
–
1.0
–
1.2
–
2.0
ns
29 I/O Cell Register/Latch, Setup Time
0.4
–
0.7
–
1.4
–
ns
30 I/O Cell Register/Latch, Hold Time
4.1
–
4.4
–
6.9
–
ns
I/O Cell Delay
tidcom
tidreg
tobp
tibp
tiolat
tioco
tiosu
tioh
tiorst
tiosuce
tiohce
todreg
todcom
todz
tslf
tsls
–
2.3
–
2.9
–
4.4
ns
32 I/O Cell Register/Latch, Setup Time for Clk Enable
31 I/O Cell Register/Latch, Reset or Set Time
2.6
–
2.7
–
3.8
–
ns
33 I/O cell Register/Latch, Hold Time for Clk Enable
1.9
–
1.9
–
2.9
–
ns
34 I/O Cell Output Buffer Delay, Registered Output
–
1.1
–
1.3
–
1.9
ns
35 I/O Cell Output Buffer Delay, Combinatorial Output
–
1.7
–
2.0
–
3.0
ns
36 Output Driver Disable Time
–
2.0
–
2.3
–
3.5
ns
37 Slew Rate Adder, Fast Slew Rate
–
0.0
–
0.0
–
0.0
ns
38 Slew Rate Adder, Slow Slew Rate
–
5.0
–
5.0
–
7.5
ns
39 AND Array, High Speed Mode
–
3.6
–
4.2
–
6.4
ns
GLB / Macrocell Delay
tandhs
tandlp
t1pt
t4ptcom
t4ptreg
tptsa
tmbp
tmlat
tmco
tmsu
tmh
tmrst
tmsuce
tmhce
tftog
tfloc
tpck
tpcken
tsck
tscken
tprst
trdir
40 AND Array, Low Power Mode
–
7.1
–
8.4
–
12.6
ns
41 Single Product Term Bypass
–
3.6
–
4.3
–
6.2
ns
42 Four Product Term Bypass, Combinatorial Macrocell
–
0.2
–
0.3
–
0.4
ns
43 Four Product Term Bypass, Registered Macrocell
–
3.4
–
4.4
–
6.1
ns
44 Product Term Sharing Array
–
3.7
–
4.5
–
6.8
ns
45 Macrocell Register/Latch Bypass
–
0.0
–
0.0
–
0.0
ns
46 Macrocell Latch, Transparent Mode
–
0.2
–
0.3
–
0.9
ns
47 Macrocell Register/Latch, Clk/Gate to Output
–
0.2
–
0.3
–
0.5
ns
48 Macrocell Register/Latch, Setup Time
0.4
–
0.8
–
1.2
–
ns
49 Macrocell Register/Latch, Hold Time
3.8
–
4.5
–
6.1
–
ns
–
4.0
–
5.2
–
7.3
ns
51 Macrocell Register/Latch, Setup Time for Clk Enable
50 Macrocell Register/Latch, Reset or Set Time
1.7
–
1.8
–
2.4
–
ns
52 Macrocell Register/Latch, Hold Time for Clk Enable
1.0
–
0.9
–
1.3
–
ns
–
3.9
–
4.7
–
6.8
ns
53 Toggle Flip-Flop Feedback
54 Local Feedback to AND Array
55 Single Product Term, Clk
56 Single Product Term, Clk Enable
57 Shared Product Term, Clk
–
1.1
–
1.3
–
1.9
ns
1.0
2.5
1.5
3.5
2.3
5.3
ns
–
2.6
–
3.1
–
4.6
ns
1.6
2.4
1.8
2.5
2.7
3.8
ns
58 Shared Product Term, Clk Enable
–
2.4
–
2.5
–
3.8
ns
59 Single Product Term, Reset or Set Delay
–
1.7
–
2.0
–
3.0
ns
60 Macrocell Register, Direct Input from GRP
–
1.8
–
2.1
–
2.7
ns
14
Specifications ispLSI 8840
Internal Timing Parameters
Over Recommended Operating Conditions
PARAMETER
-110
#2
DESCRIPTION
-90
-60
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
61 BFM Routing Delay, Signal from I/O Cell
–
0.2
–
0.3
–
0.4
ns
62 GRP Delay, Signal from I/O Cell
–
0.2
–
0.2
–
0.4
ns
63 Internal Tristate Bus Enable/Disable, I/O Cell Buffer
–
2.2
–
2.5
–
3.8
ns
64 BFM Routing Delay, Signal from Macrocell
–
1.9
–
2.3
–
3.4
ns
65 GRP Delay, Signal from Macrocell
–
2
–
2.4
–
3.5
ns
BFM / Global Routing Pool Delay
tbfmi
tgrpi
tgrpiz
tbfmm
tgrpm
tgrpmz
tbfmg
tgrpb
tbcom
tbreg
tgcom
tgreg
66 Internal Tristate Bus Enable/Disable, Macrocell Buffer
–
4
–
4.7
–
7.1
ns
67 BFM Routing Delay, Signal from GRP
–
1.6
–
1.8
–
2.8
ns
68 GRP Delay, Signal from BFM Routing
–
2.5
–
3.0
–
4.4
ns
69 BFM Routing to I/O Cell, Combinatorial Path
–
0.5
–
0.6
–
0.8
ns
70 BFM Routing to I/O Cell, Registered Path
–
3.5
–
4.1
–
6.1
ns
71 GRP to I/O Cell, Combinatorial Path
–
0.4
–
0.4
–
0.6
ns
72 GRP to I/O Cell, Registered Path
–
3.4
–
3.9
–
5.9
ns
73 Product Term as I/O Cell Register Clock
–
6.5
–
7.7
–
11.6
ns
74 Product Term as I/O Cell Register Clock Enable
–
6.5
–
7.7
–
11.6
ns
I/O Control Bus Delay
tpiock
tpiocken
tpoe
tpiorst
tpioz
75 Product Term as Output Buffer Enable/Disable
–
6.7
–
7.9
–
11.9
ns
76 Product Term as I/O Cell Register Reset or Set Delay
–
7.3
–
8.8
–
13.2
ns
77 Internal Tristate Bus Control Signal for I/O Cell Buffer
–
6.0
–
7.1
–
10.7
ns
Global Control Delay
tgck
tgcken
tgiock
tgiocken
tqck
tgoe
ttoe
tgmrst
tgiorst
78 Global Macrocell Register Clk
2.9
3.7
3.1
4.9
4.6
7.3
ns
79 Global Macrocell Register Clk Enable
4.7
4.7
5.8
5.8
8.7
8.7
ns
80 Global I/O Register Clk
3.9
3.9
4.1
5.0
6.2
7.0
ns
81 Global I/O Register Clk Enable
4.8
4.8
5.9
5.9
8.9
8.9
ns
82 Quadrant I/O Register Clk
2.4
2.4
2.1
3.5
3.2
5.1
ns
83 Global Output Enable
–
6
–
7.7
–
11.5
ns
84 Test Output Enable
–
7.3
–
8.6
–
12.9
ns
85 Global GLB Register Reset
–
4
–
5.1
–
7.6
ns
86 Global I/O Cell Register Reset
–
4.6
–
5.9
–
8.8
ns
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
15
Specifications ispLSI 8840
ispLSI 8840 Timing Model
#69, tbcom
#70, tbreg
#71, tgcom
#72, tgreg
Input Buffer and I/O Cell Register
I/O register delays
I/O
pad
Input buffer
delays
#23, tidcom
#24, tidreg
#25, tobp
#26, tibp
#27, tiolat
#28, tioco
#29, tiosu
#30, tioh
#31, tiorst
#32, tiosuce
#33, tiohce
Output path
Output
buffer
delays
Output routing
#34, todreg
#35, todcom
#36, todz
Input path
BFM Routing Pool
#61, tbfmi #67, tbfmg
#64, tbfmm
z
GLB/
Macrocell
AND array
#39,
tandhs
#40,
tandlp
Local feedback
#54, tfloc
Toggle feedback
Global
Routing
Plane
#53, Mcell register
PTSA
tftog
#41, t1pt
#45, tmbp
#42, t4ptcom
#46, tmlat
#43, t4ptreg
#47, tmco
#44, tptsa
#48, tmsu
#49, tmh
PT Mcell controls
#50, tmrst
#55, tpck
#51, tmsuce
#56, tpcken
#52, tmbce
#57, t
#62, tgrpi
#63, tgrpiz
#65, tgrpm
#66, tgrpmz
#68, tgrpb
sck
#58, tscken
#59, tprst
Bus direct
#60, trdir
PT I/O control bus
Global control
delay
Input
pad
#78, tgck
#79, tgcken
#80, tgiock
#81, tgiocken
#82, tqck
#83, tgoe
#84, ttoe
#85, tgmrst
#86, tgiorst
#73, tpiock
#74, tpiocken
#75, tpoe
#76, tpiorst
#77, tpioz
8K_Model.eps
16
Output
slew rate
adders
#37, tslf
#38, tsls
I/O
pad
Specifications ispLSI 8840
Example Timing Calculations
tpd1
= (BFM Input Path Delay) + (GLB Delay) + (Output Path Delay)
= (tidcom + tibp + tbfmi) + (tandhs + t4ptcom + tmbp) + (tbfmm + tbcom + tobp + todcom + tslf)
= (#23 + #26 + #61) + (#39 + #42 + #45) + (#64 + #69 + #25 + #35 + #37)
= (0.1 + 0.2 + 0.2) + (3.6 + 0.2 + 0.0) + (1.9 + 0.5 + 0.0 + 1.7 + 0.0)
= 8.4 ns
tpd (within BFM)
= (BFM Delay) + (GLB Delay)
= (tbfmm) + (tandhs + t4ptcom + tmbp)
= (#64) + (#39 + #42 + #45)
= (1.9) + (3.6 + 0.2 + 0.0)
= 5.7 ns
tpd (between BFMs)
= (GRP Delay) + (BFM Delay) + (GLB Delay)
= (tgrpm) + (tbfmg) + (tandhs + t4ptcom + tmbp)
= (#65) + (#67) + (#39 + #42 + #45)
= (2.0) + (1.6) + (3.6 + 0.2 + 0.0)
= 7.4 ns
BFM I/O to internal tri-state Enable/Disable
= (BFM Input Path Delay) + (GLB Delay, 1PT) + (Tri-state Control Delay)
= (tidcom + tibp + tbfmi) + (tandhs + t1pt + tmbp) + (tgrpmz)
= (#23 + #26 + #61) + (#39 + #41 + #45) + (#66)
= (0.1 + 0.2 + 0.2) + (3.6 + 3.6 + 0.0) + (4.0)
= 11.7 ns
tsu1
= (BFM Input Path Delay) + (GLB Setup Time) - (Min. Global Clock Delay)
= (tidcom + tibp + tbfmi) + (tandhs + t4ptreg + tmsu) – (tgck min)
= (#23 + #26 + #61) + (#39 + #43 + #48) – (#78)
= (0.1 + 0.2 + 0.2) + (3.6 + 3.4 + 0.4) – (2.9)
= 5 ns
1/Fmax = (Global Clk to MC Output) + (Local Feedback) + (GLB Setup Time)
= (tmco) + (tfloc) + (tandhs + tptsa + tmsu)
= (#47) + (#54) + (#39 + #44 + #48)
= (0.2) + (1.1) + (3.6 + 3.7 + 0.4)
= 9 ns
Fmax
= 111 MHz
Note: Calculations are based upon timing specifications for the ispLSI 8840-110L
17
Specifications ispLSI 8840
Power Consumption
Power consumption in the ispLSI 8840 device depends
on two primary factors: the speed at which the device is
operating and the number of product terms used. The
product terms have a fuse-selectable speed/power
tradeoff setting. Each group of four product terms has a
single speed/power tradeoff control fuse that acts on the
complete group of four. The fast “high-speed” setting
operates product terms at their normal full power consumption. For portions of the logic that can tolerate
longer propagation delays, selecting the slower “lowpower” setting will significantly reduce the power
dissipation for these product terms. Figure 10 shows the
relationship between power and operating speed.
Figure 10. Typical Device Power Consumption vs fmax
1200
1100
1000
ispLSI 8840
ICC (mA)
900
800
700
600
Turbo
Non-Turbo
500
400
300
200
0
10
20
30
40
50
60
70
80
90 100 110 120
fmax (MHz)
Notes: Configuration of 42 20-bit counters
Typical current at 5V, 25° C
ICC can be estimated for the ispLSI 8840 using the following equation:
ICC = 48.0 + (# of Turbo PTs * 0.346) + (# of Non-Turbo PTs * 0.165) + (# of Macrocells Used * fmax * AF * 0.049)
# of Turbo PTs = Number of Turbo Product Terms Used in Design
# of Non-Turbo PTs = Number of Non-Turbo Product Terms Used in Design
fmax = Maximum Operating Frequency
AF (Activity Factor) =
Average Macrocell Toggle Frequency
Fmax
Note: An Activity Factor of 1.0 means all macrocell registers toggle at Fmax. An Activity Factor of 0.5 means the
average macrocell registers toggle at half of fmax.
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of two GLB loads
on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions
and the program in the device, the actual ICC should be verified.
0127/8840
18
Specifications ispLSI 8840
Signal Descriptions
Signal Name
CLK0, CLK1,
CLK2
Description
Dedicated clock input for the GLB registers only. These clock inputs are connected to one of the clock
inputs of all GLB registers in the device.
CLKEN
Dedicated clock enable input for the GLB registers only. This input is available as a clock enable for
each GLB register in the device. Use of the clock enable input eliminates the need for the user to gate
the clock to the register.
GIOCLK0,
GIOCLK1
Dedicated clock inputs for the I/O registers only. These clock inputs are connected to one of the clock
inputs of all I/O registers in the device.
GND
Ground (GND)
GOE
Global Output Enable inputs.
SET/RESET
Dedicated reset/preset pin connected to ALL registers in the device, GLB registers and
I/O registers. Each register can independently choose to be reset or preset when this signal goes
active. The active polarity is user-selectable.
IOCLKEN
Dedicated clock enable input for the I/O registers only. This input is available as a clock enable input for
all I/O registers in the device. Use of the clock enable input eliminates the need for the user to tie the
clock to the I/O register.
I/O
Input/Output – These are the general purpose I/O used by the logic array.
BSCAN/ispEN
Input – Dedicated in-system programming enable input. When this is high, the BSCAN TAP
controller signals TMS, TDI, TDO and TCK are enabled. When this is brought low, the ISP State
Machine control signals MODE, SDI, SDO and SLCK are enabled. High-to-low transition will put the
device in the Lattice ISP programming mode and put all I/O in the high-Z state.
TMS/MODE
Input – This signal performs two functions. It is the Test Mode Select input signal when ispEN is logic
high. When ispEN is logic low, it controls the operation of the ISP State Machine.
NC1
No connect.
QIOCLK0
QIOCLK1
QIOCLK2
QIOCLK3
Dedicated clock inputs for the I/O registers only. These clock inputs are connected to the I/O registers
on the same side of the device only, they are not connected to all of the I/O registers. Use of these
quadrant I/O clocks gives the fastest tco from the device.
TCK/SCLK
Input – This signal performs two functions. It is the Test Clock input signal when ispEN is logic high.
When ispEN is logic low, it functions as a clock signal for the Serial Shift Register.
TDI/SDI
Input – This signal performs two functions. It is the Test Data input signal when ispEN is logic high.
When ispEN is logic low, it functions as an input to load programming data into the device. SDI is also
used as one of the two control signals for the ISP State Machine.
TDO/SDO
Output – This signal performs two functions. When ispEN is logic low, it reads the ISP data. When
ispEN is high, it functions as Test Data Out.
TOE
Test Output Enable pin – This pin tristates all I/O pins when a logic low is driven.
VCC
Vcc
VCCIO
Power supply for the output drivers. The internal logic of the device is connected to VCC which is
always 5V. The output drivers are connected to VCCIO which can be equal to VCC or 3.3V. This allows
the output drivers to be powered from 3.3V, for example, to interface directly with another 3.3V device.
1. NC pins are not to be connected to any active signals, VCC or GND.
19
Specifications ispLSI 8840
Signal Locations (432-Ball BGA Package)
Signal
432-Ball BGA
CLK0, CLK1, CLK2 A18, P29, AL19
CLKEN
C18
GIOCLK0,
GIOCLK1
A19, AJ18
GND
A1, A2, A16, A30, A31, B1, B5, B9, B13, B19, B23, B27, B31, E2, E30, J2, J30, N2, N30, T1, T31, W2,
W30, AC2, AC30, AG2, AG30, AK1, AK5, AK9, AK13, AK19, AK23, AK27, AK31, AL1, AL2, AL16,
AL30, AL31
GOE0, GOE1
GOE2, GOE3
D18, T29, AH18, T2
SET/RESET
P1
IOCLKEN
AL20
BSCAN/ispEN
AG28
TMS/MODE
E4
NC1
A4, B30, D1, D31, AH1, AH31, AK2, AK30, AL4, AL28
QIOCLK0,
QIOCLK1,
QIOCLK2,
QIOCKK3
D17, R31, AL18, T3
TCK/SCLK
AH2
TDI/SDI
E3
TDO/SDO
AH3
TOE
V3
VCC
A3, A10, A22, A29, B14, B18, C1, C31, K1, K31, P2, P30, V2, V30, AB1, AB31, AJ1, AJ31, AK14,
AK18, AL3, AL10, AL22, AL29
VCCIO
D5, D9, D12, D15, D20, D23, D27, H4, H28, M4, M28, T4, T28, Y4, Y28, AE4, AE28, AH5, AH9, AH12,
AH15, AH20, AH23, AH27
1. NC pins are not to be connected to any active signals, VCC or GND.
20
Specifications ispLSI 8840
I/O Pin Locations (432-Ball BGA Package)
Signal
I/O G0 <0>
I/O G0 <1>
I/O G0 <2>
I/O G0 <3>
I/O G0 <4>
I/O G0 <5>
I/O G0 <6>
I/O G0 <7>
I/O G0 <8>
I/O G0 <9>
I/O G0 <10>
I/O G0 <11>
I/O G0 <12>
I/O G0 <13>
I/O G0 <14>
I/O G0 <15>
I/O G0 <16>
I/O G0 <17>
I/O G0 <18>
I/O G0 <19>
I/O G0 <20>
I/O G0 <21>
I/O G0 <22>
I/O G0 <23>
I/O G1 <0>
I/O G1 <1>
I/O G1 <2>
I/O G1 <3>
I/O G1 <4>
I/O G1 <5>
I/O G1 <6>
I/O G1 <7>
I/O G1 <8>
I/O G1 <9>
I/O G1 <10>
I/O G1 <11>
I/O G1 <12>
I/O G1 <13>
I/O G1 <14>
I/O G1 <15>
I/O G1 <16>
I/O G1 <17>
I/O G1 <18>
I/O G1 <19>
I/O G1 <20>
I/O G1 <21>
I/O G1 <22>
I/O G1 <23>
I/O G2 <0>
I/O G2 <1>
I/O G2 <2>
I/O G2 <3>
I/O G2 <4>
I/O G2 <5>
I/O G2 <6>
I/O G2 <7>
I/O G2 <8>
I/O G2 <9>
I/O G2 <10>
I/O G2 <11>
I/O G2 <12>
I/O G2 <13>
I/O G2 <14>
BGA
C2
F4
F3
D2
G4
F2
G3
E1
G2
H3
F1
J4
F31
G30
H29
F30
E31
G29
G28
F29
E29
F28
D30
E28
L1
L2
L3
L4
K2
J1
K3
K4
H1
G1
J3
H2
J28
J29
H30
G31
H31
K28
K29
K30
J31
L28
L29
L30
M3
M2
M1
N4
N3
N1
P3
P4
R2
R3
R4
R1
R30
R29
R28
Signal
I/O G2 <15>
I/O G2 <16>
I/O G2 <17>
I/O G2 <18>
I/O G2 <19>
I/O G2 <20>
I/O G2 <21>
I/O G2 <22>
I/O G2 <23>
I/O G3 <0>
I/O G3 <1>
I/O G3 <2>
I/O G3 <3>
I/O G3 <4>
I/O G3 <5>
I/O G3 <6>
I/O G3 <7>
I/O G3 <8>
I/O G3 <9>
I/O G3 <10>
I/O G3 <11>
I/O G3 <12>
I/O G3 <13>
I/O G3 <14>
I/O G3 <15>
I/O G3 <16>
I/O G3 <17>
I/O G3 <18>
I/O G3 <19>
I/O G3 <20>
I/O G3 <21>
I/O G3 <22>
I/O G3 <23>
I/O G4 <0>
I/O G4 <1>
I/O G4 <2>
I/O G4 <3>
I/O G4 <4>
I/O G4 <5>
I/O G4 <6>
I/O G4 <7>
I/O G4 <8>
I/O G4 <9>
I/O G4 <10>
I/O G4 <11>
I/O G4 <12>
I/O G4 <13>
I/O G4 <14>
I/O G4 <15>
I/O G4 <16>
I/O G4 <17>
I/O G4 <18>
I/O G4 <19>
I/O G4 <20>
I/O G4 <21>
I/O G4 <22>
I/O G4 <23>
I/O G5 <0>
I/O G5 <1>
I/O G5 <2>
I/O G5 <3>
I/O G5 <4>
I/O G5 <5>
BGA
P31
P28
N31
N29
N28
M31
M30
L31
M29
Y3
Y1
Y2
W4
W3
W1
V1
V4
U1
U4
U3
U2
T30
U28
U29
U30
U31
V28
V29
V31
W29
W28
W31
Y31
AA2
AA3
AA4
AA1
AB3
AB4
AB2
AC3
AC4
AC1
AD2
AD3
AC28
AC29
AC31
AB28
AB29
AB30
AA29
AA28
AA30
AA31
Y30
Y29
AG4
AG3
AG1
AF1
AF4
AF3
Signal
BGA
I/O G5 <6>
I/O G5 <7>
I/O G5 <8>
I/O G5 <9>
I/O G5 <10>
I/O G5 <11>
I/O G5 <12>
I/O G5 <13>
I/O G5 <14>
I/O G5 <15>
I/O G5 <16>
I/O G5 <17>
I/O G5 <18>
I/O G5 <19>
I/O G5 <20>
I/O G5 <21>
I/O G5 <22>
I/O G5 <23>
I/O B0 <0>
I/O B0 <1>
I/O B0 <2>
I/O B0 <3>
I/O B0 <4>
I/O B0 <5>
I/O B0 <6>
I/O B0 <7>
I/O B0 <8>
I/O B0 <9>
I/O B0 <10>
I/O B0 <11>
I/O B0 <12>
I/O B0 <13>
I/O B0 <14>
I/O B0 <15>
I/O B0 <16>
I/O B0 <17>
I/O B0 <18>
I/O B0 <19>
I/O B0 <20>
I/O B0 <21>
I/O B0 <22>
I/O B0 <23>
I/O B1 <0>
I/O B1 <1>
I/O B1 <2>
I/O B1 <3>
I/O B1 <4>
I/O B1 <5>
I/O B1 <6>
I/O B1 <7>
I/O B1 <8>
I/O B1 <9>
I/O B1 <10>
I/O B1 <11>
I/O B1 <12>
I/O B1 <13>
I/O B1 <14>
I/O B1 <15>
I/O B1 <16>
I/O B1 <17>
I/O B1 <18>
I/O B1 <19>
I/O B1 <20>
21
AF2
AE1
AE3
AE2
AD1
AD4
AD31
AD29
AD28
AD30
AE29
AE30
AE31
AF31
AF28
AF29
AF30
AG31
D3
D4
B2
C3
C4
C5
D6
C6
B3
D7
B4
B6
AJ7
AK6
AH7
AJ6
AK4
AH6
AJ5
AK3
AJ4
AJ3
AH4
AJ2
D8
C7
A5
C8
B7
A6
C9
A7
D10
B8
C10
A8
AH11
AL8
AJ10
AK8
AH10
AL7
AJ9
AK7
AJ8
Signal
I/O B1 <21>
I/O B1 <22>
I/O B1 <23>
I/O B2 <0>
I/O B2 <1>
I/O B2 <2>
I/O B2 <3>
I/O B2 <4>
I/O B2 <5>
I/O B2 <6>
I/O B2 <7>
I/O B2 <8>
I/O B2 <9>
I/O B2 <10>
I/O B2 <11>
I/O B2 <12>
I/O B2 <13>
I/O B2 <14>
I/O B2 <15>
I/O B2 <16>
I/O B2 <17>
I/O B2 <18>
I/O B2 <19>
I/O B2 <20>
I/O B2 <21>
I/O B2 <22>
I/O B2 <23>
I/O B3 <0>
I/O B3 <1>
I/O B3 <2>
I/O B3 <3>
I/O B3 <4>
I/O B3 <5>
I/O B3 <6>
I/O B3 <7>
I/O B3 <8>
I/O B3 <9>
I/O B3 <10>
I/O B3 <11>
I/O B3 <12>
I/O B3 <13>
I/O B3 <14>
I/O B3 <15>
I/O B3 <16>
I/O B3 <17>
I/O B3 <18>
I/O B3 <19>
I/O B3 <20>
I/O B3 <21>
I/O B3 <22>
I/O B3 <23>
I/O B4 <0>
I/O B4 <1>
I/O B4 <2>
I/O B4 <3>
I/O B4 <4>
I/O B4 <5>
I/O B4 <6>
I/O B4 <7>
I/O B4 <8>
I/O B4 <9>
I/O B4 <10>
I/O B4 <11>
BGA
AL6
AH8
AL5
D11
A9
C11
B10
C12
B11
A11
B12
D13
C13
A12
A13
AJ14
AL13
AJ13
AH13
AL12
AL11
AK12
AJ12
AK11
AK10
AJ11
AL9
D14
C14
A14
C15
B15
A15
B16
C16
D16
A17
B17
C17
AH17
AJ17
AK17
AL17
AH16
AJ16
AK16
AL15
AJ15
AK15
AL14
AH14
A20
B20
C19
A21
D19
C20
B21
A23
C21
B22
A24
D21
Signal
BGA
I/O B4 <12>
I/O B4 <13>
I/O B4 <14>
I/O B4 <15>
I/O B4 <16>
I/O B4 <17>
I/O B4 <18>
I/O B4 <19>
I/O B4 <20>
I/O B4 <21>
I/O B4 <22>
I/O B4 <23>
I/O B5 <0>
I/O B5 <1>
I/O B5 <2>
I/O B5 <3>
I/O B5 <4>
I/O B5 <5>
I/O B5 <6>
I/O B5 <7>
I/O B5 <8>
I/O B5 <9>
I/O B5 <10>
I/O B5 <11>
I/O B5 <12>
IO B5 <13>
I/O B5 <14>
I/O B5 <15>
I/O B5 <16>
I/O B5 <17>
I/O B5 <18>
I/O B5 <19>
I/O B5 <20>
I/O B5 <21>
I/O B5 <22>
I/O B5 <23>
I/O B6 <0>
I/O B6 <1>
I/O B6 <2>
I/O B6 <3>
I/O B6 <4>
I/O B6 <5>
I/O B6 <6>
I/O B6 <7>
I/O B6 <8>
I/O B6 <9>
I/O B6 <10>
I/O B6 <11>
I/O B6 <12>
I/O B6 <13>
I/O B6 <14>
I/O B6 <15>
I/O B6 <16>
I/O B6 <17>
I/O B6 <18>
I/O B6 <19>
I/O B6 <20>
I/O B6 <21>
I/O B6 <22>
I/O B6 <23>
AH21
AK24
AL24
AJ21
AK22
AJ20
AL23
AH19
AK21
AJ19
AK20
AL21
A25
C22
B24
D22
B25
C23
A26
C24
B26
D24
C25
A27
AJ26
AJ25
AH24
AL27
AK26
AJ24
AJ23
AL26
AH22
AK25
AL25
AJ22
D25
A28
C26
B28
D26
C27
B29
C28
C29
C30
D28
D29
AG29
AH30
AH29
AH28
AJ30
AJ29
AJ28
AH26
AJ27
AK29
AK28
AH25
Specifications ispLSI 8840
Signal Configuration
ispLSI 8840 432-Ball BGA Signal Diagram
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
7
5
I/O
B1
<5>
I/O
B1
<2>
4
I/O
I/O
I/O
B6
B5
B5
<1> <11> <6>
I/O
I/O
I/O
B5
B4
B4 VCC
<0> <10> <7>
I/O
B4
<3>
I/O GIO
I/O
I/O
B4
CLK0 B3 GND B3
<0> CLK0
<9>
<5>
B
GND NC
1
I/O
B6
<6>
I/O
I/O
B6 GND B5
<3>
<8>
I/O
B5
<4>
I/O
I/O
B5 GND B4
<2>
<9>
I/O
B4
<6>
I/O
I/O
I/O
B3
B4 GND VCC B3
<1>
<10> <6>
I/O
I/O
B3 VCC GND B2
<4>
<7>
I/O
B2
<5>
C
VCC
I/O
B6
<9>
I/O
B6
<8>
I/O
B6
<7>
I/O
B4
<8>
I/O
B4
<5>
I/O
B3
<3>
I/O
B3
<1>
I/O
B2
<9>
I/O
I/O
I/O
B2
B1
B1
<2> <10> <6>
D
NC1
I/O
I/O
I/O
G0
B6
B6
<22> <11> <10>
VCCIO
I/O
B3
<0>
I/O
B2
<8>
I/O
B2
<0>
E
I/O
I/O
I/O
G0 GND G0
G0
<16>
<20> <23>
TMS/
MODE
F
I/O
I/O
I/O
I/O
G0
G0
G0
G0
<12> <15> <19> <21>
G
I/O
I/O
I/O
I/O
G0
G0
G0
G1
<15> <13> <17> <18>
H
I/O
I/O
I/O
G1
G1
G0
<16> <14> <14>
J
I/O
B6
<5>
I/O
I/O
I/O
B6
B5
B5
<2> <10> <7>
I/O
B5
<5>
I/O
B5
<1>
I/O
B4
<2>
2
1
NC1 VCC GND GND
A
I/O
I/O
I/O
I/O
B0
B0 GND B0
B1
<10> <8>
<4> <11>
I/O
B0 GND
<2>
B
I/O
B1
<3>
I/O
B1
<1>
I/O
B0
<7>
I/O
B1
<0>
I/O
B0
<9>
I/O
B0
<6>
I/O
I/O
B2 GND B1
<3>
<9>
I/O
B0
<4>
I/O
B0
<3>
I/O
G0 VCC
<0>
C
VCCIO
I/O
B0
<1>
I/O
B0
<0>
I/O
G0
<3>
NC1
D
I/O
TDI/
G0
SDI GND <7>
E
I/O
G0
<1>
I/O
G0
<2>
I/O
I/O
G0
G0
<5> <10>
F
I/O
G0
<4>
I/O
G0
<6>
I/O
G0
<8>
I/O
G1
<9>
G
I/O
I/O
I/O
G0
G1
G1
<9> <11> <8>
H
I/O
I/O
I/O
G1 GND G1
G1
<20>
<13> <12>
I/O
I/O
I/O
G0
G1 GND G1
<11> <10>
<5>
J
K
I/O
I/O
I/O
VCC G1
G1
G1
<19> <18> <17>
I/O
G1
<7>
I/O
G1
<6>
I/O
G1 VCC
<4>
K
L
I/O
I/O
I/O
I/O
G2
G1
G1
G1
<22> <23> <22> <21>
I/O
G1
<3>
I/O
G1
<2>
I/O
G1
<1>
I/O
G1
<0>
L
M
I/O
I/O
I/O
G2
G2
G2
<20> <21> <23>
VCCIO
I/O
G2
<0>
I/O
G2
<1>
I/O
G2
<2>
M
N
I/O
I/O
I/O
G2 GND G2
G2
<17>
<18> <19>
I/O
G2
<3>
I/O
I/O
G2 GND G2
<4>
<5>
N
P
I/O
I/O
G2 VCC CLK1 G2
<15>
<16>
I/O
G2
<7>
I/O
G2 VCC
<6>
R
I/O
I/O
QIO I/O
G2
G2
G2
CLK1 <12> <13> <14>
I/O
I/O
G2
G2
<10> <9>
T
GND
U
I/O
I/O
I/O
I/O
G3
G3
G3
G3
<16> <15> <14> <13>
VCCIO
I/O
B6
<0>
I/O
B5
<9>
VCCIO
I/O
I/O
B5
B4
<3> <11>
VCCIO
CLK
EN
I/O
I/O
QIO B3
B4 GOE
0 CLK0 <8>
<4>
I/O
B2
<4>
3
I/O
B0
<5>
I/O
B6
<4>
I/O
I/O
B3
B3
<11> <7>
I/O
I/O
I/O
B2
B1
B1
<1> <11> <7>
6
GND GND VCC
A
I/O
I/O
I/O
I/O
B3
B2
B2
B2 VCC
<2> <11> <10> <6>
8
VCCIO
I/O
B1
<8>
VCCIO
VCCIO
VCCIO
VCCIO
SET/
RESET
P
I/O
I/O
G2
G2
<8> <11>
R
QIO GOE GND
CLK3
3
T
I/O
I/O
I/O
I/O
G3
G3
G3
G3
<9> <10> <11> <8>
U
V
I/O
I/O
I/O
G3
G3 VCC G3
<19>
<18> <17>
I/O
G3
<7>
TOE VCC
I/O
G3
<6>
V
W
I/O
I/O
I/O
G3
G3 GND G3
<22>
<20> <21>
I/O
G3
<3>
I/O
I/O
G3 GND G3
<4>
<5>
W
Y
I/O
I/O
I/O
G4
G4
G3
<23> <22> <23>
I/O GOE
G3
1
<12>
ispLSI 8840
VCCIO
VCCIO
Bottom View
I/O
G3
<2>
I/O
G3
<1>
Y
VCCIO
I/O
G3
<0>
AA
I/O
I/O
I/O
I/O
G4
G4
G4
G4
<21> <20> <18> <19>
I/O
G4
<2>
I/O
G4
<1>
I/O
G4
<0>
I/O
G4
<3>
AA
AB
I/O
I/O
I/O
G4
G4
VCC G4
<17> <16> <15>
I/O
G4
<5>
I/O
G4
<4>
I/O
G4 VCC
<6>
AB
AC
I/O
I/O
I/O
G4
G4 GND G4
<14>
<13> <12>
I/O
G4
<8>
I/O
I/O
G4 GND G4
<7>
<9>
AC
AD
I/O
I/O
I/O
I/O
G5
G5
G5
G5
<12> <15> <13> <14>
I/O
I/O
I/O
I/O
G5
G4
G4
G5
<11> <11> <10> <10>
AD
AE
I/O
I/O
I/O
G5
G5
G5
<18> <17> <16>
AF
I/O
I/O
I/O
I/O
G5
G5
G5
G5
<19> <22> <21> <20>
AG
I/O
I/O
G5 GND B6
<23>
<12>
VCCIO
VCCIO
I/O
G5
<8>
I/O
G5
<9>
I/O
G5
<7>
AE
I/O
G5
<4>
I/O
G5
<5>
I/O
G5
<6>
I/O
G5
<3>
AF
I/O
G5
<0>
I/O
I/O
G5 GND G5
<1>
<2>
AG
AH
NC
I/O TDO/ TCK/
B0
NC1
<22> SDO SCLK
AH
AJ
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O GIO I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
B0 VCC
B0
B0
B0
B0
B0
B1
B1
B1
B2
B2
B2
B2
B3
B3
B3
B4
B4
B4
B5
B5
B5
B5
B5
B6
B6
B6
VCC B6
CLK1 <13> <17> <20> <12> <14> <19> <22> <14> <18> <20> <12> <15> <18> <20> <21> <23>
<16> <17> <18> <20> <12> <13> <17> <18> <23> <15> <17> <21>
AJ
AK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
B0 NC1 GND
B0 GND B0
B1
B2 GND B1
B2
B3 VCC GND B2
B3
B4 GND VCC B3
B4
B4 GND B4
B5
B6 GND B5
B6
<16> <19>
<15> <19> <13>
<18> <20> <21>
<14> <18> <21>
<16> <20> <22>
<16> <21> <13>
<21> <22>
AK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
QIO I/O
B1 NC1 VCC GND GND
B1
B1
B1
B2 VCC B2
B2
B2
B3
CLK2 CLK2 B3 GND B3
<23> <13> <17> <21> <23>
<15>
<19> <22> <13> <16> <17>
AL
AL
1
VCCIO
BSCAN
/ ispEN
I/O
I/O
I/O
B6
B6
B6
<13> <14> <15>
GND NC1
GND GND VCC NC1
VCCIO
I/O
I/O
I/O
B6
B6
B5
<19> <23> <14>
VCCIO
I/O
I/O
B5
B4
<20> <12>
I/O
I/O
I/O
I/O
I/O
I/O
B4 VCC B4
B4
B5
B5
B5
<23>
<15> <19> <22> <14> <18>
VCCIO
IOCLK
EN
I/O GOE I/O
I/O
B4
B3
B3
2 <12>
<19>
<16>
VCCIO
I/O
I/O
B3
B2
<23> <15>
VCCIO
I/O
I/O
B1
B1
<12> <16>
VCCIO
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
1. NC pins are not to be connected to any active signals, VCC or GND.
22
I/O
I/O
I/O
B1
B0
B0
<22> <14> <17>
8
7
6
VCCIO
5
4
3
2
1
Specifications ispLSI 8840
Part Number Description
ispLSI 8840 – XXX X
XXXX
Device Family
X
Grade
Blank = Commercial
Device Number
Package
B432 = BGA
Speed
110 = 110 MHz fmax
90 = 90 MHz fmax
60 = 60 MHz fmax
Power
L = Low
0212/8840
Ordering Information
COMMERCIAL
FAMILY
ispLSI
fmax (MHz)
tpd (ns)
ORDERING NUMBER
PACKAGE
110
8.5
ispLSI 8840-110LB432
432-Ball BGA
90
10
ispLSI 8840-90LB432
432-Ball BGA
60
15
ispLSI 8840-60LB432
432-Ball BGA
Table 2-0041/8840
23