LATTICE GAL20V8Z

GAL20V8Z
GAL20V8ZD
Zero Power E2CMOS PLD
Features
Functional Block Diagram
• ZERO POWER E2CMOS TECHNOLOGY
— 100µA Standby Current
— Input Transition Detection on GAL20V8Z
— Dedicated Power-down Pin on GAL20V8ZD
— Input and Output Latching During Power Down
I/CLK
I
IMUX
I
2
• HIGH PERFORMANCE E CMOS TECHNOLOGY
— 12 ns Maximum Propagation Delay
— Fmax = 83.3 MHz
— 8 ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Output Drive
— UltraMOS® Advanced CMOS Technology
CLK
8
OLMC
I/O/Q
8
OLMC
I/O/Q
8
OLMC
I/O/Q
8
OLMC
I/O/Q
8
OLMC
I/O/Q
8
OLMC
I/O/Q
8
OLMC
I/O/Q
8
OLMC
I/O/Q
I
• E2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
PROGRAMMABLE
AND-ARRAY
(64 X 40)
I/DPP
I
I
• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— Architecturally Similar to Standard GAL20V8
I
I
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
I
• APPLICATIONS INCLUDE:
— Battery Powered Systems
— DMA Control
— State Machine Control
— High Speed Graphics Processing
I
OE
I
I
IMUX
I/OE
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
Description
Pin Configuration
DIP
The GAL20V8Z and GAL20V8ZD, at 100 µA standby current and
12ns propagation delay provides the highest speed and lowest
power combination PLD available in the market. The
GAL20V8Z/ZD is manufactured using Lattice Semiconductor's advanced zero power E2CMOS process, which combines CMOS with
Electrically Erasable (E2) floating gate technology.
I/C LK
1
24
Vcc
I
2
23
I
I
3
22
I/ O/ Q
I/D P P
4
21
I/ O/ Q
I/O/Q
I
5
20
I/ O/ Q
I/O/Q
I
6
19
I/ O/ Q
NC
I
7
18
I/O/Q
I/O/Q
I
8
17
I/O/Q
I/O/Q
I
9
16
I/ O/ Q
I/O/Q
I
10
15
I/ O/ Q
I
11
14
I
GND
12
13
I /O E
14
GND
I
Vcc
I/O/Q
21
18
16
I/O/Q
12
23
I
11
I
I
9
GAL20V8Z
GAL20V8ZD
Top View
I/OE
I
7
NC
I
26
25
NC
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
I
I
28
5
I
I/DPP
NC
2
4
The GAL20V8Z uses Input Transition Detection (ITD) to put the
device in standby mode and is capable of emulating the full functionality of the standard GAL20V8. The GAL20V8ZD utilizes a
dedicated power-down pin (DPP) to put the device in standby mode.
It has 19 inputs available to the AND array.
I/CLK
I
I
PLCC
19
I/O/Q
GAL
20V8Z
20V8ZD
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
20v8zzd_03
1
December 1997
Specifications GAL20V8Z
GAL20V8ZD
GAL20V8Z/ZD Ordering Information
GAL20V8Z: Commercial Grade Specifications
Tpd (ns)
Tsu (ns)
Tco (ns)
Icc (mA)
ISB (µA)
Ordering #
12
10
8
55
100
GAL20V8Z-12QP
24-Pin Plastic DIP
55
100
GAL20V8Z-12QJ
28-Lead PLCC
55
100
GAL20V8Z-15QP
24-Pin Plastic DIP
55
100
GAL20V8Z-15QJ
28-Lead PLCC
15
15
10
Package
GAL20V8ZD: Commercial Grade Specifications
Tpd (ns)
Tsu (ns)
Tco (ns)
Icc (mA)
ISB (µA)
Ordering #
12
10
8
55
100
GAL20V8ZD-12QP
24-Pin Plastic DIP
55
100
GAL20V8ZD-12QJ
28-Lead PLCC
55
100
GAL20V8ZD-15QP
24-Pin Plastic DIP
55
100
GAL20V8ZD-15QJ
28-Lead PLCC
15
15
10
Package
Part Number Description
XXXXXXXX _ XX
Device Name
GAL20V8Z (Zero Power ITD)
GAL20V8ZD (Zero Power DPP)
X
X X
Grade
Blank = Commercial
Package
P = Plastic DIP
J = PLCC
Speed (ns)
Active Power
Q = Quarter Power
2
Specifications GAL20V8Z
GAL20V8ZD
Output Logic Macrocell (OLMC)
The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is accomplished by development software/hardware and is completely transparent to the user.
control the mode configuration for all macrocells. The XOR bit of
each macrocell controls the polarity of the output in any of the three
modes, while the AC1 bit of each of the macrocells controls the input/output configuration. These two global and 16 individual architecture bits define all possible configurations in a GAL20V8Z/ZD.
The information given on these architecture bits is only to give a
better understanding of the device. Compiler software will transparently set these architecture bits from the pin definitions, so the
user should not need to directly manipulate these architecture bits.
There are three global OLMC configuration modes possible:
simple, complex, and registered. Details of each of these modes
is illustrated in the following pages. Two global bits, SYN and AC0,
Compiler Support for OLMC
Software compilers support the three different global OLMC modes
as different device types. Most compilers also have the ability to
automatically select the device type, generally based on the register
usage and output enable (OE) usage. Register usage on the device
forces the software to choose the registered mode. All combinatorial outputs with OE controlled by the product term will force the
software to choose the complex mode. The software will choose
the simple mode only when all outputs are dedicated combinatorial
without OE control. For further details, refer to the compiler software manuals.
In complex mode pin 1(2) and pin 13(16) become dedicated inputs and use the feedback paths of pin 22(26) and pin 15(18) respectively. Because of this feedback path usage, pin 22(26) and
pin 15(18) do not have the feedback option in this mode.
In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins ( pins
18(21) and 19(23)) will not have the feedback option as these pins
are always configured as dedicated combinatorial output.
When using the standard GAL20V8 JEDEC fuse pattern generated
by the logic compilers for the GAL20V8ZD, special attention must
be given to pin 4(5) (DPP) to make sure that it is not used as one
of the functional inputs.
When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each mode.
In registered mode pin 1(2) and pin 13(16) are permanently configured as clock and output enable, respectively. These pins cannot
be configured as dedicated inputs in the registered mode.
3
Specifications GAL20V8Z
GAL20V8ZD
Registered Mode
In the Registered mode, macrocells are configured as dedicated
registered outputs or as I/O functions.
Registered outputs have eight product terms per output. I/Os have
seven product terms per output.
Architecture configurations available in this mode are similar to the
common 20R8 and 20RP4 devices with various permutations of
polarity, I/O and register placement.
Pin 4(5) is used as dedicated power-down pin on GAL20V8ZD. It
cannot be used as functional input.
The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product Term Disable (PTD) fuses, are shown
on the logic diagram on the following page.
All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or I/
O. Up to eight registers or up to eight I/Os are possible in this mode.
Dedicated input or output functions can be implemented as subsets of the I/O function.
CLK
Registered Configuration for Registered Mode
D
XOR
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this output configuration.
- Pin 1(2) controls common CLK for the registered
outputs.
- Pin 13(16) controls common OE for the registered
outputs.
- Pin 1(2) & Pin 13(16) are permanently configured as
CLK & OE for registered output configuration.
Q
Q
OE
Combinatorial Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this output configuration.
- Pin 1(2) & Pin 13(16) are permanently configured as
CLK & OE for registered output configuration.
XOR
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
4
Specifications GAL20V8Z
GAL20V8ZD
Registered Mode Logic Diagram
DIP (PLCC) Package Pinouts
1(2)
2640
0
4
8
12
16
20
24
28
32
36
PTD
2(3)
23(27)
0000
OLMC
22(26)
XOR-2560
AC1-2632
0280
3(4)
0320
OLMC
21(25)
XOR-2561
AC1-2633
0600
* 4(5)
0640
OLMC
20(24)
XOR-2562
AC1-2634
0920
5(6)
0960
OLMC
19(23)
XOR-2563
AC1-2635
1240
6(7)
1280
OLMC
18(21)
XOR-2564
AC1-2636
1560
7(9)
1600
OLMC
17(20)
XOR-2565
AC1-2637
1880
8(10)
1920
OLMC
16(19)
XOR-2566
AC1-2638
2200
9(11)
2240
OLMC
15(18)
XOR-2567
AC1-2639
2520
10(12)
14(17)
11(13)
OE
2703
64-USER ELECTRONIC SIGNATURE FUSES
2568, 2569, ....
.... 2630, 2631
Byte7 Byte6 ....
.... Byte1 Byte0
MSB
LSB
13(16)
SYN-2704
AC0-2705
* Note: Input not available on GAL20V8ZD
5
Specifications GAL20V8Z
GAL20V8ZD
Complex Mode
All macrocells have seven product terms per output. One product
term is used for programmable output enable control. Pins 1(2) and
13(16) are always available as data inputs into the AND array.
In the Complex mode, macrocells are configured as output only or
I/O functions.
Architecture configurations available in this mode are similar to the
common 20L8 and 20P8 devices with programmable polarity in
each macrocell.
Pin 4(5) is used as dedicated power-down pin on GAL20V8ZD. It
cannot be used as functional input.
The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.
Up to six I/Os are possible in this mode. Dedicated inputs or outputs
can be implemented as subsets of the I/O function. The two outer
most macrocells (pins 15(18) & 22(26)) do not have input capability.
Designs requiring eight I/Os can be implemented in the Registered
mode.
Combinatorial I/O Configuration for Complex Mode
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 has no effect on this mode.
- Pin 16(19) through Pin 21(25) are configured to this
function.
XOR
Combinatorial Output Configuration for Complex Mode
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 has no effect on this mode.
- Pin 15(18) and Pin 22(26) are configured to this
function.
XOR
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
6
Specifications GAL20V8Z
GAL20V8ZD
Complex Mode Logic Diagram
DIP (PLCC) Package Pinouts
1(2)
2640
0
4
8
12
16
20
24
28
32
36
PTD
2(3)
23(27)
0000
OLMC
22(26)
XOR-2560
AC1-2632
0280
3(4)
0320
OLMC
21(25)
XOR-2561
AC1-2633
0600
* 4(5)
0640
OLMC
20(24)
XOR-2562
AC1-2634
0920
5(6)
0960
OLMC
19(23)
XOR-2563
AC1-2635
1240
6(7)
1280
OLMC
18(21)
XOR-2564
AC1-2636
1560
7(9)
1600
OLMC
17(20)
XOR-2565
AC1-2637
1880
8(10)
1920
OLMC
16(19)
XOR-2566
AC1-2638
2200
9(11)
2240
OLMC
15(18)
XOR-2567
AC1-2639
2520
10(12)
14(17)
11(13)
13(16)
2703
64-USER ELECTRONIC SIGNATURE FUSES
2568, 2569, ....
.... 2630, 2631
Byte7 Byte6 ....
.... Byte1 Byte0
MSB
LSB
SYN-2704
AC0-2705
* Note: Input not available on GAL20V8ZD
7
Specifications GAL20V8Z
GAL20V8ZD
Simple Mode
In the Simple mode, macrocells are configured as dedicated inputs
or as dedicated, always active, combinatorial outputs.
Pins 1(2) and 13(16) are always available as data inputs into the
AND array. The center two macrocells (pins 18(21) & 19(23)) cannot be used in the input configuration.
Architecture configurations available in this mode are similar to the
common 14L8 and 16P6 devices with many permutations of generic output polarity or input choices.
Pin 4(5) is used as dedicated power-down pin on GAL20V8ZD. It
cannot be used as functional input.
All outputs in the simple mode have a maximum of eight product
terms that can control the logic. In addition, each output has programmable polarity.
The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram.
Combinatorial Output with Feedback Configuration
for Simple Mode
Vcc
- SYN=1.
- AC0=0.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this configuration.
- All OLMC except pins 18(21) & 19(23) can be
configured to this function.
XOR
Combinatorial Output Configuration for Simple Mode
Vcc
- SYN=1.
- AC0=0.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this configuration.
- Pins 18(21) & 19(23) are permanently configured to
this function.
XOR
Dedicated Input Configuration for Simple Mode
- SYN=1.
- AC0=0.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this configuration.
- All OLMC except pins 18(21) & 19(23) can be
configured to this function.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
8
Specifications GAL20V8Z
GAL20V8ZD
Simple Mode Logic Diagram
DIP (PLCC) Package Pinouts
1(2)
2640
0
4
8
12
16
20
24
28
32
36
PTD
23(27)
2(3)
OLMC
0000
XOR-2560
AC1-2632
0280
22(26)
3(4)
0320
OLMC
XOR-2561
AC1-2633
0600
21(25)
* 4(5)
0640
OLMC
XOR-2562
AC1-2634
0920
20(24)
5(6)
0960
OLMC
XOR-2563
AC1-2635
1240
19(23)
6(7)
1280
OLMC
XOR-2564
AC1-2636
1560
18(21)
7(9)
1600
OLMC
XOR-2565
AC1-2637
1880
17(20)
8(10)
1920
OLMC
XOR-2566
AC1-2638
2200
16(19)
9(11)
2240
OLMC
XOR-2567
AC1-2639
2520
15(18)
10(12)
14(17)
11(13)
13(16)
2703
64-USER ELECTRONIC SIGNATURE FUSES
2568, 2569, ....
.... 2630, 2631
Byte7 Byte6 ....
.... Byte1 Byte0
MSB
LSB
SYN-2704
AC0-2705
* Note: Input not available on GAL20V8ZD
9
Specifications GAL20V8Z
GAL20V8ZD
Absolute Maximum Ratings(1)
Recommended Operating Conditions
Supply voltage VCC ........................................ –.5 to +7V
Input voltage applied .......................... –2.5 to VCC +1.0V
Off-state output voltage applied ......... –2.5 to VCC +1.0V
Storage Temperature ................................ –65 to 150°C
Ambient Temperature with
Power Applied ........................................... –55 to 125°C
Commercial Devices:
Ambient Temperature (TA) ............................... 0 to 75°C
Supply voltage (VCC)
with Respect to Ground ..................... +4.75 to +5.25V
1. Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
VIL
VIH
IIL
IIH
VOL
VOH
MIN.
TYP.2
MAX.
UNITS
Input Low Voltage
Vss – 0.5
—
0.8
V
Input High Voltage
2.0
—
Vcc+1
V
PARAMETER
CONDITION
Input or I/O Low Leakage Current
0V ≤ VIN ≤ VIL (MAX.)
—
—
–10
µA
Input or I/O High Leakage Current
3.5V ≤ VIN ≤ VCC
—
—
10
µA
Output Low Voltage
IOL = MAX. Vin = VIL or VIH
—
—
0.5
V
Output High Voltage
IOH = MAX. Vin = VIL or VIH
2.4
—
—
V
Vcc-1
—
—
V
Low Level Output Current
—
—
16
mA
High Level Output Current
—
—
–3.2
mA
–30
—
–150
mA
IOH = -100 µA Vin = VIL or VIH
IOL
IOH
IOS1
Output Short Circuit Current
COMMERCIAL
ISB
Stand-by Power
VCC = 5V VOUT = 0.5V
VIL = GND VIH = Vcc Outputs Open
Z-12/-15
ZD-12/-15
—
50
100
µA
VIL = 0.5V VIH = 3.0V
ftoggle = 15 MHz Outputs Open
Z-12/-15
ZD-12/-15
—
—
55
mA
Supply Current
ICC
Operating Power
Supply Current
TA = 25°C
1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground
degradation. Characterized but not 100% tested.
2) Typical values are at Vcc = 5V and TA = 25 °C
Capacitance (TA = 25°C, f = 1.0 MHz)
SYMBOL
PARAMETER
MAXIMUM*
UNITS
TEST CONDITIONS
CI
Input Capacitance
10
pF
VCC = 5.0V, VI = 2.0V
CI/O
I/O Capacitance
10
pF
VCC = 5.0V, VI/O = 2.0V
*Characterized but not 100% tested
10
Specifications GAL20V8Z
Specifications
GAL20V8Z
GAL20V8ZD
AC Switching Characteristics
Over Recommended Operating Conditions
PARAMETER
tpd
tco
tcf2
tsu
th
fmax3
twh
twl
ten
tdis
tas
tsa4
TEST
COND1.
COM
COM
-12
-15
DESCRIPTION
MIN.
MAX. MIN.
MAX.
UNITS
A
Input or I/O to Combinational Output
3
12
3
15
ns
A
Clock to Output Delay
2
8
2
10
ns
—
Clock to Feedback Delay
—
6
—
7
ns
—
Setup Time, Input or Feedback before Clock↑
10
—
15
—
ns
—
Hold Time, Input or Feedback after Clock↑
0
—
0
—
ns
A
Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
55
—
40
—
MHz
A
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
62.5
—
45.5
—
MHz
A
Maximum Clock Frequency with
No Feedback
83.3
—
62.5
—
MHz
—
Clock Pulse Duration, High
6
—
8
—
ns
—
Clock Pulse Duration, Low
6
—
8
—
ns
B
Input or I/O to Output Enabled
—
12
—
15
ns
B
OE to Output Enabled
—
12
—
15
ns
C
Input or I/O to Output Disabled
—
15
—
15
ns
C
OE to Output Disabled
—
12
—
15
ns
—
Last Active Input to Standby
60
140
50
150
ns
—
Standby to Active Output
6
13
5
15
ns
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Specification section.
3) Refer to fmax Specification section.
4) Add tsa to tpd, tsu, ten and tdis when the device is coming out of standby state.
Standby Power Timing Waveforms
Icc
POWER
Isb
t as
tsa
tpd
INPUT or
I/O FEEDBACK
ten, tdis
OE
*
tsu
* Note: Rising clock edges
are allowed during tsa but
outputs are not guaranteed.
CLK
tco
OUTPUT
11
Specifications GAL20V8Z
Specifications GAL20V8ZD
GAL20V8ZD
AC Switching Characteristics
Over Recommended Operating Conditions
PARAMETER
tpd
tco
tcf2
tsu
th
fmax3
twh
twl
ten
tdis
TEST
COND1.
COM
COM
-12
-15
MIN. MAX.
MIN. MAX.
DESCRIPTION
UNITS
A
Input or I/O to Combinational Output
3
12
3
15
ns
A
Clock to Output Delay
2
8
2
10
ns
—
Clock to Feedback Delay
—
6
—
7
ns
—
Setup Time, Input or Feedback before Clock↑
10
—
15
—
ns
—
Hold Time, Input or Feedback after Clock↑
0
—
0
—
ns
A
Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
55
—
40
—
MHz
A
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
62.5
—
45.5
—
MHz
A
Maximum Clock Frequency with
No Feedback
83.3
—
62.5
—
MHz
—
Clock Pulse Duration, High
6
—
8
—
ns
—
Clock Pulse Duration, Low
6
—
8
—
ns
B
Input or I/O to Output Enabled
—
12
—
15
ns
B
OE to Output Enabled
—
12
—
15
ns
C
Input or I/O to Output Disabled
—
15
—
15
ns
C
OE to Output Disabled
—
12
—
15
ns
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Specification section.
3) Refer to fmax Specification section.
12
Specifications GAL20V8Z
Specifications GAL20V8ZD
GAL20V8ZD
Dedicated Power-Down Pin Specifications
Over Recommended Operating Conditions
PARAMETER
twhd
twld
TEST
COND1.
COM
COM
-12
-15
MIN. MAX.
MIN. MAX.
DESCRIPTION
UNITS
—
DPP Pulse Duration High
12
—
15
—
ns
—
DPP Pulse Duration Low
25
—
30
—
ns
—
Valid Input before DPP High
5
—
8
—
ns
—
Valid OE before DPP High
0
—
0
—
ns
—
Valid Clock Before DPP High
0
—
0
—
ns
—
Input Don't Care after DPP High
—
2
—
5
ns
—
OE Don't Care after DPP High
—
6
—
9
ns
—
Clock Don't Care after DPP High
—
8
—
11
ns
—
DPP Low to Valid Input
12
—
15
—
ns
—
DPP Low to Valid OE
16
—
20
—
ns
—
DPP Low to Valid Clock
18
—
20
—
ns
A
DPP Low to Valid Output
5
24
5
30
ns
ACTIVE TO STANDBY
tivdh
tgvdh
tcvdh
tdhix
tdhgx
tdhcx
STANDBY TO ACTIVE
tdliv
tdlgv
tdlcv
tdlov
1) Refer to Switching Test Conditions section.
Dedicated Power-Down Pin Timing Waveforms
DPP
t ivdh
t dhix
t dliv
t gvdh
t dhgx
t dlgv
INPUT or
I/O FEEDBACK
OE
t cvdh
t dhcx
t dlcv
CLK
tc o
t p d ,t e n ,t di s
OUTPUT
13
t dlov
Specifications GAL20V8Z
GAL20V8ZD
Switching Waveforms
INPUT or
I/O FEEDBACK
INPUT or
I/O FEEDBACK
VALID INPUT
VALID INPUT
tsu
tpd
th
CLK
COMBINATIONAL
OUTPUT
tco
REGISTERED
OUTPUT
1/fmax
(external fdbk)
Combinatorial Output
INPUT or
I/O FEEDBACK
Registered Output
tdis
ten
COMBINATIONAL
OUTPUT
OE
tdis
Input or I/O to Output Enable/Disable
ten
REGISTERED
OUTPUT
OE to Output Enable/Disable
twh
twl
CLK
CLK
1/ fmax
(w/o fb)
1/ fmax (internal fdbk)
tcf
REGISTERED
FEEDBACK
Clock Width
fmax with Feedback
14
tsu
Specifications GAL20V8Z
GAL20V8ZD
fmax Specifications
CL K
LOGIC
ARR AY
R EG I S T E R
CLK
LOGIC
ARRAY
ts u
tc o
REGISTER
fmax with External Feedback 1/(tsu+tco)
Note: fmax with external feedback is calculated from
measured tsu and tco.
t cf
t pd
CLK
fmax with Internal Feedback 1/(tsu+tcf)
LOGIC
ARRAY
Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal
feedback (tcf = 1/fmax - tsu). The value of tcf is
used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combinatorial output is equal to tcf + tpd.
REGISTER
tsu + th
fmax with No Feedback
Note: fmax with no feedback may be less than 1/(twh
+ twl). This is to allow for a clock duty cycle of other
than 50%.
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
+5V
GND to 3.0V
3ns 10% – 90%
1.5V
1.5V
R1
See Figure
3-state levels are measured 0.5V from steady-state active
level.
FROM OUTPUT (O/Q)
UNDER TEST
Output Load Conditions (see figure)
Test Condition
A
B
Active High
Active Low
C
Active High
Active Low
R1
300Ω
∞
300Ω
∞
300Ω
TEST POINT
R2
R2
390Ω
390Ω
390Ω
390Ω
390Ω
CL
50pF
50pF
50pF
5pF
5pF
C L*
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
15
Specifications GAL20V8Z
GAL20V8ZD
Electronic Signature
Output Register Preload
An electronic signature word is provided in every GAL20V8Z/ZD
device. It contains 64 bits of reprogrammable memory that can
contain user defined data. Some uses include user ID codes,
revision numbers, or inventory control. The signature data is always available to the user independent of the state of the security
cell.
When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because, in system
operation, certain events occur that may throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired (i.e.,
illegal) state into the registers. Then the machine can be sequenced
and the outputs tested for correct next state conditions.
NOTE: The electronic signature is included in checksum calculations. Changing the electronic signature will alter checksum.
The GAL20V8Z/ZD devices includes circuitry that allows each registered output to be synchronously set either high or low. Thus, any
present state condition can be forced for test sequencing. If necessary, approved GAL programmers capable of executing text
vectors perform output register preload automatically.
Security Cell
A security cell is provided in the GAL20V8Z/ZD devices to prevent
unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the functional bits in the
device. This cell can only be erased by re-programming the device, so the original configuration can never be examined once this
cell is programmed. The electronic signature data is always available to the user, regardless of the state of this security cell.
Input Buffers
GAL20V8Z/ZD devices are designed with TTL level compatible input buffers. These buffers, with their characteristically high impedance, load driving logic much less than traditional bipolar devices.
This allows for a greater fan out from the driving logic.
Device Programming
GAL devices are programmed using a Lattice Semiconductorapproved Logic Programmer, available from a number of manufacturers (see the GAL Development Tools Section of the Data
Book). Complete programming of the device takes only a few
seconds. Erasing of the device is transparent to the user, and is
done automatically as part of the programming cycle.
GAL20V8Z/ZD input buffers have latches within the buffers. As a
result, when the device goes into standby mode the inputs will be
latched to its values prior to standby. In order to overcome the input
latches, they will have to be driven by an external source. Lattice
Semiconductor recommends that all unused inputs and tri-stated
I/O pins for both devices be connected to another active input, VCC,
or GND. Doing this will tend to improve noise immunity and reduce
ICC for the device.
Input Transition Detection (ITD)
The GAL20V8Z relies on its internal input detection circuitry to put
the device in power down mode. If there is no input transition for
the specified period of time, the device will go into the power down
state. Any valid input transition will put the device back into active
state. The first rising clock transition from power-down state only
acts as a wake up signal into the device and will not clock the data
input through to the output (refer to standby power timing waveform
for more detail). Any input pulse widths greater than 5ns at input
voltage level of 1.5V will be detected as input transition. The device
will not detect any input pulse widths less than 1ns measured at
input voltage level of 1.5V as input transition.
Typical Input Characteristic
40
Input Current (uA)
30
Dedicated Power-Down Pin
20
10
0
-10
-20
-30
The GAL20V8ZD uses pin 4 (pin 5 on PLCC) as the dedicated
power-down signal to put the device in power-down state. DPP is
an active high signal where logic high driven on this signal puts the
device into power-down state. Input pin 4 (5) cannot be used as
a functional input on this device.
-40
0
1
2
3
Input Voltage (Volts)
16
4
5
Specifications GAL20V8Z
GAL20V8ZD
Power-Up Reset
Vcc
Vcc (min.)
t su
t wl
CLK
t pr
INTERNAL REGISTER
Q - OUTPUT
Internal Register
Reset to Logic "0"
FEEDBACK/EXTERNAL
OUTPUT REGISTER
Device Pin
Reset to Logic "1"
asynchronous nature of system power-up, some conditions must
be met to provide a valid power-up reset of the GAL20V8Z/ZD.
First, the VCC rise must be monotonic. Second, the clock input
must be at static TTL level as shown in the diagram during power
up. The registers will reset within a maximum of tpr time. As in
normal system operation, avoid clocking the device until all input
and feedback path setup times have been met. The clock must
also meet the minimum pulse width requirements.
Circuitry within the GAL20V8Z/ZD provides a reset signal to all
registers during power-up. All internal registers will have their Q
outputs set low after a specified time (tpr, 1µs MAX). As a result,
the state on the registered output pins (if they are enabled) will
always be high on power-up, regardless of the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. The
timing diagram for power-up is shown below. Because of the
Input/Output Equivalent Schematics
PIN
PIN
Feedback
Vcc
Vcc
Tri-State
Control
Vcc
Vcc
ESD
Protection
Circuit
Data
Output
PIN
ESD
Protection
Circuit
PIN
Feedback
(To Input Buffer)
Typical Input
Typical Output
17
Specifications GAL20V8Z
GAL20V8ZD
Typical AC and DC Characteristics
Normalized Tpd vs Vcc
1.4
1.2
PT L->H
1
0.9
0.8
1.1
FALL
1
0.9
4.75
5.00
5.25
5.50
4.50
1.2
PT L->H
1.1
1
0.9
4.75
5.00
5.25
4.50
5.50
4.75
5.00
5.25
5.50
Supply Voltage (V)
Supply Voltage (V)
Supply Voltage (V)
Normalized Tpd vs Temp
Normalized Tco vs Temp
Normalized Tsu vs Temp
1.3
0.9
0.8
0.8
Temperature (deg. C)
Delta Tco vs # of Outputs
Switching
0
Delta Tco (ns)
0
-0.5
-1
RISE
-1.5
FALL
-2
-0.5
-1
RISE
-1.5
FALL
-2
1
2
3
4
5
6
7
8
1
Number of Outputs Switching
2
3
4
5
6
7
8
Number of Outputs Switching
Delta Tpd vs Output Loading
Delta Tco vs Output Loading
10
RISE
6
FALL
Delta Tco (ns)
10
8
4
2
0
8
RISE
6
FALL
4
2
0
-2
-2
0
50
100
150
200
250
300
0
Output Loading (pF)
50
100
150
200
250
Output Loading (pF)
18
100
-55
125
100
75
50
Delta Tpd vs # of Outputs
Switching
Delta Tpd (ns)
1
0.9
Temperature (deg. C)
Temperature (deg. C)
Delta Tpd (ns)
PT L->H
1.1
0.7
25
-25
-55
125
100
75
50
25
0
-25
0
0.7
0.7
PT H->L
1.2
75
0.8
1
1.3
50
0.9
1.1
FALL
0
1
RISE
25
1.1
PT L->H
1.4
1.2
-25
PT H->L
Normalized Tsu
1.2
Normalized Tco
1.3
-55
PT H->L
0.8
0.8
4.50
1.3
300
125
1.1
RISE
Normalized Tsu
PT H->L
Normalized Tco
Normalized Tpd
1.2
Normalized Tpd
Normalized Tsu vs Vcc
Normalized Tco vs Vcc
Specifications GAL20V8Z
GAL20V8ZD
Typical AC and DC Characteristics
Voh vs Ioh
Voh vs Ioh
5
5
1.25
4
4.5
1
0.75
0.5
Voh (V)
1.5
Voh (V)
Vol (V)
Vol vs Iol
3
2
0
2.5
0
0.00
20.00
40.00
60.00
3.5
3
1
0.25
4
0.00
10.00
20.00
Iol (mA)
30.00
40.00
50.00
0.00
60.00
1.00
Normalized Icc vs Vcc
Normalized Icc vs Temp
1.30
2.00
3.00
4.00
Ioh(mA)
Ioh(mA)
Normalized Icc vs Freq. (DPP
& ITD > 10MHz)
1.2
1.10
1.00
0.90
0.80
0.70
1.1
Normalized Icc
Normalized Icc
Normalized Icc
1.30
1.20
1
0.9
0.8
4.50
4.75
5.00
5.25
5.50
1.20
1.10
1.00
0.90
0.80
-55
Supply Voltage (V)
-25
0
25
50
75
100
125
0
Temperature (deg. C)
Delta Icc vs Vin (1 input)
50
75
100
Frequency (MHz)
Normalized Icc vs Freq. (ITD)
Input Clamp (Vik)
5
25
1
0
Normalized Icc
4
20
Iik (mA)
Delta Icc (mA)
10
3
2
1
30
40
50
60
70
0.8
0.6
0.4
0.2
80
0
90
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
Vin (V)
-1.00
0
-0.80
-0.60
-0.40
Vik (V)
19
-0.20
0.00
1
10
100
1000
Frequency (KHz)
10000