LT6301 Dual 500mA, Differential xDSL Line Driver in 28-Lead TSSOP Package U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LT®6301 is a 500mA minimum output current, quad op amp with outstanding distortion performance. The amplifiers are gain-of-ten stable, but can be easily compensated for lower gains. The extended output swing allows for lower supply rails to reduce system power. Supply current is set with an external resistor to optimize power dissipation. The LT6301 features balanced, high impedance inputs with low input bias current and input offset voltage. Active termination is easily implemented for further system power reduction. Short-circuit protection and thermal shutdown ensure the device’s ruggedness. Drives Two Lines from One Package Exceeds All Requirements For Full Rate, Downstream ADSL Line Drivers Power Enhanced 28-Lead TSSOP Package Power Saving Adjustable Supply Current ±500mA Minimum IOUT ±11.1V Output Swing, VS = ±12V, RL = 100Ω ±10.9V Output Swing, VS = ±12V, IL = 250mA Low Distortion: – 82dBc at 1MHz, 2VP-P Into 50Ω 200MHz Gain Bandwidth 600V/µs Slew Rate Specified at ±12V and ±5V The outputs drive a 100Ω load to ±11.1V with ±12V supplies, and ±10.9V with a 250mA load. The LT6301 is a functional replacement for the LT1739 and LT1794 in xDSL line driver applications and requires no circuit changes. U APPLICATIO S ■ ■ ■ ■ ■ High Density ADSL Central Office Line Drivers High Efficiency ADSL, HDSL2, SHDSL Line Drivers Buffers Test Equipment Amplifiers Cable Drivers The LT6301 is available in the very small, thermally enhanced, 28-lead TSSOP package for maximum port density in line driver applications. , LTC and LT are registered trademarks of Linear Technology Corporation. U TYPICAL APPLICATIO High Efficiency ±12V Supply ADSL Line Driver 12V 24.9k + +IN 1/4 LT6301 SHDN 12.7Ω TWO COMPLETE ADSL LINE DRIVERS PROVIDED WITH ONE LT6301 PACKAGE – 1k 1:2* • • 110Ω 100Ω 1000pF 110Ω 1k – 1/4 LT6301 –IN + 12.7Ω *COILCRAFT X8390-A OR EQUIVALENT ISUPPLY = 10mA PER AMPLIFIER WITH RSHDN = 24.9k SHDNREF 6301 TA01 –12V sn6301 6301f 1 LT6301 U W U U W W W ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER INFORMATION (Note 1) Supply Voltage (V + to V –) ................................. ±13.5V Input Current ..................................................... ±10mA Output Short-Circuit Duration (Note 2) ........... Indefinite Operating Temperature Range ............... – 40°C to 85°C Specified Temperature Range (Note 3) .. – 40°C to 85°C Junction Temperature .......................................... 150°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER TOP VIEW V– V– 1 –IN A 2 +IN A 3 SHDN1 4 25 V + SHDNREF1 5 24 V + +IN B 6 –IN B 7 –IN C 8 +IN C 9 28 27 V – A 23 OUT B B 22 V – 21 V – C 20 OUT C SHDN2 10 19 V + SHDNREF2 11 18 V + +IN D 12 –IN D 13 LT6301CFE LT6301IFE 26 OUT A 17 OUT D D 16 V – 15 V – V – 14 FE PACKAGE 28-LEAD PLASTIC TSSOP TJMAX = 150°C, θJA = 25°C/W (NOTE 4) UNDERSIDE METAL CONNECTED TO V – Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full specified temperature range, otherwise specifications are at TA = 25°C. VCM = 0V, pulse tested, ±5V ≤ VS ≤ ±12V, VSHDNREF = 0V, RBIAS = 24.9k between V + and SHDN unless otherwise noted. (Note 3) SYMBOL PARAMETER VOS Input Offset Voltage CONDITIONS MIN TYP MAX 1 5.0 7.5 mV mV 0.3 5.0 7.5 mV mV ● Input Offset Voltage Matching (Note 6) ● Input Offset Voltage Drift IOS 100 500 800 nA nA ±0.1 ±4 ±6 µA µA 100 500 800 nA nA ● IB Input Bias Current ● Input Bias Current Matching µV/°C 10 ● Input Offset Current (Note 6) UNITS ● en Input Noise Voltage Density f = 10kHz 8 nV/√Hz in Input Noise Current Density f = 10kHz 0.8 pA/√Hz RIN Input Resistance VCM = (V + – 2V) to (V –+ 2V) Differential 50 6.5 MΩ MΩ CIN Input Capacitance 3 pF CMRR Input Voltage Range (Positive) Input Voltage Range (Negative) (Note 5) (Note 5) Common Mode Rejection Ratio VCM = (V + – 2V) to (V – + 2V) 5 ● ● ● ● V+ –2 74 66 V+ –1 V– + 1 83 V– + 2 V V dB dB sn6301 6301f 2 LT6301 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full specified temperature range, otherwise specifications are at TA = 25°C. VCM = 0V, pulse tested, ±5V ≤ VS ≤ ±12V, VSHDNREF = 0V, RBIAS = 24.9k between V + and SHDN unless otherwise noted. (Note 3) SYMBOL PARAMETER CONDITIONS PSRR Power Supply Rejection Ratio VS = ±4V to ±12V AVOL Large-Signal Voltage Gain MIN TYP 74 66 88 ● dB dB 63 57 76 ● dB dB 60 54 70 ● dB dB 10.9 10.7 11.1 ● ±V ±V 10.6 10.4 10.9 ● ±V ±V 3.7 3.5 4 ● ±V ±V 3.6 3.4 3.9 ● ±V ±V 500 1200 mA 8.0 6.7 10 VS = ±12V, VOUT = ±10V, RL = 40Ω VS = ±5V, VOUT = ±3V, RL = 25Ω VOUT Output Swing VS = ±12V, RL = 100Ω VS = ±12V, IL = 250mA VS = ±5V, RL = 25Ω VS = ±5V, IL = 250mA IOUT Maximum Output Current VS = ±12V, RL = 1Ω IS Supply Current per Amplifier VS = ±12V, RBIAS = 24.9k (Note 7) VS = ±12V, RBIAS = 32.4k (Note 7) VS = ±12V, RBIAS = 43.2k (Note 7) VS = ±12V, RBIAS = 66.5k (Note 7) ● ● 2.2 1.8 VSHDN = 0.4V Output Leakage in Shutdown VSHDN = 0.4V Channel Separation VS = ±12V, VOUT = ±10V, RL = 40Ω (Note 8) UNITS 13.5 15.0 mA mA mA mA mA 3.4 5.0 5.8 mA mA 0.1 1 mA 0.3 1 mA 8 6 4 VS = ±5V, RBIAS = 24.9k (Note 7) Supply Current in Shutdown MAX 80 77 110 dB dB VS = ±12V, AV = – 10, (Note 9) 300 600 V/µs VS = ±5V, AV = –10, (Note 9) 100 ● SR Slew Rate 200 V/µs HD2 Differential 2nd Harmonic Distortion VS = ±12V, AV = 10, 2VP-P, RL = 50Ω, 1MHz – 85 dBc HD3 Differential 3rd Harmonic Distortion VS = ±12V, AV = 10, 2VP-P, RL = 50Ω, 1MHz – 82 dBc GBW Gain Bandwidth f = 1MHz 200 MHz Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Applies to short circuits to ground only. A short circuit between the output and either supply may permanently damage the part when operated on supplies greater than ±10V. Note 3: The LT6301C is guaranteed to meet specified performance from 0°C to 70°C and is designed, characterized and expected to meet these extended temperature limits, but is not tested at – 40°C and 85°C. The LT6301I is guaranteed to meet the extended temperature limits. Note 4: Thermal resistance varies depending upon the amount of PC board metal attached to Pins 1, 14, 15, 28 and the exposed bottom side metal of the device. If the maximum dissipation of the package is exceeded, the device will go into thermal shutdown and be protected. Note 5: Guaranteed by the CMRR tests. Note 6: Matching is between amplifiers A and B or between amplifiers C and D. Note 7: RBIAS is connected between V + and each SHDN pin, with each SHDNREF pin grounded. Note 8: Channel separation is measured between amplifiers A and B and between amplifiers C and D. Channel separation between any other combination of amplifiers is guaranteed by design as two separate die are used in the package. Note 9: Slew rate is measured at ±5V on a ±10V output signal while operating on ±12V supplies and ±1V on a ±3V output signal while operating on ±5V supplies. sn6301 6301f 3 LT6301 U W TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs Ambient Temperature 13 12 11 10 9 200 VS = ±12V 180 IS PER AMPLIFIER = 10mA TA = 25°C ∆VOS > 1mV –0.5 COMMON MODE RANGE (V) 14 –1.0 160 –1.5 140 –2.0 2.0 80 60 40 6 0.5 20 5 –50 V– –30 –10 10 30 50 TEMPERATURE (°C) 70 90 2 4 8 10 6 SUPPLY VOLTAGE (±V) 12 1 1 INPUT CURRENT NOISE (pA/√Hz) 10 in V+ 760 740 720 700 SINKING 680 SOURCING 660 640 620 0.1 10 1 100 1k FREQUENCY (Hz) 600 –50 0.1 100k 10k –30 30 –10 10 50 TEMPERATURE (°C) 6301 G04 120 45 100 80 40 –40 20 –80 GAIN 0 –20 –40 –60 –120 –160 TA = 25°C VS = ±12V AV = –10 RL = 100Ω IS PER AMPLIFIER = 10mA –80 100k 1M 10M FREQUENCY (Hz) 70 RL = 100Ω –1.0 ILOAD = 250mA –1.5 1.5 ILOAD = 250mA 1.0 RL = 100Ω 0.5 V– – 50 –30 90 –200 100M 6300 G07 50 30 10 TEMPERATURE (°C) 70 –10 Slew Rate vs Supply Current 1000 TA = 25°C VS = ±12V AV = 10 RL = 100Ω 35 900 800 30 25 20 15 10 –240 5 –280 0 90 6301 G06 SLEW RATE (V/µs) 40 PHASE (DEG) 0 –3dB BANDWIDTH (MHz) 40 60 90 VS = ±12V –0.5 –3dB Bandwidth vs Supply Current 120 80 70 6301 G05 Open-Loop Gain and Phase vs Frequency PHASE 10 30 50 –10 TEMPERATURE (°C) Output Saturation Voltage vs Ambient Temperature VS = ±12V IS PER AMPLIFIER = 10mA 780 en 10 800 100 TA = 25°C VS = ±12V IS PER AMPLIFIER = 10mA –30 6301 G03 Output Short-Circuit Current vs Ambient Temperature ISC (mA) 100 0 –50 14 6301 G02 Input Noise Spectral Density INPUT VOLTAGE NOISE (nV/√Hz) 100 1.0 6301 G01 GAIN (dB) 120 1.5 8 7 OUTPUT SATURATION VOLTAGE (V) ISUPPLY PER AMPLIFIER (mA) V+ VS = ±12V RBIAS = 24.9k TO SHDN VSHDNREF = 0V Input Bias Current vs Ambient Temperature ±IBIAS (nA) 15 Input Common Mode Range vs Supply Voltage 700 600 TA = 25°C VS = ±12V AV = –10 RL = 1k RISING FALLING 500 400 300 200 100 2 4 6 8 10 12 14 SUPPLY CURRENT PER AMPLIFIER (mA) 6301 G08 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SUPPLY CURRENT PER AMPLIFIER (mA) 6301 G09 sn6301 6301f 4 LT6301 U W TYPICAL PERFOR A CE CHARACTERISTICS CMRR vs Frequency 100 80 70 60 50 40 30 20 80 0 0.1 1 10 FREQUENCY (MHz) 100 15 60 50 (–) SUPPLY 40 30 (+) SUPPLY 20 –15 –10 0.01 –20 0.1 1 10 FREQUENCY (MHz) ISHDN (mA) IS PER AMPLIFIER = 10mA IS PER AMPLIFIER = 15mA 1.5 1.0 0.5 0 100 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VSHDN (V) 0 –40 f = 1MHz TA = 25°C –50 VS = ±12V AV = 10 RL = 50Ω –60 I PER AMPLIFIER = 10mA S –45 DISTORTION (dBc) –50 HD3 –70 –80 HD2 –55 –100 10 25 20 15 10 5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VSHDN (V) 12 14 6301 G15 –60 VO = 10VP-P TA = 25°C VS = ±12V AV = 10 RL = 50Ω IS PER AMPLIFIER = 10mA –65 –70 –75 –85 8 TA = 25°C VS = ±12V VSHDNREF = 0V 30 HD3 –80 –90 6 6301 G12 Differential Harmonic Distortion vs Frequency –40 4 100M 6301 G14 Differential Harmonic Distortion vs Output Amplitude 2 100k 1M 10M FREQUENCY (Hz) Supply Current vs VSHDN TA = 25°C VS = ±12V VSHDNREF = 0V 6301 G13 DISTORTION (dBc) OUTPUT IMPEDANCE (Ω) 10 0 10k 35 2.0 IS PER AMPLIFIER = 2mA 1 10 FREQUENCY (MHz) 1k 100 ISHDN vs VSHDN 100 0.1 15mA PER AMPLIFIER 6301 G11 TA = 25°C VS ±12V 0.01 0.01 5 –10 2.5 0.1 10mA PER AMPLIFIER 0 0 Output Impedance vs Frequency 1 2mA PER AMPLIFIER 10 –5 10 6301 G10 1000 20 70 10 VS = ±12V AV = 10 25 SUPPLY CURRENT PER AMPLIFIER (mA) 90 30 VS = ±12V AV = 10 IS = 10mA PER AMPLIFIER 90 GAIN (dB) TA = 25°C VS = ±12V IS = 10mA PER AMPLIFIER POWER SUPPLY REJECTION (dB) COMMON MODE REJECTION RATIO (dB) 100 Frequency Response vs Supply Current PSRR vs Frequency 16 18 VOUT(P-P) 6301 G16 HD2 –90 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (kHz) 6301 G17 sn6301 6301f 5 LT6301 U W TYPICAL PERFOR A CE CHARACTERISTICS Differential Harmonic Distortion vs Supply Current –40 20 –50 OUTPUT VOLTAGE (VP-P) VO = 10VP-P VS = ±12V AV = 10 RL = 50Ω –45 DISTORTION (dBc) Undistorted Output Swing vs Frequency –55 f = 1MHz, HD3 –60 –65 f = 100kHz, HD2 –70 –75 15 10 SFDR > 40dB TA = 25°C VS = ±12V AV = 10 RL = 50Ω IS PER AMPLIFIER = 10mA 5 f = 100kHz, HD3 –80 f = 1MHz, HD2 –85 2 3 4 5 6 7 8 9 10 ISUPPLY PER AMPLIFIER (mA) 0 100k 11 300k 1M 3M FREQUENCY (Hz) 10M 6301 G19 6301 G18 TEST CIRCUIT SUPPLY BYPASSING TO PINS: 18, 19, 24 AND 25 0.1µF 0.1µF RBIAS RBIAS 4 (SHDN) 4.7µF –12V VOUT(P-P) 26 OR 20 12.7Ω 1k OUT (+) 110Ω OUT (–) 110Ω 1:2* RL ≈ 50Ω SPLITTER MINICIRCUITS ZSC5-2-2 0.1µF – –12V 49.9Ω 4.7µF TO PINS: 1, 14, 15, 16, 21, 22, 27 AND 28 10k EIN + 10 + A OR C 2 OR 8 4.7µF + 12V 3 OR 9 12V + 100 LINE LOAD 10k 7 OR 13 0.01µF 1k – B OR D 6 OR 12 + 23 OR 17 12.7Ω 6301 TC 5 (SHDNREF) 11 *COILCRAFT X8390-A OR EQUIVALENT VOUTP-P AMPLITUDE SET AT EACH AMPLIFIER OUTPUT DISTORTION MEASURED ACROSS LINE LOAD FOR MATCHING, USE AMPLIFIERS A AND B, OR AMPLIFIERS C AND D sn6301 6301f 6 LT6301 U W U U APPLICATIO S I FOR ATIO The LT6301 is a high speed, 200MHz gain bandwidth product, quad voltage feedback amplifier with high output current drive capability, 500mA source and sink. The LT6301 is ideal for use as a line driver in xDSL data communication applications. The output voltage swing has been optimized to provide sufficient headroom when operating from ±12V power supplies in full-rate ADSL applications. The LT6301 also allows for an adjustment of the operating current to minimize power consumption. In addition, the LT6301 is available in a small footprint surface mount package to minimize PCB area. Setting the Quiescent Operating Current Power consumption and dissipation are critical concerns in multiport xDSL applications. Two pins, Shutdown (SHDN) and Shutdown Reference (SHDNREF), are provided to control quiescent power consumption and allow for the complete shutdown of the drivers. The quiescent current should be set high enough to prevent distortion induced errors in a particular application, but not so high that power is wasted in the driver unnecessarily. A good starting point to evaluate the LT6301 is to set the quiescent current to 10mA per amplifier. Pins 4 and 5 set the current for amplifiers A and B and Pins 10 and 11 set the current for amplifers C and D. Each amplifier pair should be controlled separately. To minimize signal distortion, the LT6301 amplifiers are decompensated to provide very high open-loop gain at high frequency. As a result each amplifier is frequency stable with a closed-loop gain of 10 or more. If a closedloop gain of less than 10 is desired, external frequency compensating components can be used. The internal biasing circuitry is shown in Figure 1. Grounding the SHDNREF pin and directly driving the SHDN pin with a voltage can control the operating current as seen in the Typical Performance Characteristics. When the SHDN pin is less than SHDNREF + 0.4V, the driver is shut down and consumes typically only 100µA of supply current and the outputs are in a high impedance state. Part to part variations, however, will cause inconsistent control of the quiescent current if direct voltage drive of the SHDN pin is used. SHDN 5I 2k I 2I 2I Using an external resistor, RBIAS, connected in one of two ways provides a much more predictable control of the quiescent supply current. Figure 2 illustrates the effect on supply current per amplifier with RBIAS connected between the SHDN pin and the 12V V + supply of the LT6301 and the approximate design equations. Figure 3 illustrates the same control with RBIAS connected between the SHDNREF pin and ground while the SHDN pin is tied to V +. Either approach is equally effective. 1k TO START-UP CIRCUITRY IBIAS TO AMPLIFIERS BIAS CIRCUITRY SHDNREF 6301 F01 IBIAS = 2 ISHDN = ISHDNREF 5 ISUPPLY PER AMPLIFIER (mA) = 64 • IBIAS Figure 1. Internal Current Biasing Circuitry ISUPPLY PER AMPLIFIER (mA) 30 VS = ±12V V + = 12V 25 RBIAS SHDN 20 IS PER AMPLIFIER (mA) ≈ V + – 1.2V • 25.6 RBIAS + 2k 15 RBIAS = 10 V + – 1.2V • 25.6 – 2k IS PER AMPLIFIER (mA) SHDNREF 5 0 7 10 40 70 100 RBIAS (kΩ) 130 160 190 6301 F02 Figure 2. RBIAS to V+ Current Control sn6301 6301f 7 LT6301 U W U U APPLICATIO S I FOR ATIO 45 VS = ±12V V + = 12V ISUPPLY PER AMPLIFIER (mA) 40 SHDN 35 V + – 1.2V • 64 IS PER AMPLIFIER (mA) ≈ RBIAS + 5k 30 25 RBIAS = 20 V + – 1.2V • 64 – 5k IS PER AMPLIFIER (mA) SHDNREF 15 RBIAS 10 5 0 4 7 10 30 50 70 90 100 130 150 170 190 210 230 250 270 290 RBIAS (kΩ) 6301 F03 Figure 3. RBIAS to Ground Current Control 12V OR VLOGIC Two Control Inputs VC1 H H L L RESISTOR VALUES (kΩ) RSHDN TO VCC (12V) RSHDN TO VLOGIC VLOGIC 3V 3.3V 5V 3V 3.3V 5V RSHDN 40.2 43.2 60.4 4.99 6.81 19.6 RC1 11.5 13.0 21.5 8.66 10.7 20.5 RCO 19.1 22.1 36.5 14.3 17.8 34.0 VC0 SUPPLY CURRENT PER AMPLIFIER (mA) H 10 10 10 10 10 10 L 7 7 7 7 7 7 H 5 5 5 5 5 5 L 2 2 2 2 2 2 VLOGIC VC1 0V VC0 SHDN RC0 2k SHDNREF One Control Input 12V OR VLOGIC RESISTOR VALUES (kΩ) RSHDN TO VCC (12V) RSHDN TO VLOGIC VLOGIC 3V 3.3V 5V 3V 3.3V 5V RSHDN 40.2 43.2 60.4 4.99 6.81 19.6 RC 7.32 8.25 13.7 5.49 6.65 12.7 VC H L RSHDN RC1 VLOGIC 0V VC RC RSHDN SHDN 2k SUPPLY CURRENT PER AMPLIFIER (mA) 10 10 10 10 10 10 2 2 2 2 2 2 6301 F04 SHDNREF Figure 4. Providing Logic Input Control of Operating Current Logic Controlled Operating Current The DSP controller in a typical xDSL application can have I/O pins assigned to provide logic control of the LT6301 line driver operating current. As shown in Figure 4 one or two logic control inputs can control two or four different operating modes. The logic inputs add or subtract current to the SHDN input to set the operating current. The one logic input example selects the supply current to be either full power, 10mA per amplifier or just 2mA per amplifier, which significantly reduces the driver power consumption while maintaining less than 2Ω output impedance to frequencies less than 1MHz. This low power mode retains termination impedance at the amplifier outputs and the line driving back termination resistors. With this termination, while a DSL port is not transmitting data, it can still sense a received signal from the line across the backtermination resistors and respond accordingly. The two logic input control provides two intermediate (approximately 7mA per amplifier and 5mA per amplifier) operating levels between full power and termination modes. sn6301 6301f 8 LT6301 U W U U APPLICATIO S I FOR ATIO These modes can be useful for overall system power management when full power transmissions are not necessary. Contact LTC Applications for single supply design information. Shutdown and Recovery The ultimate power saving action on a completely idle port is to fully shut down the line driver by pulling the SHDN pin to within 0.4V of the SHDNREF potential. As shown in Figure 5 complete shutdown occurs in less than 10µs and, more importantly, complete recovery from the shut down state to full operation occurs in less than 2µs. The biasing circuitry in the LT6301 reacts very quickly to bring the amplifiers back to normal operation. VSHDN SHDNREF = 0V AMPLIFIER OUTPUT Power Dissipation and Heat Management xDSL applications require the line driver to dissipate a significant amount of power and heat compared to other components in the system. The large peak to RMS variations of DMT and CAP ADSL signals require high supply voltages to prevent clipping, and the use of a step-up transformer to couple the signal to the telephone line can require high peak current levels. These requirements result in the driver package having to dissipate significant amounts of power. Several multiport cards inserted into a rack in an enclosed central office box can add up to many, many watts of power dissipation in an elevated ambient temperature environment. The LT6301 has builtin thermal shutdown circuitry that will protect the amplifiers if operated at excessive temperatures, however data transmissions will be seriously impaired. It is important in the design of the PCB and card enclosure to take measures to spread the heat developed in the driver away to the ambient environment to prevent thermal shutdown (which occurs when the junction temperature of the LT6301 exceeds 165°C). Estimating Line Driver Power Dissipation Figure 6 is a typical ADSL application shown for the purpose of estimating the power dissipation in the line driver. Due to the complex nature of the DMT signal, 6301 F05 Figure 5. Shutdown and Recovery Timing 12V 24.9k – SETS IQ PER AMPLIFIER = 10mA 20mA DC 2VRMS SHDN 17.4Ω + +IN A – 1k 1:1.7 • • 110Ω ILOAD = 57mARMS 1000pF 110Ω 3.16VRMS 1k – 17.4Ω 6301 F06 B –IN 100Ω SHDNREF + –12V –2VRMS Figure 6. Estimating Line Driver Power Dissipation sn6301 6301f 9 LT6301 U W U U APPLICATIO S I FOR ATIO which looks very much like noise, it is easiest to use the RMS values of voltages and currents for estimating the driver power dissipation. The voltage and current levels shown for this example are for a full-rate ADSL signal driving 20dBm or 100mWRMS of power on to the 100Ω telephone line and assuming a 0.5dBm insertion loss in the transformer. The quiescent current for the LT6301 is set to 10mA per amplifier. becomes part of the load current. Figure 7 illustrates the total amount of biasing current flowing between the + and – power supplies through the amplifiers as a function of load current for one differential driver. As much as 60% of the quiescent no load operating current is diverted to the load. The power dissipated in the LT6301 is a combination of the quiescent power and the output stage power when driving a signal. The two pairs of amplifiers are configured to place a differential signal on two lines. The Class AB output stage in each amplifier will simultaneously dissipate power in the upper power transistor of one amplifier, while sourcing current, and the lower power transistor of the other amplifier, while sinking current. The total device power dissipation is then: PD = PQUIESCENT + PQ(UPPER) + PQ(LOWER) PD(FULL) = [24V • 8mA + (12V – 2VRMS) • 57mARMS + [|–12V – (– 2VRMS)|] • 57mARMS] • 2 PD = (V+ – V–) • IQ + (V+ – VOUTARMS) • ILOAD + (V – – VOUTBRMS) • ILOAD With no signal being placed on the line and the amplifier biased for 10mA per amplifier supply current, the quiescent driver power dissipation is: PDQ = [24V • 10mA] • 4 = 960mW This can be reduced in many applications by operating with a lower quiescent current value or shutting down the part during idle conditions. When driving a load, a large percentage of the amplifier quiescent current is diverted to the output stage and At full power to both lines the total package power dissipation is: PD(FULL) = [192mW + 570mW + 570mW] • 2 = 2.664W* The junction temperature of the driver must be kept less than the thermal shutdown temperature when processing a signal. The junction temperature is determined from the following expression: TJ = TAMBIENT (°C) + PD(FULL) (W) • θJA (°C/W) θJA is the thermal resistance from the junction of the LT6301 to the ambient air, which can be minimized by heat-spreading PCB metal and airflow through the enclosure as required. For the example given, assuming a maximum ambient temperature of 50°C and keeping the junction temperature of the LT6301 to 150°C maximum, the maximum thermal resistance from junction to ambient required is: θJA(MAX) = 150°C – 50°C = 37.5°C / W 2.664W *Design techniques exist to significantly reduce this value (See Line Driving Back Termination). 25 TOTAL IQ (mA) 20 15 10 5 0 –240 –200 –160 –120 –80 –40 0 40 80 120 ILOAD (mA) (ONE DIFFERENTIAL DRIVER) 160 200 240 6301 F07 Figure 7. IQ vs ILOAD sn6301 6301f 10 LT6301 U W U U APPLICATIO S I FOR ATIO Heat Sinking Using PCB Metal Layout and Passive Components Designing a thermal management system is often a trial and error process as it is never certain how effective it is until it is manufactured and evaluated. As a general rule, the more copper area of a PCB used for spreading heat away from the driver package, the more the operating junction temperature of the driver will be reduced. The limit to this approach however is the need for very compact circuit layout to allow more ports to be implemented on any given size PCB. With a gain bandwidth product of 200MHz the LT6301 requires attention to detail in order to extract maximum performance. Use a ground plane, short lead lengths and a combination of RF-quality supply bypass capacitors (i.e., 0.1µF). As the primary applications have high drive current, use low ESR supply bypass capacitors (1µF to 10µF). To best extract heat from the FE28 package, a generous area of top layer PCB metal should be connected to the four corner pins (Pins 1, 14, 15 and 28). These pins are fused to the leadframe where the LT6301 die are attached. The package also has an exposed metal heat sinking pad on the bottom side which, when soldered to the PCB top layer metal, directly conducts heat away from the IC junction. Soldering the thermal pad to the board produces a thermal resistance from junction to case, θJC, of approximately 3°C/W. Important Note: The metal planes used for heat sinking the LT6301 are electrically connected to the negative supply potential of the driver, typically –12V. These planes must be isolated from any other power planes used in the board design. Fortunately xDSL circuit boards use multiple layers of metal for interconnection of components. Areas of metal beneath the LT6301 connected together through several small 13 mil vias can be effective in conducting heat away from the driver package. The use of inner layer metal can free up top and bottom layer PCB area for external component placement. When PCB cards containing multiple ports are inserted into a rack in an enclosed cabinet, it is often necessary to provide airflow through the cabinet and over the cards. This is also very effective in reducing the junction-toambient thermal resistance of each line driver. To a limit, this thermal resistance can be reduced approximately 5°C/W for every 100lfpm of laminar airflow. The four V + pins (Pins 18, 19, 24, 25) separately provide power to each amplifier and should be shorted together with leads as short as possible to the bypass capacitors. The parallel combination of the feedback resistor and gain setting resistor on the inverting input can combine with the input capacitance to form a pole that can cause frequency peaking. In general, use feedback resistors of 1k or less. Compensation The LT6301 is stable in a gain 10 or higher for any supply and resistive load. It is easily compensated for lower gains with a single resistor or a resistor plus a capacitor. Figure␣ 8 shows that for inverting gains, a resistor from the inverting node to AC ground guarantees stability if the parallel combination of RC and RG is less than or equal to RF/9. For lowest distortion and DC output offset, a series capacitor, CC, can be used to reduce the noise gain at lower frequencies. The break frequency produced by RC and CC should be less than 5MHz to minimize peaking. Figure 9 shows compensation in the noninverting configuration. The RC, CC network acts similarly to the inverting case. The input impedance is not reduced because the network is bootstrapped. This network can also be placed between the inverting input and an AC ground. RF RG VI RC CC (OPTIONAL) VO –RF = RG VI – + VO (RC || RG) ≤ RF/9 1 < 5MHz 2πRCCC 6301 F08 Figure 8. Compensation for Inverting Gains sn6301 6301f 11 LT6301 U W U U APPLICATIO S I FOR ATIO RC VO – CC (OPTIONAL) In differential driver applications, as shown on the first page of this data sheet, it is recommended that the gain setting resistor be comprised of two equal value resistors connected to a good AC ground at high frequencies. This ensures that the feedback factor of each amplifier remains less than 0.1 at any frequency. The midpoint of the resistors can be directly connected to ground, with the resulting DC gain to the VOS of the amplifiers, or just bypassed to ground with a 1000pF or larger capacitor. RF VO =1+ VI RG + VI (RC || RG) ≤ RF/9 1 < 5MHz 2πRCCC RF RG 6301 F09 Figure 9. Compensation for Noninverting Gains Another compensation scheme for noninverting circuits is shown in Figure 10. The circuit is unity gain at low frequency and a gain of 1 + RF/RG at high frequency. The DC output offset is reduced by a factor of ten. The techniques of Figures 9 and 10 can be combined as shown in Figure␣ 11. The gain is unity at low frequencies, 1 + RF/RG at mid-band and for stability, a gain of 10 or greater at high frequencies. + Vi VO – VO = 1 (LOW FREQUENCIES) VI R = 1 + F (HIGH FREQUENCIES) RG RG ≤ RF/9 RF 1 < 5MHz 2πRGCC RG CC 6301 F10 Line Driving Back-Termination The standard method of cable or line back-termination is shown in Figure 12. The cable/line is terminated in its characteristic impedance (50Ω, 75Ω, 100Ω, 135Ω, etc.). A back-termination resistor also equal to the chararacteristic impedance should be used for maximum pulse fidelity of outgoing signals, and to terminate the line for incoming signals in a full-duplex application. There are three main drawbacks to this approach. First, the power dissipated in the load and back-termination resistors is equal so half of the power delivered by the amplifier is wasted in the termination resistor. Second, the signal is halved so the gain of the amplifer must be doubled to have the same overall gain to the load. The increase in gain increases noise and decreases bandwidth (which can also increase distortion). Third, the output swing of the amplifier is doubled which can limit the power it can deliver to the load for a given power supply voltage. An alternate method of back-termination is shown in Figure 13. Positive feedback increases the effective backtermination resistance so RBT can be reduced by a factor Figure 10. Alternate Noninverting Compensation + VI RC VO – CC RF RG CBIG VI RBT VO – VO = 1 AT LOW FREQUENCIES VI RF AT HIGH FREQUENCIES (RC || RG) RL RF R = 1 + F AT MEDIUM FREQUENCIES RG =1+ CABLE OR LINE WITH CHARACTERISTIC IMPEDANCE RL + RBT = RL RG 6301 F12 VO 1 = (1 + RF/RG) VI 2 6301 F11 Figure 11. Combination Compensation Figure 12. Standard Cable/Line Back Termination sn6301 6301f 12 LT6301 U W U U APPLICATIO S I FOR ATIO RP2 + VI RP1 VI VA RBT + VO VA RBT VP VO RL RF n= RG 6301 F13 RP ( )( RG ) – ( ) 1+ RF RG RP1 – RP2 + RP1 –VI Figure 13. Back Termination Using Postive Feedback VA = VO (1 – 1/n) to increase the effective value of RBT by n. VP = VO (1 – 1/n)/(1 + RF/RG) Eliminating VP, we get the following: –VA –VO 6301 F14 and assuming RP >> RL, we require VA = VO (1 – 1/n) solving RF/RP = 1 – 1/n VO/VI = (1 + RF/RG + RF/RP)/[2(1 – RF/RP)] (1 + RP2/RP1) = (1 + RF/RG)/(1 – 1/n) For example, reducing RBT by a factor of n = 4, and with an amplifer gain of (1 + RF/RG) = 10 requires that RP2/RP1 =␣ 12.3. Note that the overall gain is increased: RP2 / (RP2 + RP1) VO = VI (1+ 1/n) / (1+ RF /RG ) − RP1/(RP2 + RP1) ] A simpler method of using positive feedback to reduce the back-termination is shown in Figure 14. In this case, the drivers are driven differentially and provide complementary outputs. Grounding the inputs, we see there is inverting gain of –RF/RP from –VO to VA VA = VO (RF/RP) + So to reduce the back-termination by a factor of 3 choose RF/RP = 2/3. Note that the overall gain is increased to: VO = VP (1 + RP2/RP1) ] [ RF RP Figure 14. Back Termination Using Differential Postive Feedback of n. To analyze this circuit, first ground the input. As RBT␣ = RL/n, and assuming RP2>>RL we require that: [ ( ) RBT RP2/(RP2 + RP1) 1 + 1/n R R 1+ F + F RG RP 2 1– 1 RP1 R =1– 1+ F n RG RP1 + RP2 VO = VI VO = VI RL RF 1 RF RP 1– RL RP RL FOR RBT = n RL n FOR RBT = RF – RG – Using positive feedback is often referred to as active termination. Figure 16 shows a full-rate ADSL line driver incorporating positive feedback to reduce the power lost in the back termination resistors by 40% yet still maintains the proper impedance match to the100Ω characteristic line impedance. This circuit also reduces the transformer turns ratio over the standard line driving approach resulting in lower peak current requirements. With lower current and less power loss in the back termination resistors, this driver dissipates only 1W of power, a 30% reduction. While the power savings of positive feedback are attractive there is one important system consideration to be addressed, received signal sensitivity. The signal received sn6301 6301f 13 LT6301 U W U U APPLICATIO S I FOR ATIO from the line is sensed across the back termination resistors. With positive feedback, signals are present on both ends of the RBT resistors, reducing the sensed amplitude. Extra gain may be required in the receive channel to compensate, or a completely separate receive path may be implemented through a separate line coupling transformer. Using DC blocking capacitors, as shown in Figure 15, to AC couple the signal to the transformer eliminates the possibility for DC current to flow under any conditions. These capacitors should be sized large enough to not impair the frequency response characteristics required for the data transmission. Considerations for Fault Protection Another important fault related concern has to do with very fast high voltage transients appearing on the telephone line (lightning strikes for example). TransZorbs®, varistors and other transient protection devices are often used to absorb the transient energy, but in doing so also create fast voltage transitions themselves that can be coupled through the transformer to the outputs of the line driver. Several hundred volt transient signals can appear at the primary windings of the transformer with current into the driver outputs limited only by the back termination resistors. While the LT6301 has clamps to the supply rails at the output pins, they may not be large enough to handle the significant transient energy. External clamping diodes, such as BAV99s, at each end of the transformer primary help to shunt this destructive transient energy away from the amplifier outputs. The basic line driver design, shown on the front page of this data sheet, presents a direct DC path between the outputs of the two amplifiers. An imbalance in the DC biasing potentials at the noninverting inputs through either a fault condition or during turn-on of the system can create a DC voltage differential between the two amplifier outputs. This condition can force a considerable amount of current to flow as it is limited only by the small valued back-termination resistors and the DC resistance of the transformer primary. This high current can possibly cause the power supply voltage source to drop significantly impacting overall system performance. If left unchecked, the high DC current can heat the LT6301 to thermal shutdown. TransZorb is a registered trademark of General Instruments, GSI 12V 12V –12V 24.9k + +IN BAV99 0.1µF 1/4 LT6301 SHDN 12.7Ω – 1k 1:2 • • 110Ω LINE LOAD 1000pF 110Ω 1k – 0.1µF 1/4 LT6301 –IN + –12V 12.7Ω SHDNREF BAV99 12V –12V 6301 F15 Figure 15. Protecting the Driver Against Load Faults and Line Transients sn6301 6301f 14 LT6301 W W SI PLIFIED SCHE ATIC (one amplifier shown) V+ Q9 Q10 Q13 Q17 Q3 C1 R1 Q1 –IN Q7 Q6 Q2 Q5 Q14 +IN C2 OUT Q15 Q8 Q4 Q18 Q16 Q12 Q11 V– 6301 SS U PACKAGE DESCRIPTIO FE Package 28-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663) Exposed Pad Variation EA 9.60 – 9.80* (.378 – .386) 7.56 (.298) 7.56 (.298) 28 2726 25 24 23 22 21 20 19 18 1716 15 6.60 ±0.10 3.05 (.120) 4.50 ±0.10 SEE NOTE 4 0.45 ±0.05 EXPOSED PAD HEAT SINK ON BOTTOM OF PACKAGE 3.05 6.40 (.120) BSC 1.05 ±0.10 0.65 BSC RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1.20 (.047) MAX 4.30 – 4.50* (.169 – .177) 0° – 8° 0.45 – 0.75 (.018 – .030) 0.09 – 0.20 (.0036 – .0079) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE 0.65 (.0256) BSC 0.195 – 0.30 (.0077 – .0118) 0.05 – 0.15 (.002 – .006) FE28 (EA) TSSOP 0203 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE sn6301 6301f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LT6301 U TYPICAL APPLICATIO 12V 24.9k + +IN SHDN 1/4 LT6301 13.7Ω – 1k 1:1.2* 1.65k • • 182Ω 100Ω LINE 1.65k 1000pF 182Ω 1k – 1/4 LT6301 + –IN 13.7Ω *COILCRAFT X8502-A OR EQUIVALENT 1W DRIVER POWER DISSIPATION 1.15W POWER CONSUMPTION SHDNREF 6301 F16 –12V Figure 16. ADSL Line Driver Using Active Termination RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1361 Dual 50MHz, 800V/µs Op Amp ±15V Operation, 1mV VOS, 1µA IB LT1739 Dual 500mA, 200MHz xDSL Line Driver Low Cost ADSL CO Driver, Low Power LT1794 Dual 500mA, 200MHz xDSL Line Driver ADSL CO Driver, Extended Output Swing, Low Power LT1795 Dual 500mA, 50MHz Current Feedback Amplifier Shutdown/Current Set Function, ADSL CO Driver LT1813 Dual 100MHz, 750V/µs, 8nV/√Hz Op Amp Low Noise, Low Power Differential Receiver, 4mA/Amplifier LT1886 Dual 200mA, 700MHz Op Amp 12V Operation, 7mA/Amplifier, ADSL CPE Modem Line Driver LT1969 Dual 200mA, 700MHz Op Amp with Power Control 12V Operation, MSOP Package, ADSL CPE Modem Line Driver LT6300 Dual 500mA, 200MHz, xDSL Line Driver ADSL CO Driver in SSOP Package sn6301 6301f 16 Linear Technology Corporation LT/TP 0303 2K • PRINTED IN THE USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2001 This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components.