Final Electrical Specifications
LTC3722-1/LTC3722-2
Synchronous Dual Mode
Phase Modulated
Full Bridge Controllers
U
DESCRIPTIO
FEATURES
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■
■
■
■
■
■
■
■
■
■
■
Adaptive or Manual Delay Control for Zero Voltage
Switching Operation
Adjustable Synchronous Rectification Timing for
Highest Efficiency
Adjustable Maximum ZVS Delay
Adjustable System Undervoltage Lockout and
Hysteresis
Programmable Leading Edge Blanking
Very Low Start-Up and Quiescent Currents
Current Mode (LTC3722-1) or Voltage Mode
(LTC3722-2) Operation
Programmable Slope Compensation
VCC UVLO and 25mA Shunt Regulator
50mA Output Drivers
Soft-Start, Cycle-by-Cycle Current Limiting and
Hiccup Mode Short-Circuit Protection
5V, 15mA Low Dropout Regulator
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APPLICATIO S
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Telecommunications, Infrastructure Power Systems
Distributed Power Architectures
Server Power Supplies
The LTC®3722-1/LTC3722-2 phase shift PWM controllers
provide all of the control and protection functions necessary to implement a high efficiency, zero voltage switched
(ZVS), full bridge power converter. Adaptive ZVS circuitry
delays the turn-on signals for each MOSFET independent
of internal and external component tolerances. Manual
delay set mode enables secondary side control operation
or direct control of switch turn-on delays.
The LTC3722-1/LTC3722-2 feature adjustable synchronous rectifier timing for optimal efficiency. A UVLO program input provides accurate system turn-on and turn-off
voltages. The LTC3722-1 features peak current mode
control with programmable slope compensation and leading edge blanking, while the LTC3722-2 employs voltage
mode control with voltage feedforward capability.
The LTC3722-1/LTC3722-2 feature extremely low operating and start-up currents. Both devices include a full range
of protection features and are available in the 24-pin
surface mount (GN) package.
, LTC and LT are registered trademarks of Linear Technology Corporation.
U
■
February 2003
TYPICAL APPLICATIO
VIN
36V TO 72V
CIN
12VOUT, 240W Converter Efficiency
R1
95
MA
36VIN
MC
T1
L1
L2
MB
90
VOUT
12V
COUT
MD
1/2
U1
1/2
U1
U2
EFFICIENCY (%)
LTC3722
48VIN
72VIN
85
80
ME
RCS
T2
75
C1
0
MF
U1, U2: LTC1693-1 DUAL GATE DRIVER
2
4
3722 • TA01A
6
8 10 12 14 16 18 20
CURRENT (A)
3722 TA01b
372212i
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
1
LTC3722-1/LTC3722-2
U
W W
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ABSOLUTE
AXI U RATI GS
(Note 1)
VCC to GND (Low Impedance Source) ......... –0.3 to 10V
(Chip Self Regulates at 10.3V)
UVLO to GND ................................................ –0.3 to VCC
All Other Pins to GND
(Low Impedance Source) ....................... –0.3 to 5.5V
VCC (Current Fed) ................................................. 25mA
VREF Output Current ................................ Self Regulated
Outputs (A,B,C,D,E,F) Current .......................... ±100mA
Operating Temperature Range (Note 6)
LTC3722E ........................................... – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
U
W
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
SYNC
1
24 CT
DPRG
2
23 GND
CS
3
22 PGND
COMP
4
RLEB
5
FB
6
SS
ORDER PART
NUMBER
TOP VIEW
SYNC
1
24 CT
RAMP
2
23 GND
CS
3
22 PGND
21 OUTA
COMP
4
21 OUTA
20 OUTB
DPRG
5
20 OUTB
19 OUTC
FB
6
19 OUTC
7
18 VCC
SS
7
18 VCC
NC
8
17 OUTD
NC
8
17 OUTD
PDLY
9
16 OUTE
PDLY
9
16 OUTE
SBUS 10
15 OUTF
SBUS 10
15 OUTF
ADLY 11
14 VREF
ADLY 11
14 VREF
UVLO 12
13 SPRG
UVLO 12
13 SPRG
LTC3722EGN-1
GN PACKAGE
24-LEAD NARROW PLASTIC SSOP
TJMAX = 125°C, θJA = 100°C/W
ORDER PART
NUMBER
LTC3722EGN-2
GN PACKAGE
24-LEAD NARROW PLASTIC SSOP
TJMAX = 125°C, θJA = 100°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
372212i
2
LTC3722-1/LTC3722-2
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 9.5V, CT = 270pF, RDPRG = 60.4k, RSPRG = 100k, TA = t MIN to t MAX,
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCCUV
VCC Under Voltage Lockout
Measured on VCC
10.25
10.5
V
VCCHY
VCC UVLO Hysteresis
Measured on VCC
ICCST
Start-Up Current
VCC = VUVLO – 0.3V
ICCRN
Operating Current
No Load on Outputs
VSHUNT
Shunt Regulator Voltage
Current into VCC = 10mA
RSHUNT
Shunt Resistance
Current into VCC = 10mA to 17mA
SUVLO
System UVLO Threshold
Measured on UVLO Pin, 7mA into VCC
4.8
SHYST
System UVLO Hysteresis Current
Current Flows Out of UVLO Pin, 7mA into VCC
8.5
DTHR
Delay Pin Threshold
ADLY and PDLY
SBUS = 1.5V
SBUS = 2.25V
1.4
2.1
DHYS
Delay Hysteresis Current
ADLY and PDLY
SBUS = 1.5V, ADLY/PDLY = 1.7V
1.3
mA
DTMO
Delay Timeout
RDPRG = 60.4K
100
ns
DFXT
Fixed Delay Threshold
Measured on SBUS
4
V
DFTM
Fixed Delay Time
ADLY,PDLY = 1V, SBUS = VREF
70
ns
IRMP
Ramp Discharge Current
RAMP = 1V, COMP = 0V, CT = 4V,
LTC3722-1 Only
50
mA
ISLP
Slope Compensation Current
Measured on CS, CT = 1V
CT = 2.25V
30
68
µA
µA
DCMAX
Maximum Phase Shift
COMP = 4.5V
●
DCMIN
Minimum Phase Shift
COMP = 0V
●
Input Supply
3.8
●
4.2
V
145
230
µA
5
8
mA
10.3
10.8
V
1.1
3.5
Ω
5.0
5.2
V
10
11.5
µA
1.5
2.25
1.6
2.4
V
V
Delay Blocks
●
●
Phase Modulator
95
98.5
0
%
0.5
%
Oscillator
OSCI
Initial Accuracy
TA = 25°C, CT = 270pF
OSCT
Total Variation
VCC = 6.5V to 9.5V
OSCV
CT Ramp Amplitude
Measured on CT
●
225
250
275
kHz
215
250
285
kHz
2.2
1.6
1.9
V
OSYT
SYNC Threshold
Measured on SYNC
OSYW
Minimum SYNC Pulse Width
Measured at Outputs (Note 2)
100
2.2
ns
V
OSYR
SYNC Frequency Range
Measured at Outputs (Note 2)
1000
kHz
372212i
3
LTC3722-1/LTC3722-2
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 9.5V, TA = t MIN to t MAX, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
FB Input Voltage
COMP = 2.5V (Note 4)
1.172
1.204
1.236
V
Error Amplifier
VFB
FBI
FB Input Range
Measured on FB (Note 5)
–0.3
AVOL
Open-Loop Gain
COMP = 1V to 3V (Note 4)
70
2.5
IIB
Input Bias Current
COMP = 2.5V (Note 4)
VOH
Output High
Load on COMP = –100µA
VOL
Output Low
Load on COMP = 100µA
ISOURCE
Output Source Current
COMP = 2.5V
400
800
µA
ISINK
Output Sink Current
COMP = 2.5V
2
5
mA
VREF
Initial Accuracy
TA = 25°C, Measured on VREF
4.925
5.00
REFLD
Load Regulation
Load on VREF = 100µA to 5mA
REFLN
Line Regulation
VCC = 6.5V to 9.5V
REFTV
Total Variation
Line, Load
REFSC
Short-Circuit Current
OUTH(x)
Output High Voltage
OUTL(x)
Output Low Voltage
IOUT(x) = 50mA
0.6
1
V
RHI(x)
Pull-Up Resistance
IOUT(x) = –50mA to –10mA
22
30
Ω
RLO(x)
Pull-Down Resistance
IOUT(x) = –50mA to –10mA
12
20
Ω
t r(x)
Rise Time
COUT(x) = 50pF
5
15
ns
t f(x)
Fall Time
COUT(x) = 50pF
5
15
ns
SDEL
SYNC Driver Turn-0ff Delay
RSPRG = 100k
180
5
4.7
V
90
dB
20
nA
0.4
V
4.92
0.18
V
Reference
5.075
V
2
15
mV
0.9
10
mV
4.900
5.000
5.100
VREF Shorted to GND
18
30
45
IOUT(x) = –50mA
7.9
8.4
●
V
mA
Outputs
V
ns
Current Limit and Shutdown
CLPP
Pulse by Pulse Current Limit Threshold
Measured on CS
240
270
300
CLSD
Shutdown Current Limit Threshold
Measured on CS
0.55
0.65
0.73
CLDEL
Current Limit Delay to Output
100mV Overdrive on CS (Notes 3, 7)
SSI
Soft-Start Current
SS = 2.5V
SSR
Soft-Start Reset Threshold
Measured on SS
0.7
0.4
0.1
V
FLT
Fault Reset Threshold
Measured on SS
4.5
3.9
3.5
V
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Sync amplitude = 5VP-P, pulse width = 50ns. Verify output (A-F)
frequency = 1/2 sync frequency.
Note 3: Includes leading edge blanking delay, RLEB = 20k.
Note 4: FB is driven by a servo-loop amplifier to control VCOMP for these
tests.
mV
V
80
7
12
ns
µA
17
Note 5: Set FB to –0.3V, 2.5V and insure that COMP does not phase
invert.
Note 6: The LTC3722E-1/LTC3722E-2 are guaranteed to meet
performance specifications from 0°C to 85°C. Specifications over the
–40°C to 85°C operating temperature range are assured by design,
characterization and correlation with statistical process controls.
Note 7: Guaranteed by design, not tested in production.
372212i
4
LTC3722-1/LTC3722-2
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Start-Up ICC vs VCC
200
10.50
TA = 25°C
CT = 270pF
100
50
250
FREQUENCY (kHz)
VCC (V)
10.25
10.00
9.75
2
6
4
8
10
9.50
10
0
30
20
ISHUNT (mA)
40
220
– 60 – 40 – 20 0
20 40 60
TEMPERATURE (°C)
50
3722 • G01
3722 • G02
Leading Edge Blanking Time
vs RLEB
350
240
230
VCC (V)
80
100
3722 • G03
VREF vs IREF
5.05
TA = 25°C
300
TJ = 25°C
5.00
250
TJ = 85°C
200
VREF (V)
BLANK TIME (ns)
150
4.95
4.90
TJ = –40°C
100
4.85
50
0
4.80
0 10 20 30 40 50 60
RLEB (kΩ)
0
70 80 90 100
5
10
15 20
25
IREF (mA)
30
VREF vs Temperature
Error Amplifier Gain/Phase
GAIN (dB)
5.01
5.00
4.99
4.98
4.97
– 60 – 40 – 20 0
20 40 60
TEMPERATURE (°C)
40
35
3722 • G05
3722 • G04
PHASE (DEG)
0
VREF (V)
ICC (µA)
260
TA = 25°C
150
0
Oscillator Frequency vs
Temperature
VCC vs ISHUNT
80
100
3722 • G06
TA = 25°C
100
80
60
40
20
0
–180
–270
–360
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
3722 • G07
372212i
5
LTC3722-1/LTC3722-2
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Delay Hysteresis Current vs
Temperature
Start-Up ICC vs Temperature
150
1.276
140
ICC (µA)
130
120
110
100
90
80
Slope Current vs Temperature
90
SBUS = 1.5V
80
1.274
70
1.270
1.268
1.266
1.264
1.262
–25
5
35
65
TEMPERATURE (°C)
95
50
40
CT = 1V
30
10
1.256
–55
125
60
20
1.260
1.258
70
–55
CT = 2.25V
1.272
CURRENT (µA)
HYSTERESIS CURRENT (mA)
160
1.278
–25
5
35
65
TEMPERATURE (°C)
95
0
–55
125
–25
5
35
65
TEMPERATURE (°C)
VCC Shunt Voltage vs
Temperature
Delay Pin Threshold vs
Temperature
10.5
FB Input Voltage vs Temperature
2.4
ICC = 10mA
2.3
10.4
125
3722 • G10
3722 • G09
3722 • G08
95
1.202
SBUS = 2.25V
1.201
10.2
10.1
1.200
2.1
FB VOLTAGE (V)
10.3
THRESHOLD (V)
SHUNT VOLTAGE (V)
2.2
2.0
1.9
1.8
1.198
1.197
1.7
10.0
1.196
1.6
9.9
9.8
–55
1.199
SBUS = 1.5V
1.5
–25
5
35
65
TEMPERATURE (°C)
95
125
1.4
–55
–25
5
35
65
TEMPERATURE (°C)
3722 • G11
95
1.195
125
3722 • G12
1.194
–55
–25
5
35
65
TEMPERATURE (°C)
95
125
3722 • G13
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U
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PI FU CTIO S (LTC3722-1/LTC3722-2)
SYNC (Pin 1/Pin 1): Synchronization Input/Output for the
Oscillator. The input threshold for SYNC is approximately
1.5V, making it compatible with both CMOS and TTL logic.
Terminate SYNC with a 5.1k resistor to GND.
DPRG (Pin 2/Pin 5): Programming Input for Default Zero
Voltage Transition (ZVS) Delay. Connect a resistor from
DPRG to VREF to set the maximum turn on delay for
outputs A, B, C, D. The delay is approximately equal to
(1.66e-12 x RDPRG). The nominal voltage on DPRG is 2V.
RAMP (NA/Pin 2): Input to Phase Modulator Comparator
for LTC3722-2 only. The voltage on RAMP is internally
level shifted by 650mV.
CS (Pin 3/Pin 3): Input to phase modulator for the
LTC3722-1. Input to Pulse by Pulse and Overload Current
Limit Comparators, Output of Slope Compensation Circuitry. The pulse by pulse comparator has a nominal
300mV threshold, while the overload comparator has a
nominal 600mV threshold.
COMP (Pin 4/Pin 4): Error Amplifier Output, Inverting
Input to Phase Modulator.
RLEB (Pin 5/NA): Timing Resistor for Leading Edge Blanking. Use a 10k to 100k resistor to program from 40ns to
310ns of leading edge blanking of the current sense signal
on CS for the LTC3722-1. A ±1% tolerance resistor is
372212i
6
LTC3722-1/LTC3722-2
U
U
U
PI FU CTIO S (LTC3722-1/LTC3722-2)
recommended. The LTC3722-2 has a fixed blanking time
of approximately 80ns.
nous rectifier driver outputs (OUTE and OUTF). The nominal voltage on SPRG is 2V.
FB (Pin 6/Pin 6): Error Amplifier Inverting Input. This is the
voltage feedback input for the LTC3722. The nominal
regulation voltage at FB is 1.204V.
VREF (Pin 14/Pin 14): Output of the 5V Reference. VREF is
capable of supplying up to 19mA to external circuitry. VREF
should be decoupled to GND with a 1µF ceramic capacitor.
SS (Pin 7/Pin 7): Soft-Start/Restart Delay Circuitry Timing
Capacitor. A capacitor from SS to GND provides a controlled ramp of the current command (LTC3722-1), or
duty cycle (LTC3722-2). During overload conditions SS is
discharged to ground initiating a soft-start cycle.
OUTF (Pin 15/Pin 15): 50mA Driver for Synchronous
Rectifier Associated with OUTB and OUTC.
NC (Pin 8/Pin 8): No Connection. Tie this pin to GND.
PDLY (Pin 9/Pin 9): Passive Leg Delay Circuit Input. PDLY
is connected through a voltage divider to the left leg of the
bridge in adaptive ZVS mode. In fixed ZVS mode, a voltage
between 0V and 2.5V on PDLY, programs a fixed ZVS
delay time for the passive leg transition.
SBUS (Pin 10/Pin 10): Line Voltage Sense Input. SBUS is
connected to the main DC voltage feed by a resistive
voltage divider when using adaptive ZVS control. The
voltage divider is designed to produce 1.5V on SBUS at
nominal VIN. If SBUS is tied to VREF, the LTC3722-1/
LTC3722-2 is configured for fixed mode ZVS control.
ADLY (Pin 11/Pin 11): Active Leg Delay Circuit Input.
ADLY is connected through a voltage divider to the right
leg of the bridge in adaptive ZVS mode. In fixed ZVS mode,
a voltage between 0V and 2.5V on ADLY, programs a fixed
ZVS delay time for the active leg transition.
UVLO (Pin 12/Pin 12): Input to Program System Turn-On
and Turn-Off Voltages. The nominal threshold of the UVLO
comparator is 5V. UVLO is connected to the main DC
system feed through a resistor divider. When the UVLO
threshold is exceeded, the LTC3722-1/LTC3722-2 commences a soft start cycle and a 10µA (nominal) current is
fed out of UVLO to program the desired amount of system
hysteresis. The hysteresis level can be adjusted by changing the resistance of the divider.
SPRG (Pin 13/Pin 13): A Resistor is connected between
SPRG and GND to set the turn-off delay for the synchro-
OUTE (Pin 16/Pin 16): 50mA Driver for Synchronous
Rectifier Associated with OUTA and OUTD.
OUTD (Pin 17/Pin 17): 50mA driver for Low Side of the Full
Bridge Active Leg.
VCC (Pin 18/Pin 18): Supply Voltage Input to the
LTC3722-1/LTC3722-2 and 10.25V Shunt Regulator. The
chip is enabled after VCC has risen high enough to allow the
VCC shunt regulator to conduct current and the UVLO
comparator threshold is exceeded. Once the VCC shunt
regulator has turned on, VCC can drop to as low as 6V and
maintain operation.
OUTC (Pin 19/Pin 19): 50mA Driver for High Side of the
Full Bridge Active Leg.
OUTB (Pin 20/Pin 20): 50mA Driver for Low Side of the
Full Bridge Passive Leg.
OUTA (Pin 21/Pin 21): 50mA Driver for High Side of the
Full Bridge Passive Leg.
PGND (Pin 22/Pin 22): Power Ground for the LTC3722.
The output drivers of the LTC3722 are referenced to
PGND. Connect the ceramic VCC bypass capacitor directly
to PGND.
GND (Pin 23/Pin 23): All circuits other than the output
drivers in the LTC3722 are referenced to GND. Use of a
ground plane is recommended but not absolutely necessary.
CT (Pin 24/Pin 24): Timing Capacitor for the Oscillator.
Use a ±5% or better low ESR ceramic capacitor for best
results.
372212i
7
LTC3722-1/LTC3722-2
W
BLOCK DIAGRA S
LTC3722-1 Current Mode SYNC Phase Shift PWM
VCC
UVLO
VREF
CT
SYNC
SPRG
DPRG
SBUS
18
12
14
24
1
13
2
10
VCC UVLO
10.25V = ON
6V = OFF
FB
6
1.2V
PDLY
9
5V
REF AND LDO
1.2V
REF GOOD
–
+
OSC
OUTA
21
SYSTEM
UVLO
Q
1 = ENABLE
0 = DISABLE
+
–
5V
ERROR
AMPLIFIER
COMP
4
R1
50k
T
QB
–
+
SYNC
RECTIFIER
DRIVE
LOGIC
PHASE
MODULATOR
R2
14.9k
–
M1
VREF
QB
R
Q
S
R QB
S
7
+
650mV
–
SHUTDOWN
CURRENT
LIMIT
ACTIVE
DELAY
OUTD
17
ADLY
FAULT
LOGIC
11
PGND
22
M2
BLANK
+
270mV
–
5
RLEB
OUTF
15
SLOPE
COMPENSATION
CT/R
CS
3
OUTE
16
OUTC
19
12µA
SS
OUTB
20
VCC
GOOD
+
650mV
PASSIVE
DELAY
PULSE BY PULSE
CURRENT LIMIT
23
GND
3722 • BD01
372212i
8
LTC3722-1/LTC3722-2
W
BLOCK DIAGRA S
LTC3722-2 Voltage Mode SYNC Phase Shift PWM
VCC
UVLO
VREF
CT
SYNC
SPRG
DPRG
SBUS
18
12
14
24
1
13
5
10
VCC UVLO
10.25V = ON
6V = OFF
FB
6
1.2V
ERROR
AMPLIFIER
–
+
+
OUTA
21
SYSTEM
UVLO
–
R1
50k
Q
T
OUTB
20
QB
VCC
GOOD
–
PHASE
MODULATOR
650mV
VREF
QB
R
Q
S
OUTE
16
SYNC
RECTIFIER
DRIVE
LOGIC
+
R
12µA
SS
PASSIVE
DELAY
–
+
2
OSC
1 = ENABLE
0 = DISABLE
5V
COMP
4
RAMP
PDLY
9
5V
REF AND LDO
1.2V
REF GOOD
S
OUTF
15
OUTC
19
QB
ACTIVE
DELAY
OUTD
17
7
+
650mV
–
SHUTDOWN
CURRENT
LIMIT
ADLY
FAULT
LOGIC
11
M2
3722 • BD02
PGND
22
CS
3
BLANK
+
270mV
–
23
PULSE BY PULSE
CURRENT LIMIT
GND
372212i
9
LTC3722-1/LTC3722-2
WU
W
TI I G DIAGRA
PASSIVE LEG
DELAY
ACTIVE LEG
DELAY
OUTA
OUTB
OUTC
OUTD
COMP
RAMP
COMP
COMP
OUTE
SYNC TURN OFF
DELAY (PROGRAMMABLE)
OUTF
SYNC TURN OFF
DELAY (PROGRAMMABLE)
NOTE: SHADED AREAS CORRESPOND TO POWER DELIVERY PULSES.
3722 TD
U
OPERATIO
Phase Shift Full-Bridge PWM
Conventional full-bridge switching power supply topologies are often employed for high power, isolated DC/DC
and off-line converters. Although they require two additional switching elements, substantially greater power and
higher efficiency can be attained for a given transformer
size compared to the more common single-ended forward
and flyback converters. These improvements are realized
since the full-bridge converter delivers power during both
parts of the switching cycle, reducing transformer core
loss and lowering voltage and current stresses. The fullbridge converter also provides inherent automatic transformer flux reset and balancing due to its bidirectional
drive configuration. As a result, the maximum duty cycle
range is extended, further improving efficiency. Soft switching variations on the full-bridge topology have been proposed to improve and extend its performance and application. These zero voltage switching (ZVS) techniques ex-
ploit the generally undesirable parasitic elements present
within the power stage. The parasitic elements are utilized
to drive near lossless switching transitions for all of the
external power MOSFETs.
LTC3722-1/LTC3722-2 phase shift PWM controllers provide enhanced performance and simplify the design task
required for a ZVS phase shifted full-bridge converter. The
primary attributes of the LTC3722-1/LTC3722-2 as compared to currently available solutions include:
1) Truly adaptive and accurate (DirectSense technology)
ZVS with programmable timeout.
Benefit: higher efficiency, higher duty cycle capability,
eliminates external trim.
2) Fixed ZVS capability.
Benefit: enables secondary side control and simplifies
external circuit.
372212i
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LTC3722-1/LTC3722-2
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OPERATIO
3) Internally generated drive signals with programmable
turn-off for current doubler synchronous rectifiers.
Benefit: eliminates external glue logic, drivers, optimal
timing for highest efficiency.
4) Programmable (single resistor) leading edge blanking.
Benefit: prevents spurious operation, reduces external
filtering required on CS.
5) Programmable (single resistor) slope compensation.
Benefit: eliminates external glue circuitry.
6) Optimized current mode control architecture.
Benefit: eliminates glue circuitry, less overshoot at startup, faster recovery from system faults.
7) Programmable system undervoltage lockout and hysteresis.
Benefit: provides an accurate turn-on voltage for power
supply and reduces external circuitry.
As a result, the LTC3722-1/LTC3722-2 makes the ZVS
topology feasible for a wider variety of applications, including those at lower power levels.
The LTC3722-1/LTC3722-2 control four external power
switches in a full-bridge arrangement. The load on the
bridge is the primary winding of a power transformer. The
diagonal switches in the bridge connect the primary winding between the input voltage and ground every oscillator
cycle. The pair of switches that conduct are alternated by
an internal flip-flop in the LTC3722-1/LTC3722-2. Thus,
the voltage applied to the primary is reversed in polarity on
every switching cycle and each output drive signal is 1/2
the frequency of the oscillator. The on-time of each driver
signal is slightly less that 50%. The on-time overlap of the
diagonal switch pairs is controlled by the LTC3722-1/
LTC3722-2 phase modulation circuitry. (Refer to Block
and Timing Diagrams) This overlap sets the approximate
duty cycle of the converter. The LTC3722-1/LTC3722-2
driver output signals (OUTA to OUTF) are optimized for
interface with an external gate driver IC or buffer. External
power MOSFETs A and C require high side driver circuitry,
while B and D are ground referenced and E and F are
ground referenced but on the secondary side of the
isolation barrier. Methods for providing drive to these
elements are detailed in this data sheet. The secondary
voltage of the transformer is the primary voltage divided
by the transformer turns ratio. Similar to a buck converter,
the secondary square wave is applied to an output filter
inductor and capacitor to produce a well regulated DC
output voltage.
Switching Transitions
The phase shifted full-bridge can be described by four
primary operating states. The key to understanding how
ZVS occurs is revealed by examining the states in detail.
Each full cycle of the transformer has two distinct periods
in which power is delivered to the output, and two “freewheeling” periods. The two sides of the external bridge
have fundamentally different operating characteristics that
become important when designing for ZVS over a wide
load current range. The left bridge leg is referred to as the
“passive” leg, while the right leg is referred to as the
“active” leg. The following descriptions provide insight as
to why these differences exist.
State 1 (Power Pulse 1)
Referring to Figure 1, State 1 begins with MA, MD and MF
“ON” and MB, MC and ME “OFF.” During the simultaneous
conduction of MA and MD, the full input voltage is applied
across the transformer primary winding and following the
dot convention, VIN/N is applied to the left side of LO1
allowing current to increase in LO1. The primary current
during this period is approximately equal to the output
inductor current (LO1) divided by the transformer turns
ratio plus the transformer magnetizing current (VIN • tON/
LMAG). MD turns off and ME turns on at the end of State 1.
State 2 (Active Transition and Freewheel Interval)
MD turns off when the phase modulator comparator
transitions. At this instant, the voltage on the MD/MC
junction begins to rise towards the applied input voltage
(VIN). The transformer’s magnetizing current and the
reflected output inductor current propels this action. The
slew rate is limited by MOSFET MC and MD’s output
capacitance (COSS), snubbing capacitance and the transformer interwinding capacitance. The voltage transition
372212i
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LTC3722-1/LTC3722-2
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OPERATIO
on the active leg from the ground reference point to VIN will
always occur, independent of load current as long as
energy in the transformer’s magnetizing and leakage inductance is greater than the capacitive energy. That is,
1/2 • (LM + LI) • IM2 > 1/2 • 2 • COSS • VIN2 — the worst case
occurs when the load current is zero. This condition is
usually easy to meet. The magnetizing current is virtually
constant during this transition because the magnetizing
inductance has positive voltage applied across it throughout the low to high transition. Since the leg is actively
driven by this “current source,” it is called the active or
linear transition. When the voltage on the active leg has
risen to VIN, MOSFET MC is switched on by the ZVS
circuitry. The primary current␣ now flows through the two
high side MOSFETs (MA and MC). The transformer’s
secondary windings are electrically shorted at this time
since both ME and MF are “ON”. As long as positive
current flows in LO1 and LO2, the transformer primary
(magnetizing) inductance is also shorted through normal
transformer action. MA and MF turn off at the end of
State 2.
resonantly transferred to the capacitive elements, hence,
the term passive or resonant transition. Assuming there is
sufficient inductive energy to propel the bridge leg to
GND, the time required will be approximately equal to
π • √LC/2. When the voltage on the passive leg nears GND,
MOSFET MB is commanded “ON” by the ZVS circuitry.
Current continues to increase in the leakage and external
series inductance which is opposite in polarity to the
reflected output inductor current. When this current is
equal in magnitude to the reflected output current, the
primary current reverses direction, the opposite secondary winding becomes forward biased and a new power
pulse is initiated. The time required for the current reversal
reduces the effective maximum duty cycle and must be
considered when computing the power transformer turns
ratio. If ZVS is required over the entire range of loads, a
small commutating inductor is added in series with the
primary to aid with the passive leg transition, since the
leakage inductance alone is usually not sufficient and
predictable enough to guarantee ZVS over the full load
range.
State 3 (Passive Transition)
State 4 (Power Pulse 2)
MA turns off when the oscillator timing period ends, i.e.,
the clock pulse toggles the internal flip-flop. At the instant
MA turns off, the voltage on the MA/MB junction begins to
decay towards the lower supply (GND). The energy available to drive this transition is limited to the primary leakage
inductance and added commutating inductance which
have (IMAG + IOUT/2N) flowing through them initially. The
magnetizing and output inductors don’t contribute any
energy because they are effectively shorted as mentioned
previously, significantly reducing the available energy.
This is the major difference between the active and passive
transitions. If the energy stored in the leakage and commutating inductance is greater than the capacitive energy,
the transition will be completed successfully. During the
transition, an increasing reverse voltage is applied to the
leakage and commutating inductances, helping the overall
primary current to decay. The inductive energy is thus
During power pulse 2, current builds up in the primary
winding in the opposite direction as power pulse 1. The
primary current consists of reflected output inductor
current and current due to the primary magnetizing inductance. At the end of State 4, MOSFET MC turns off and an
active transition, essentially similar to State 2, but opposite in direction (high to low) takes place.
Zero Voltage Switching (ZVS)
A lossless switching transition requires that the respective
full-bridge MOSFETs be switched to the “ON” state at the
exact instant their drain to source voltage is zero. Delaying
the turn-on results in lower efficiency due to circulating
current flowing in the body diode of the primary side
MOSFET rather than its low resistance channel. Premature
turn-on produces hard switching of the MOSFETs, increasing noise and power dissipation.
372212i
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OPERATIO
State 1.
POWER PULSE 1
VIN
VOUT
L01
MC
MA
N:1
+
MD
MB
LOAD
L02
MF
ME
IP ≈ IL01/N + (VIN • TOVL)/LMAG
PRIMARY AND
SECONDARY SHORTED
State 2.
ACTIVE
TRANSITION
MA
FREEWHEEL
INTERVAL
MC
VOUT
MA
MC
LOAD
MB
MD
MB
MD
MF
State 3.
PASSIVE
TRANSITION
MA
MC
MB
MD
State 4.
MA
ME
POWER PULSE 2
VOUT
MC
LOAD
MB
+
MD
MF
ME
3722 F01
Figure 1. ZVS Operation
372212i
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LTC3722-1/LTC3722-2 Adaptive Delay Circuitry
The LTC3722-1/LTC3722-2 monitors both the input supply and instantaneous bridge leg voltages, and commands
a switching transition when the expected zero voltage
condition is reached. DirectSense technology provides
optimal turn-on delay timing, regardless of input voltage,
output load, or component tolerances. The DirectSense
technique requires only a simple voltage divider sense
network to implement. If there is not enough energy to
fully commutate the bridge leg to a ZVS condition, the
LTC3722-1/LTC3722-2 automatically overrides the
DirectSense circuitry and forces a transition. The override
or default delay time is programmed with a resistor from
DPRG to VREF.
Adaptive Mode
The LTC3722-1/LTC3722-2 are configured for adaptive
delay sensing with three pins, ADLY, PDLY and SBUS.
ADLY and PDLY sense the active and passive delay legs
respectively via a voltage divider network as shown in
Figure 2.
VIN
A
R2
C
ADLY
SBUS
R5
R6
ADLY and PDLY are connected through voltage dividers to
the active and passive bridge legs respectively. The lower
resistor in the divider is set to 1k. The upper resistor in the
divider is selected for the desired positive transition trip
threshold.
To set up the ADLY and PDLY resistors, first determine at
what drain to source voltage to turn-on the MOSFETs.
Finite delays exist between the time at which the LTC37221/LTC3722-2 controller output transitions, to the time at
which the power MOSFET switches on due to MOSFET
turn on delay and external driver circuit delay. Ideally, we
want the power MOSFET to switch at the instant there is
zero volts across it. By setting a threshold voltage for
ADLY and PDLY corresponding to several volts across the
MOSFET, the LTC3722-1/LTC3722-2 can “anticipate” a
zero voltage VDS and signal the external driver and switch
to turn-on. The amount of anticipation can be tailored for
any application by modifying the upper divider resistor(s).
The LTC3722-1/LTC3722-2 DirectSense circuitry sources
a trimmed current out of PDLY and ADLY after a low to
high level transition occurs. This provides hysteresis and
noise immunity for the PDLY and ADLY circuitry, and sets
the high to low threshold on ADLY or PDLY to nearly the
same level as the low to high threshold, thereby making
the upper and lower MOSFET VDS switch points virtually
identical, independent of VIN.
PDLY
B
R1
1k
Example: VIN = 48V nominal (36V to 72V)
D
R3
1k
R4
1k
RCS
1. Set up SBUS: 1.5V is desired on SBUS with VIN = 48V.
Set divider current to 100µA.
1922 F02
R1 = 1.5V/100µA = 15k.
Figure 2. Adaptive Mode
The threshold voltage on PDLY and ADLY for both the
rising and falling transitions is set by the voltage on SBUS.
A buffered version of this voltage is used as the threshold
level for the internal DirectSense circuitry. At nominal VIN,
the voltage on SBUS is set to 1.5V by an external voltage
divider between VIN and GND, making this voltage directly
proportional to V IN . The LTC3722-1/LTC3722-2
DirectSense circuitry uses this characteristic to zero
voltage switch all of the external power MOSFETs, independent of input voltage.
R2 = (48V – 1.5V)/100µA = 465k.
An optional small capacitor (0.001µF) can be added
across R1 to decouple noise from this input.
2. Set up ADLY and PDLY: 7V of “anticipation” is desired
in this circuit to account for the delays of the external
MOSFET driver and gate drive components.
R3, R4 = 1k, sets a nominal 1.5mA in the divider
chain at the threshold.
R5, R6 = (48V – 7V – 1.5V)/1.5mA = 26.3k,
use (2) equal 13k segments.
372212i
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LTC3722-1/LTC3722-2
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OPERATIO
Fixed Delay Mode
Powering the LTC3722-1/LTC3722-2
The LTC3722-1/LTC3722-2 provides the flexibility through
the SBUS pin to disable the DirectSense delay circuitry and
enable fixed ZVS delays. The level of fixed ZVS delay is
proportional to the voltage programmed through the voltage divider on the PDLY and ADLY pins. See Figure␣ 3 for
more detail.
The LTC3722-1/LTC3722-2 utilize an integrated VCC shunt
regulator to serve the dual purposes of limiting the voltage
applied to VCC as well as signaling that the chip’s bias
voltage is sufficient to begin switching operation (under
voltage lockout). With its typical 10.2V turn-on voltage
and 4.2V UVLO hysteresis, the LTC3722-1/LTC3722-2 is
tolerant of loosely regulated input sources such as an
auxiliary transformer winding. The VCC shunt is capable of
sinking up to 25mA of externally applied current. The
UVLO turn-on and turn-off thresholds are derived from an
internally trimmed reference making them extremely accurate. In addition, the LTC3722-1/LTC3722-2 exhibits
very low (145µA typ) start-up current that allows the use
of 1/8W to 1/4W trickle charge start-up resistors.
VREF
R1
SBUS
PDLY
R2
ADLY
R3
3722 F03
The trickle charge resistor should be selected as follows:
RSTART(MAX) = VIN(MIN) – 10.7V/250µA
Figure 3. Setup for Fixed ZVS Delays
Programming Adaptive Delay Time-Out
The LTC3722-1/LTC3722-2 controllers include a feature
to program the maximum time delay before a bridge
switch turn on command is summoned. This function will
come into play if there is not enough energy to commutate
a bridge leg to the opposite supply rail, therefore bypassing the adaptive delay circuitry. The time delay can be set
with an external resistor connected between DPRG and
VREF ( see Figure 4). The nominal regulated voltage on
DPRG is 2V. The external resistor programs a current
which flows into DPRG. The delay can be adjusted from
approximately 35ns to 300ns, depending on the resistor
value. If DPRG is left open, the delay time is approximately
400ns. The amount of delay can also be modulated based
on an external current source that feeds current into
DPRG. Care must be taken to limit the current fed into
DPRG to 350µA or less.
VREF
RDPRG
Adding a small safety margin and choosing standard
values yields:
APPLICATION
VIN RANGE
RSTART
DC/DC
36V to 72V
100k
Off-Line
85V to 270VRMS
430k
390VDC
1.4M
PFC Preregulator
VCC should be bypassed with a 0.1µF to 1µF multilayer
ceramic capacitor to decouple the fast transient currents
demanded by the output drivers and a bulk tantalum or
electrolytic capacitor to hold up the VCC supply before the
bootstrap winding, or an auxiliary regulator circuit takes
over.
CHOLDUP = (ICC + IDRIVE) • tDELAY/3.8V
(minimum UVLO hysteresis)
Regulated bias supplies as low as 7V can be utilized to
provide bias to the LTC3722-1/LTC3722-2. Refer to
Figure 5 for various bias supply configurations.
VIN
12V ±10%
DPRG
+
+
V 2V
–
SBUS
–
1.5k
1N5226
3V
1N914
RSTART
TURN-ON
OUTPUT
+
0.1µF
0.1µF
3722 F04
Figure 4. Delay Timeout Circuitry
VBIAS < VUVLO
VCC
VCC
CHOLD
3722 F04
Figure 5. Bias Configurations
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LTC3722-1/LTC3722-2
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OPERATIO
Programming Undervoltage Lockout
The LTC3722-1/LTC3722-2 provides undervoltage lockout (UVLO) control for the input DC voltage feed to the
power converter in addition to the VCC UVLO function
described in the preceding section. Input DC feed UVLO is
provided with the UVLO pin. A comparator on UVLO
compares a divided down input DC feed voltage to the 5V
precision reference. When the 5V level is exceeded on
UVLO, the SS pin is released and output switching commences. At the same time a 10µA current is enabled which
flows out of UVLO into the voltage divider connected to
UVLO. The amount of DC feed hysteresis provided by this
current is: 10µA • RTOP, see Figure 6. The system UVLO
threshold is: 5V • {(RTOP + RBOTTOM)/RBOTTOM}. If the
voltage applied to UVLO is present and greater than 5V
prior to the VCC UVLO circuitry activation, then the internal
UVLO logic will prevent output switching until the following three conditions are met: (1) VCC UVLO is enabled, (2)
VREF is in regulation and (3) UVLO pin is greater than 5V.
maintains decent regulation as the supply voltage varies,
and it does not require full safety isolation from the input
winding of the transformer. Some manufacturers include
a primary winding for this purpose in their standard
product offerings as well. A different approach is to add a
winding to the output inductor and peak detect and filter
the square wave signal (see Figure 7b). The polarity of this
winding is designed so that the positive voltage square
wave is produced while the output inductor is freewheeling. An advantage of this technique over the previous is
that it does not require a separate filter inductor and since
the voltage is derived from the well-regulated output
voltage, it is also well controlled. One disadvantage is that
this winding will require the same safety isolation that is
required for the main transformer. Another disadvantage
is that a much larger VCC filter capacitor is needed, since
it does not generate a voltage as the output is first starting
up, or during short-circuit conditions.
VIN
VCC
RSTART
UVLO can also be used to enable and disable the power
converter. An open drain transistor connected to UVLO as
shown in Figure 6 provides this capability.
2k
+
15V*
0.1µF
CHOLD
1922 F05a
*OPTIONAL
RTOP
UVLO
ON OFF
RBOTTOM
Figure 7a. Auxiliary Winding Bias Supply
VIN
VOUT
LOUT
3722 F0A
RSTART
ISO BARRIER
+
Figure 6. System UVLO Setup
0.1µF
CHOLD
Off-Line Bias Supply Generation
If a regulated bias supply is not available to provide VCC
voltage to the LTC3722-1/LTC3722-2 and supporting
circuitry, one must be generated. Since the power requirement is small, approximately 1W, and the regulation is not
critical, a simple open-loop method is usually the easiest
and lowest cost approach. One method that works well is
to add a winding to the main power transformer, and post
regulate the resultant square wave with an L-C filter (see
Figure␣ 7a). The advantage of this approach is that it
VCC
1922 F05b
Figure 7b. Output Inductor Bias Supply
Programming the LTC3722-1/LTC3722-2 Oscillator
The high accuracy LTC3722-1/LTC3722-2 oscillator circuit provides flexibility to program the switching frequency, slope compensation, and synchronization with
minimal external components. The LTC3722-1/LTC3722-2
372212i
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LTC3722-1/LTC3722-2
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OPERATIO
oscillator circuitry produces a 2.2V peak-to-peak amplitude ramp waveform on CT and a narrow pulse on SYNC
that can be used to synchronize other PWM chips. Typical
maximum duty cycles of 98.5% are obtained at 300kHz
and 96% at 1MHz. A compensating slope current is
derived from the oscillator ramp waveform and sourced
out of CS.
The desired amount of slope compensation is selected
with single external resistor. A capacitor to GND on CT
programs the switching frequency. The CT ramp discharge current is internally set to a high value (>10mA).
The dedicated SYNC I/O pin easily achieves synchronization. The LTC3722-1/LTC3722-2 can be set up to either
synchronize other PWM chips or be synchronized by
another chip or external clock source. The 1.8V SYNC
threshold allows the LTC3722-1/LTC3722-2 to be synchronized directly from all standard 3V and 5V logic
families.
Design Procedure:
1. Choose CT for the desired oscillator frequency. The
switching frequency selected must be consistent with the
power magnetics and output power level. This is detailed
in the Transformer Design section. In general, increasing
the switching frequency will decrease the maximum achievable output power, due to limitations of maximum duty
cycle imposed by transformer core reset and ZVS. Remember that the output frequency is 1/2 that of the
oscillator.
CT = 1/(13.4k • fOSC)
Example: Desired fOSC = 330kHz
CT = 1/(13.4k • fOSC) = 226pF, choose closest standard
value of 220pF. A 5% or better tolerance multilayer NPO
or X7R ceramic capacitor is recommended for best
performance.
2. The LTC3722-1/LTC3722-2 can either synchronize other
PWMs, or be synchronized to an external frequency source
or PWM chip. See Figure 8 for details.
3. Slope compensation is required for most peak current
mode controllers in order to prevent subharmonic oscilla-
CT OF SLAVE(S) IS
1.25 CT OF MASTER.
LTC3722
CT
5.1k
MASTER
CT
SYNC
CT
5.1k
SYNC
CT
LTC3722
1k
1k
SYNC
•
•
5.1k
•
UP TO
5 SLAVES
LTC3722
CT
CT
SLAVES
3722 F06a
Figure 8a. SYNC Output (Master Mode)
AMPLITUDE > 1.8V
100ns < PW < 0.4/ƒ
EXTERNAL
FREQUENCY
SOURCE
1k
SYNC
5.1k
LTC3722
CT
CT
3722 F06b
Figure 8b. SYNC Input from an External Source
tion of the current control loop. In general, if the system
duty cycle exceeds 50% in a fixed frequency, continuous
current mode converter, an unstable condition exists
within the current control loop. Any perturbation in the
current signal is amplified by the PWM modulator resulting in an unstable condition. Some common manifestations of this include alternate pulse nonuniformity and
pulse width jitter. Fortunately, this can be addressed by
adding a corrective slope to the current sense signal or by
subtracting the same slope from the current command
signal (error amplifier output). In theory, the current
doubler output configuration does not require slope compensation since the output inductor duty cycles only
approach 50%. However, transient conditions can momentarily cause higher duty cycles and therefore, the
possibility for unstable operation. The exact amount of
required slope compensation is easily programmed by the
LTC3722-1/LTC3722-2 with the addition of a single external resistor (see Figure 9). The LTC3722-1/LTC3722-2
generates a current that is proportional to the instantaneous voltage on CT, (33µA/V(CT)). Thus, at the peak of CT,
this current is approximately 82.5µA and is output from
the CS pin. A resistor connected between CS and the
external current sense resistor sums in the required amount
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OPERATIO
of slope compensation. The value of this resistor is dependent on several factors including minimum VIN, VOUT,
switching frequency, current sense resistor value and
output inductor value. An illustrative example with the
design equation is provided below.
Example: VIN = 36V to 72V
VOUT = 3.3V
IOUT = 40A
L = 2.2µH
Transformer turns ratio (N) = VIN(MIN) • DMAX/
VOUT␣ =␣ 3
RCS = 0.025Ω
fSW = 300kHz, i.e., transformer f = fSW/2 = 150kHz
RSLOPE = VO • RCS/(2 • L • fT • 82.5µA • N) = 3.3V • 0.025/
(2 • 2.2µA • 100k • 82.5µA • 3)
RSLOPE = 505Ω, choose the next higher standard value
to account for tolerances in ISLOPE, RCS, N and L.
LTC3722
BRIDGE
CURRENT
RSLOPE
CS
ADDED
SLOPE
33k
RCS
CURRENT SENSE
WAVEFORM
3722 F07
Figure 9. Slope Compensation Circuitry
PULSE BY PULSE
CURRENT LIMIT
φMOD
+
RCS
270mV
PWM
LATCH
Q
Q
S Q
S
–
R
OVERLOAD
CURRENT LIMIT
+
650mV
PWM
LOGIC
H = SHUTDOWN
OUTPUTS
UVLO
ENABLE
S Q
–
UVLO
ENABLE
4.1V
–
CS
The pulse-by-pulse comparator has a 270mV nominal
threshold. If the 270mV threshold is exceeded, the PWM
cycle is terminated. The overcurrent comparator is set
approximately 2x higher than the pulse-by-pulse level. If
the current signal exceeds this level, the PWM cycle is
terminated, the soft-start capacitor is quickly discharged
and a soft-start cycle is initiated. If the overcurrent condition persists, the LTC3722-1/LTC3722-2 halts PWM operation and waits for the soft-start capacitor to charge up
to approximately 4V before a retry is allowed. The softstart capacitor is charged by an internal 12µA current
source. If the fault condition has not cleared when softstart reaches 4V, the soft-start pin is again discharged and
a new cycle is initiated. This is referred to as hiccup mode
operation. In normal operation and under most abnormal
conditions, the pulse-by-pulse comparator is fast enough
to prevent hiccup mode operation. In severe cases, however, with high input voltage, very low RDS(ON) MOSFETs
and a shorted output, or with saturating magnetics, the
overcurrent comparator provides a means of protecting
the power converter.
R
12µA
SS
0.4V
+
V(CT)
33k
Current sensing provides feedback for the current mode
control loop and protection from overload conditions. The
LTC3722-1/LTC3722-2 are compatible with either resistive sensing or current transformer methods. Internally
connected to the LTC3722-1/LTC3722-2 CS pin are two
comparators that provide pulse-by-pulse and overcurrent
shutdown functions respectively. (See Figure 10)
+
CT
I=
Current Sensing and Overcurrent Protection
CSS
–
Q
3722 F08
Figure 10. Current Sense/Fault Circuitry Detail
372212i
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OPERATIO
Leading Edge Blanking
Current Transformer Sensing
The LTC3722-1/LTC3722-2 provides programmable leading edge blanking to prevent nuisance tripping of the
current sense circuitry. Leading edge blanking relieves the
filtering requirements for the CS pin, greatly improving the
response to real overcurrent conditions. It also allows the
use of a ground referenced current sense resistor or
transformer(s), further simplifying the design. With a
single 10k to 100k resistor from RLEB to GND, blanking
times of approximately 40ns to 320ns are programmed. If
not required, connecting RLEB to VREF can disable leading
edge blanking. Keep in mind that the use of leading edge
blanking will set a minimum linear control range for the
phase modulation circuitry.
A current sense transformer can be used in lieu of resistive
sensing with the LTC3722-1/LTC3722-2. Current sense
transformers are available in many styles from several
manufacturers. A typical sense transformer for this application will use a 1:50 turns ratio (N), so that the sense
resistor value is N times larger, and the secondary current
N times smaller than in the resistive sense case. Therefore,
the sense resistor power loss is about N times less with the
transformer method, neglecting the transformers core
and copper losses. The disadvantages of this approach
include, higher cost and complexity, lower accuracy, core
reset/max duty cycle limitations and lower speed. Nevertheless, for very high power applications, this method is
preferred. The sense transformer primary is placed in the
same location as the ground referenced sense resistor, or
between the upper MOSFET drains in the (MA, MC) and
VIN. The advantage of the high side location is a greater
immunity to leading edge noise spikes, since gate charge
current and reflected rectifier recovery current are largely
eliminated. Figure 11 illustrates a typical current sense
transformer based sensing scheme. RS in this case is
calculated the same as in the resistive case, only its value
is increased by the sense transformer turns ratio. At high
duty cycles, it may become difficult or impossible to reset
the current transformer. This is because the required
transformer reset voltage increases as the available time
for reset decreases to equalize the (volt • seconds) applied.
The interwinding capacitance and secondary inductance
of the current sense transformer form a resonant circuit
that limits the dV/dT on the secondary of the CS transformer. This in turn limits the maximum achievable duty
cycle for the CS transformer. Attempts to operate beyond
this limit will cause the transformer core to “walk” and
eventually saturate, opening up the current feedback loop.
Resistive Sensing
A resistor connected between input common and the
sources of MB and MD is the simplest method of current
sensing for the full-bridge converter. This is the preferred
method for low to moderate power levels. The sense
resistor should be chosen such that the maximum rated
output current for the converter can be delivered at the
lowest expected VIN. Use the following formula to calculate the optimal value for RCS.
LTC3722-1:
RCS =
270mV – (82.5µA • RSLOPE)
IP (PEAK)
IP (PEAK) =
IO(MAX)
+
VIN(MAX) • 2 • DMIN
LMAG • f CLK
2 • N • EFF
VO (1 – DMIN )
LOUT • f CLK• N
+
Common methods to address this limitation include:
NP
where: N = Transformer turns ratio =
NS
1. Reducing the maximum duty cycle by lowering the
power transformer turns ratio.
LTC3722-2:
2. Reducing the switching frequency of the converter.
3. Employ external active reset circuitry.
RCS
270mV
=
IP (PEAK)
372212i
19
LTC3722-1/LTC3722-2
U
OPERATIO
4. Using two CS transformers summed together.
directly. The voltage COMP is internally attenuated by the
LTC3722-1. The attenuated COMP voltage provides one
input to the phase modulation comparator. This is the
current command. The other input to the phase modulation comparator is the RAMP voltage, level shifted by
approximately 650mV. This is the current loop feedback.
During every switching cycle, alternate diagonal switches
(MA-MD or MB-MC) conduct and cause current in an
output inductor to increase. This current is seen on the
primary of the power transformer divided by the turns
ratio. Since the current sense resistor is connected between GND and the two bottom bridge transistors, a
voltage proportional to the output inductor current will be
seen across RSENSE. The high side of RSENSE is also
connected to CS, usually through a small resistor (RSLOPE).
When the voltage on CS exceeds either (COMP/5.2)
– 650mV, or 270mV, the overlap conduction period will
terminate. During normal operation, the attenuated COMP
voltage will determine the CS trip point. During start-up, or
slewing conditions following a large load step, the 270mV
CS threshold will terminate the cycle, as COMP will be
driven high, such that the attenuated version exceeds the
270mV threshold. In extreme conditions, the 650mV
threshold on CS will be exceeded, invoking a soft-start/
restart cycle.
5. Choose a CS transformer optimized for high frequency
applications.
MD
SOURCE
MB
SOURCE
RSLOPE
N:1
RAMP
CURRENT
TRANSFORMER
RS
CS
OPTIONAL
FILTERING
1922 F10
Figure 11. Current Transformer Sense Circuitry
Phase Modulator (LTC3722-1)
The LTC3722-1 phase modulation control circuitry is
comprised of the phase modulation comparator and logic,
the error amplifier, and the soft-start amplifier (see Figure␣ 12). Together, these elements develop the required
phase overlap (duty cycle) required to keep the output
voltage in regulation. In isolated applications, the sensed
output voltage error signal is fed back to COMP across the
input to output isolation boundary by an optical coupler
and shunt reference/error amplifier (LT®1431) combination. The FB pin is connected to GND, forcing COMP high.
The collector of the optoisolator is connected to COMP
FB
–
1.2V
TOGGLE
F/F
Q
ERROR
AMPLIFIER
+
50k
PHASE
MODULATION
COMPARATOR
COMP
VREF
SS
Q
–
PHASE
MODULATION
LOGIC
+
S Q
+
12µA
+
A
CLK
CLK
650mV
SOFT-START
AMPLIFIER
–
B
C
D
R
FROM
CURRENT
LIMIT
COMPARATOR
–
14.9k
RLEB
CS
BLANKING
Q S
R
CLK
3722 F11
Figure 12. Phase Modulation Circuitry (LTC3722-1)
372212i
20
LTC3722-1/LTC3722-2
U
OPERATIO
Selecting the Power Stage Components
Perhaps the most critical part of the overall design of the
converter is selecting the power MOSFETs, transformer,
inductors and filter capacitors. Tremendous gains in efficiency, transient performance and overall operation can
be obtained as long as a few simple guidelines are followed
with the phase shifted full-bridge topology.
Power Transformer
Switching frequency, core material characteristics, series
resistance and input/output voltages all play an important
role in transformer selection. Close attention also needs to
be paid to leakage and magnetizing inductances as they
play an important role in how well the converter will
achieve ZVS. Planar magnetics are very well suited to
these applications because of their excellent control of
these parameters.
Turns Ratio
The required turns ratio for a current doubler secondary is
given below. Depending on the magnetics selected, this
value may need to be reduced slightly.
Turns ratio formula:
N=
VIN(MIN) • DMAX
2 • VOUT
where:
VIN(MIN) = Minimum VIN for operation
DMAX = Maximum duty cycle of controller (DCMAX)
maximized at high duty cycle and decreases as the duty
cycle reduces. This means that a current doubler converter requires less output capacitance for the same
performance as a conventional converter. By determining
the minimum duty cycle for the converter, worse-case
VOUT ripple can be derived by the formula given below.
VORIPPLE = IRIPPLE • ESR =
VO • ESR
(1 – D)(1 – 2D)
LO • 2 • f SW
where:
D
= minimum duty cycle
fSW = oscillator frequency
LO
= output inductance
ESR = output capacitor series resistance
The amount of bulk capacitance required is usually system
dependent, but has some relationship to output inductance value, switching frequency, load power and dynamic
load characteristics. Polymer electrolytic capacitors are
the preferred choice for their combination of low ESR,
small size and high reliability. For less demanding applications, or those not constrained by size, aluminum electrolytic capacitors are commonly applied. Most
DC/DC converters in the 100kHz to 300kHz range use 20µF
to 25µF of bulk capacitance per watt of output power.
Converters switching at higher frequencies can usually
use less bulk capacitance. In systems where dynamic
response is critical, additional high frequency capacitors,
such as ceramics, can substantially reduce voltage transients.
Output Capacitors
Power MOSFETs
Output capacitor selection has a dramatic impact on ripple
voltage, dynamic response to transients and stability.
Capacitor ESR along with output inductor ripple current
will determine the peak-to-peak voltage ripple on the
output. The current doubler configuration is advantageous because it has inherent ripple current reduction.
The dual output inductors deliver current to the output
capacitor 180 degrees out of phase, in effect, partially
canceling each other’s ripple current. This reduction is
The full-bridge power MOSFETs should be selected for
their RDS(ON) and BVDSS ratings. Select the lowest BVDSS
rated MOSFET available for a given input voltage range
leaving at least a 20% voltage margin. Conduction losses
are directly proportional to RDS(ON). Since the full-bridge
has two MOSFETs in the power path most of the time,
conduction losses are approximately equal to:
2 • RDS(ON) • I2, where I = IO/2N
372212i
21
LTC3722-1/LTC3722-2
U
OPERATIO
Switching losses in the MOSFETs are dominated by the
power required to charge their gates, and turn-on and
turn-off losses. At higher power levels, gate charge power
is seldom a significant contributor to efficiency loss. ZVS
operation virtually eliminates turn-on losses. Turn-off
losses are reduced by the use of an external drain to source
snubber capacitor and/or a very low resistance turn-off
driver. If synchronous rectifier MOSFETs are used on the
secondary, the same general guidelines apply. Keep in
mind, however, that the BVDSS rating needed for these can
be greater than VIN(MAX)/N, depending on how well the
secondary is snubbed. Without snubbing, the secondary
voltage can ring to levels far beyond what is expected due
to the resonant tank circuit formed between the secondary
leakage inductance and the COSS (output capacitance) of
the synchronous rectifier MOSFETs.
Switching Frequency Selection
Unless constrained by other system requirements, the
power converter’s switching frequency is usually set as
high as possible while staying within the desired efficiency
target. The benefits of higher switching frequencies are
many including smaller size, weight and reduced bulk
capacitance. In the full-bridge phase shift converter, these
principles are generally the same with the added complication of maintaining zero voltage transitions, and therefore, higher efficiency. ZVS is achieved in a finite time
during the switching cycle. During the ZVS time, power is
not delivered to the output; the act of ZVS reduces the
maximum available duty cycle. This reduction is proportional to maximum output power since the parasitic capacitive element (MOSFETs) that increase ZVS time get
larger as power levels increase. This implies an inverse
relationship between output power level and switching
frequency. Table 1 displays recommended maximum
switching frequency vs power level for a 30V/75V in to
3.3V/5V out converter. Higher switching frequencies can
be used if the input voltage range is limited, the output
voltage is lower and/or lower efficiency can be tolerated.
Table 1.Switching Frequency vs Power Level
<50W
600kHz
<100W
450kHz
<200W
300kHz
<500W
200kHz
<1kW
150kHz
<2kW
100kHz
Closing the Feedback Loop
Closing the feedback loop with the full-bridge converter
involves identifying where the power stage and other
system poles/zeroes are located and then designing a
compensation network around the converters error amplifier to shape the frequency response to insure adequate
phase margin and transient response. Additional modifications will sometimes be required in order to deal with
parasitic elements within the converter that can alter the
feedback response. The compensation network will vary
depending on the load current range and the type of output
capacitors used. In isolated applications, the compensation network is generally located on the secondary side of
the power supply, around the error amplifier of the
optocoupler driver, usually an LT1431 or equivalent. In
nonisolated systems, the compensation network is located around the LTC3722-1/LTC3722-2’s error amplifier.
In current mode control, the dominant system pole is
determined by the load resistance (VO/IO) and the output
capacitor 1/(2π • RO • CO). The output capacitors ESR
1/(2π • ESR • CO) introduces a zero. Excellent DC line and
load regulation can be obtained if there is high loop gain at
DC. This requires an integrator type of compensator
around the error amplifier. A procedure is provided for
deriving the required compensation components. More
complex types of compensation networks can be used to
obtain higher bandwidth if necessary.
Step 1. Calculate location of minimum and maximum
output pole:
372212i
22
LTC3722-1/LTC3722-2
U
OPERATIO
FP1(MIN) = 1/(2π • RO(MAX) • CO)
Polymer Electrolytic (see Figure 13) 1/(2πCCRI) sets a
low frequency pole. 1/(2πCCRF) sets the low frequency
zero. The zero frequency should coincide with the worstcase lowest output pole frequency. The pole frequency
and mid frequency gain (RF/RI) should be set such so that
the loop crosses over zero dB with a –1 slope at a
frequency lower than (fSW/8). Use a bode plot to graphically display the frequency response. An optional higher
frequency pole set by CP2 and Rf is used to attenuate
switching frequency noise.
FP1(MAX) = 1/(2π • RO(MIN) • CO)
Step 2. Calculate ESR zero location:
FZ1 = 1/(2π • RESR • CO)
Step 3. Calculate the feedback divider gain:
RB/(RB + RT) or VREF/VOUT
If Polymer electrolytic output capacitors are used, the ESR
zero can be employed in the overall loop compensation
and optimum bandwidth can be achieved. If aluminum
electrolytics are used, the loop will need to be rolled off
prior to the ESR zero frequency, making the loop response
slower. A linearized SPICE macromodel of the control loop
is very helpful tool to quickly evaluate the frequency
response of various compensation networks.
Aluminum Electrolytic (see Figure 13) the goal of this
compensator will be to cross over the output minimum
pole frequency. Set a low frequency pole with CC and RIN
at a frequency that will cross over the loop at the output
pole minimum F, place the zero formed by CC and Rf at the
output pole F.
VOUT
CP2
VOUT
OPTIONAL
CC
Rf
CO
RI
REF
RL
–
ESR
COMP
OPTO
RD
2.5V
COLL
+
LT1431 OR EQUIVALENT
PRECISION ERROR
AMP AND REFERENCE
1922 F12
Figure 13. Compensation for Polymer Electrolytic
372212i
23
LTC3722-1/LTC3722-2
U
OPERATIO
Synchronous Rectification
The LTC3722-1/LTC3722-2 produces the precise timing
signals necessary to control current doubler secondary
side synchronous MOSFETs on OUTE and OUTF. Synchronous rectifiers are used in place of Schottky or Silicon
diodes on the secondary side of the power supply. As
MOSFET RDS(ON) levels continue to drop, significant efficiency improvements can be realized with synchronous
rectification, provided that the MOSFET switch timing is
optimized. An additional benefit realized with synchronous rectifiers is bipolar output current capability. These
characteristics improve transient response, particularly
overshoot, and improve ZVS ability at light loads.
Programming the Synchronous Rectifier Turn-Off
Delay
The LTC3722-1/LTC3722-2 controllers include a feature
to program the turn-off edge of the secondary side synchronous rectifier MOSFETs relative to the beginning of a
new primary side power delivery pulse. This feature provides optimized timing for the synchronous MOSFETs
which improves efficiency. At higher load currents it
becomes more advantageous to delay the turn-off of the
synchronous rectifiers until the transformer core has been
reset to begin the new power pulse. This allows for
secondary freewheeling current to flow through the synchronous MOSFET channel instead of its body diode.
The turn-off delay is programmed with a resistor from
SPRG to GND, see Figure 14. The nominal regulated
voltage on SPRG is 2V. The external resistor programs a
current which flows out of SPRG. The delay can be
adjusted from approximately 20ns to 200ns, with resistor
values of 10k to 200k. Do not leave SPRG floating. The
amount of delay can also be modulated based on an
external current source that sinks current out of SPRG.
Care must be taken to limit the current out of SPRG to
350µA or less.
SPRG
RSPRG
+
V 2V
–
+
–
TURN-OFF
SYNC OUT
3722 F0Y
Figure 14. Synchronous Delay Circuitry
372212i
24
LTC3722-1/LTC3722-2
U
OPERATIO
Current Doubler
The current doubler secondary employs two output inductors that equally share the output load current. The transformer secondary is not center-tapped. This configuration
provides 2x higher output current capability compared to
similarly sized single output inductor modules, hence the
name. Each output inductor is twice the inductance value
as the equivalent single inductor configuration and the
transformer turns ratio is 1/2 that of a single inductor
secondary. The drive to the inductors is 180 degrees out
of phase which provides partial ripple current cancellation
in the output capacitor(s). Reduced capacitor ripple current lowers output voltage ripple and enhances the
1
capacitors’s reliability. The amount of ripple cancellation
is related to duty cycle (see Figure 15). Although the
current doubler requires an additional inductor, the inductor core volume is proportional to LI2, thus the size penalty
is small. The transformer construction is simplified without a center-tap winding and the turns ratio is reduced by
1/2 compared to a conventional full wave rectifier configuration.
Synchronous rectification of the current doubler secondary requires two ground referenced N-channel MOSFETs.
The timing of the LTC3722-1/LTC3722-2 drive signals is
shown in the Timing Diagram.
NOTE: INDUCTOR(S) DUTY CYCLE
IS LIMITED TO 50% WITH CURRENT
DOUBLER PHASE SHIFT CONTROL.
NORMALIZED
OUTPUT RIPPLE
CURRENT
ATTENUATION
0
0
0.25
DUTY CYCLE
0.5
1922 • F13
Figure 15. Ripple Current Cancellation vs Duty Cycle
372212i
25
LTC3722-1/LTC3722-2
U
OPERATIO
Full-Bridge Gate Drive
does not require the propagation delays of the high and
low side drive circuits to be precisely matched as the
DirectSense ZVS circuitry will adapt accordingly. As a
result, LTC3722-1/LTC3722-2 can drive a simple NPNPNP buffer or a gate driver chip like the LTC1693-1 to
provide the low side gate drive. Providing drive to the high
side presents additional challenges since the MOSFET
gate must be driven above the input supply. A simple
circuit (Figure 17) using a single LTC1693-1, an inexpensive signal transformer, and a few discrete components
provides both high side gate drives (A and C) reliably.
The full-bridge converter requires high current MOSFET
gate driver circuitry for two ground referenced switches
and two high side referred switches. Providing drive to the
ground referenced switches is not too difficult as long as
the traces from the gate driver chip or buffer to the gate and
source leads are short and direct. Drive requirements are
further eased since all of the switches turn on with zero
VDS, eliminating the “Miller” effect. Low turn-off resistance is critical, however, in order to prevent excessive
turn-off losses resulting from the same Miller effects that
were not an issue for turn on. The LTC3722-1/LTC3722-2
LTC1693-1
OUT1
IN1
LTC3722
1:2
OUTE
GND1
OUTF
GND2
IN2
OUT2
3722 F14
Figure 16. Isolated Drive Circuitry
VIN
REGULATED
BIAS
LTC3722
VCC
0.1µF
0.1µF
OUTA
OR
OUTC
IN
2k
BAT
54
2µF
CER
OUT
POWER
MOSFET
1/2
LTC1693-1
GND
SIGNAL
TRANSFORMER
BRIDGE
LEG
3722 F15
Figure 17. High Side Gate Driver Circuitry
372212i
26
LTC3722-1/LTC3722-2
U
PACKAGE DESCRIPTIO
GN Package
24-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.337 – .344*
(8.560 – 8.738)
24 23 22 21 20 19 18 17 16 15 1413
.033
(0.838)
REF
.045 ±.005
.229 – .244
(5.817 – 6.198)
.254 MIN
.150 – .157**
(3.810 – 3.988)
.150 – .165
1
.0165 ± .0015
2 3
4
5 6
7
8
9 10 11 12
.0250 TYP
RECOMMENDED SOLDER PAD LAYOUT
.015 ± .004
× 45°
(0.38 ± 0.10)
.007 – .0098
(0.178 – 0.249)
.053 – .068
(1.351 – 1.727)
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
.008 – .012
(0.203 – 0.305)
.0250
(0.635)
BSC
GN24 (SSOP) 0502
372212i
27
LTC3722-1/LTC3722-2
U
TYPICAL APPLICATIO
240W, 36-72 VIN to 12V/20A Isolated Supply
L5
1.3µH
VIN
36V TO
72V
VIN
+VIN
3× 0.82µF 10V
100V
0.82µF
100V
–VIN
T2
A 1µF 785µH 0.01µF
1:1
10V
D3
D4
T3
C 1µF 785µH 0.01µF
1:1
Q2
75Ω
Q3
1k
Q1
Q4
D22
1k
T4
7T(75µH): 6T: 6T
12
6
11
5
10
Q6
0.1µF
D7
A_LEG
L2
252nH
P_LEG
10V
1
2
10V
Q7
B
D21
75Ω
Q5
0.1µF
D6
PRELIMINARY SCHEMATIC, UNLESS NOTED:
ALL CAPS 25V, ALL RESISTORS 0603 (1/16W) OR 0805 (1/8W)
L4 COILCRAFT DO1608C-105
D3, D4, D12, D14 BAS21
L5 SUMIDA CDEP105-1R3MC-50
D6, D7, D15, D17 BAT54
D8, D9 ON-SEMI MMBD914LT1 Q1, Q2, Q7,Q9 ZETEX FMMT619
Q3, Q4, Q8, Q11-Q15 Si7456 DP
D16, D20 MMBZ5239B
Q5, Q6, Q10, Q16-Q18 ZETEX FMMT718
D21, D22 MURS120T3
T2, T3 PULSE PE-68386
D22 MMBZ5251B
T4 PULSE PB2001
L1,L3 PULSE PA0295
T5 PULSE PA0297
L2 PULSE PA0573
9
8
7
L1
6.7µH
VLOW
+VOUT
+VOUT
L3
VHIGH 6.7µH
220µF
16V
+
12V
20A
1µF
Q9
D
4
Q8
Q10
Q12,
Q13
Q11
Q14,
Q15
Q16
–VOUT
–VOUT
ISNS
10V
680Ω
0.04Ω
1.5W
15.4k
+
13.3k
13.3k
SBUS
1k
D8
Q17
3
1.5pF
100V
1.5pF
100V
1
13.3k
1k
1k
ADLY
D15
4.7k
4
D17
1nF
8
PDLY
100Ω
1/4W
6
0.1µF
22Ω
15k
D12
D14
Q18
D9
T5
1mH 1:0.5:0.5
P_LEG
13.3k
15.4k
15k
0.04Ω 68µF
1.5W
20V
–VOUT
A_LEG
VIN
680Ω
L4
1mH
220pF
5
7
OUT1
OUT2
3 LTC1693-1 6
IN2
VCC2
1
8
IN1
VCC1
2
4
GND2 GND1
51Ω
1/4W
+VOUT
D16
9.1V
0.1µF
5
10V
ADLY
11
SBUS
39Ω
1/4W
10
18
12
VIN
180k
100pF
SBUS ADLY
A
C
21
OUTA
19
OUTC
PDLY
B
OUTB
OUTD
–VOUT
ISNS 5VREF
D
17
20
VIN
15
OUTF
16
+VOUT
750Ω
OUTE
4
7
6
COMP
LTC3722-1
3
200Ω
1/4W
470Ω
1
9.53k
1k
0.1µF
0.1µF
10k
3
UVLO VREF
DPRG
14
2
5VREF
30k
27k
1µF
PDLY
9
NC
8
SYNC
1
CT
SPRG
RLEB
13
5
23
33k
0.068µF
24
5.1k
22
7
FB
CS
6
3
2
4
V COMP RTOP
LT1431
1
COLL
REF
+
MOC207
5
10k
150pF
1µF
GND PGND SS
330pF
8
2.2nF
250V
2
100k
D20
10V
GNDF GNDS RMID
6
5
0.022µF
2.49k
7
–VOUT
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1681/LT3781
Synchronous Forward Controller
High Efficiency 2-Switch Forward Control
LTC1696
Overvoltage Protection Controller
ThinSOT Package, Gate Drive for SCR Crowbar or External N-Channel MOSFET
LT1910
Protected High Side MOSFET Driver
8V-48V, Protected from –15V to 60V Transients, Auto Restart
LTC1922-1
Synchronous Phase Shift Controller
Adaptive ZVS, Primary Side Control
372212i
28
Linear Technology Corporation
LT/TP 0203 1.5K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507 ● www.linear.com
LINEAR TECHNOLOGY CORPORATION 2003