May 1997 ML4819 Power Factor and PWM Controller “Combo” GENERAL DESCRIPTION FEATURES The ML4819 is a complete boost mode Power factor Controller (PFC) which also contains a PWM controller. The PFC circuit is similar to the ML4812 while the PWM controller can be used for current or voltage mode control for a second stage converter. Since the PWM and PFC circuits share the same oscillator, synchronization of the two stages is inherent. The outputs of the controller IC provide high current (>1A peak) and high slew rate to quickly charge and discharge MOSFET gates. Special care has been taken in the design of the ML4819 to increase system noise immunity. ■ ■ ■ ■ s ■ Over-Voltage comparator helps prevent output “runaway” ■ Wide common mode range in current sense compensators for better noise immunity Under-Voltage Lockout circuit with 6V hysteresis rN ■ l4 ISENSE A e + 2 POWER FACTOR CONTROLLER R PWM B VCC GM OUT OVP S Q + PGND B EA OUT A ea s 4 Pl 5 6 19 INV A ISINE UNDER VOLTAGE LOCKOUT + 5V OUT B 8 14 13 – e 5V 9 0.7V – Se 3 11 1V ISENSE B – 5V ILIM 7 – M SLOPE COMPENSATION + RAMP COMP DUTY CYCLE – 1 CT PWM CONTROLLER + 12 OSC + 20 RT – 10 82 4 BLOCK DIAGRAM Current input gain modulator improves noise immunity Programmable Ramp Compensation circuit fo The PWM section includes cycle by cycle current limiting, precise duty cycle limiting for single ended converters, and slope compensation. Large oscillator amplitude for better noise immunity Precision duty cycle limit for PWM section ew The PFC section is of the peak current sensing boost type, using a current sense transformer or current sensing MOSFETs to non-dissipatively sense switch current. This gives the system overall efficiency over average current sensing control method. si gn ■ Two 1A peak current totem-pole output drivers Precision buffered 5V reference (±1%) De ■ – ERROR AMP IEA VREF VCC 18 15 R VCC OUT A GAIN MODULATOR S GND Q PGND A IMULT 16 17 REV. 1.0 10/10/2000 ML4819 PIN CONFIGURATION ML4819 20-Pin PDIP ISENSE A 1 20 CT OVP 2 19 GND GM OUT 3 18 VREF EA OUT A 4 17 PGND A INV A 5 16 OUT A ISINE 6 15 VCC DUTY CYCLE 7 14 OUT B PWM B 8 13 PGND B ISENSE B 9 12 RAMP COMP RT 10 11 ILIM TOP VIEW PIN DESCRIPTION PIN NAME FUNCTION PIN 1 ISENSE A Input form the PFC current sense transformer to the PWM comparator (+). Current Limit occurs when this point reaches 5V. 11 ILIM 2 OVP Input to Over-Voltage comparator. 3 GM OUT Output of Gain Modulator. A resistor to ground on this pin converts the current to a voltage. 4 EA OUT A Output of error amplifier. 5 INV A Inverting input to error amplifier. 6 ISINE Current Multiplier input. 7 DUTY CYCLE PWM controller duty cycle is limited by setting this pin to a fixed voltage. 8 PWM B Error voltage feedback input. 9 ISENSE B Input for Current Sense resistor for current mode operation or for Oscillator ramp for voltage mode operation. 10 RT 2 Oscillator timing resistor pin. A 5V source across this resistor sets the charging current for CT NAME FUNCTION Cycle by cycle PWM current limit. Exceeding 1V threshold on this pin terminates the PWM cycle. 12 RAMP COMP Buffered output from the Oscillator Ramp (CT). A resistor to ground sets a current, 1/2 of which is sourced on pins 9 and 11. 13 GND B Return for the high current totem pole output of the PWM controller. 14 OUT B PWM controller totem pole output. 15 VCC Positive Supply for the IC. 16 OUT A PFC controller totem pole output. 17 GND A Return for the high current totem pole output of the PFC controller. 18 VREF Buffered output for the 5V voltage reference 19 GND Analog signal ground. 20 CT Timing Capacitor for the Oscillator. REV. 1.0 10/10/2000 ML4819 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Supply Voltage (VCC) ................................................. 35V Output Current, Source or Sink (RAMP COMP) DC ....................................................................... 1.0A Output Energy (capacitive load per cycle) ................... 5µJ Multiplier ISINE Input (ISINE) ................................... 1.2mA Error Amp Sink Current (GM OUT) ........................ 10mA Oscillator Charge Current ........................................ 2mA Analog Inputs (ISENSE A, EA OUT A, INV A) ............................................................... –0.3V to 5.5V Junction Temperature ............................................. 150°C Storage Temperature Range ..................... –65°C to 150°C Lead Temperature (soldering 10 sec.) ..................... 260°C Thermal Resistance (θJA) Plastic DIP or SOIC ......................................... 60°C/W OPERATING CONDITIONS Temperature Range ML4819C .................................................. 0°C to 70°C ELECTRICAL CHARACTERISTICS Unless otherwise specified, RT = 14kΩ, CT = 1000pF, TA = Operating Temperature Range, VCC = 15V (Notes 1, 2). PARAMETER CONDITIONS MIN TYP MAX UNITS 97 104 kHz OSCILLATOR Initial Accuracy TJ = 25°C Voltage Stability 12V < VCC < 18V 90 Temperature Stability Total Variation Line, temp. 0.2 % 2 % 88 106 kHz Ramp Valley 0.9 V Ramp Peak 4.3 V RT Voltage Discharge Current (PWM B open) 4.8 5.0 5.2 V TJ = 25°C, VOUT A = 2V 7.5 8.4 9.3 mA VOUT A = 2V 7.2 8.4 9.5 mA 15 mV –2 –10 µA DUTY CYCLE LIMIT COMPARATOR Input Offset Voltage –15 Input Bias Current Duty Cycle VDUTY CYCLE = VREF/2 43 45 49 % Output Voltage TJ = 25°C, IO = 1mA 4.95 5.00 5.05 V Line Regulation 12V < VCC < 25V 2 20 mV Load Regulation 1mA < IO < 20mA 8 25 mV REFERENCE Temperature Stability 0.4 4.9 % Total Variation Line, load, temperature Output Noise Voltage 10Hz to 10kHz 50 Long Term Stability TJ = 125°C, 1000 hours, (Note 1) 5 25 mV Short Circuit Current VREF = 0V –85 –180 mA 15 mV –1.0 µA –30 5.1 V µV ERROR AMPLIFIER Input Offset Voltage –15 Input Bias Current –0.1 Open Loop Gain 1 < VEA OUT A < 5V 60 75 dB PSRR 12V < VCC < 25V 60 90 dB Output Sink Current VEA OUT A = 1.1V, VINV A = 5.2V 2 12 mA Output Source Current VEA OUT A = 5.0V, VINV A = 4.8V –0.5 –1.0 mA REV. 1.0 10/10/2000 3 ML4819 ELECTRICAL CHARACTERISTICS (Continued) PARAMETER CONDITIONS MIN TYP 6.5 7.0 MAX UNITS ERROR AMPLIFIER (continued) Output High voltage IEA OUT A = –0.5mA, VINV A = 4.8V Output Low Voltage IEA OUT A = 2mA, VINV A = 5.2V 0.7 Unity Gain Bandwidth V 1.0 1.0 V MHz GAIN MODULATOR ISINE Input Voltage ISINE = 500µA 0.4 0.7 0.9 V Output Current (GM OUT) ISINE = 500µA, INV A = VREF –20mV 460 495 505 µA 0 10 µA 990 1005 µA ISINE = 500µA, INV A = VREF + 20mV ISINE = 1mA, INV A = VREF – 20mV 900 Bandwidth PSRR 12V < VCC < 25V 200 kHz 70 dB VC(T) – 1 V SLOPE COMPENSATION CIRCUIT RAMP COMP Voltage 51 µA 15 mV 120 140 mV Input Bias Current –0.3 –3 µA Propagation Delay 150 IOUT (ISENSE A or ISENSE B) IRAMP COMP = 100µA (Note 3) 45 Input Offset Voltage Output Off –15 Hysteresis Output On 100 48 OVP COMPARATOR ns ISENSE COMPARATORS Input Common Mode Range Input Offset Voltage –0.2 5.5 V ISENSE A –15 15 mV ISENSE B 0.4 0.7 0.9 V –3 –10 µA 0 3 µA Input Bias Current Input Offset Current –3 Propagation Delay ILIMIT (A) Trip Point 150 VOVP = 5.5V ns 4.8 5 5.2 V .95 1.0 1.05 V Input Bias Current –2 –10 µA Propagation Delay 150 ILIM COMPARATOR ILIMIT Trip Point ns OUTPUT DRIVERS Output Voltage Low Output Voltage High IOUT = –20mA 0.1 0.4 V IOUT = –200mA 1.6 2.2 V IOUT = 20mA 13 13.5 V IOUT = 200mA 12 13.4 V Output Voltage Low in UVLO IOUT = –1mA, VCC = 8V 0.1 Output Rise/Fall Time CL = 1000pF 50 4 0.8 V ns REV. 1.0 10/10/2000 ML4819 ELECTRICAL CHARACTERISTICS (Continued) PARAMETER CONDITIONS MIN TYP MAX UNITS Start-Up Threshold 15 16 17 V Shut-Down Threshold 9 10 11 V UNDER-VOLTAGE LOCKOUT VREF Good Threshold 4.4 V SUPPLY Supply Current Note 1: Note 2: Note 3: Start-Up, VCC = 14V 0.6 1.2 mA Operating, TJ = 25°C 25 35 mA Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. VCC is raised above the Start-Up Threshold first to activate the IC, then returned to 15V. PWM comparator bias currents are subtracted from this reading. FUNCTIONAL DESCRIPTION OSCILLATOR The ML4819 oscillator charges the external capacitor (CT) with a current (ISET) equal to 5/RSET. When the capacitor voltage reaches the upper threshold, the comparator changes state and the capacitor discharges to the lower threshold through Q1. While the capacitor is discharging, the clock provides a high pulse. +5V DUTY CYCLE 7 + 5V VREF 10 RT ISET The oscillator period can be described by the following relationship: 20 tOSC = tRAMP + tDEADTIME + CT CLOCK – TO PWM LATCHES 8.4mA where: t RAMP = TO PWM LATCH B – ISET C(Ramp Valley to Peak) ISET Q1 and: t DEADTIME = C(Ramp Valley to Peak) 8.4mA - ISET The maximum duty cycle of the PWM section can be limited by setting a threshold on pin 7. when the CT ramp is above the threshold at pin 7, the PWM output is held off and the PWM flip-flop is set: DLIMIT D × (VPIN7 - 0.9) ≅ OSC 3.4 CLOCK tD RAMP PEAK CT RAMP VALLEY where: DLIMIT = Desired duty cycle limit DOSC = Oscillator duty cycle REV. 1.0 10/10/2000 Figure 1. Oscillator Block Diagram 5 VCC = 15V TA = 25 C 10 0p RT, TIMING RESISTOR (kΩ) 30 20 F 90% 0p 20 50 0p 1n F 10 F F 85% 2n F 8 5n 5 F 10 nF 100 0 80 GAIN 60 30 50 100 200 300 40 90 PHASE 20 120 0 150 –20 100 1.0k 500 fOSC, OSCILLATOR FREQUENCY (kHz) MAX DUTY CYCLE –30 60 10 3 20 VCC = 15V VO = 1.0V TO 5.0V RL = 100kΩ TA= 25 C 10k 100k f, FREQUENCY (Hz) 1.0M φ, EXCESS PHASE (DEGREES) 95% 50 AVOL, OPEN-LOOP VOLTAGE GAIN (dB) ML4819 180 10M Figure 5. Error Amplifier Open-Loop Gain and Phase vs Frequency Figure 2. Oscillator Timing Resistance vs. Frequency GAIN MODULATOR VSAT, OUTPUT SATURATION VOLTAGE (V) 0 SOURCE SATURATION (LOAD TO GROUND) VCC –1.0 –2.0 VCC = 15V 80µs PULSED LOAD 120 Hz RATE TA = 25 C The output of the gain modulator is a current of the form: 3.0 TA = 25 C 2.0 IOUT is proportional to ISINE × IEA SINK SATURATION (LOAD TO VCC) 1.0 GND 0 The ML4819 gain modulator is a linear current input multiplier to provide high immunity to the disturbances caused by high power switching. The rectified line input sine wave is converted to a current via a dropping resistor. In this way, small amounts of ground noise produce an insignificant effect on the reference to the PWM comparator. 0 200 400 600 800 IO, OUTPUT LOAD CURRENT (mA) Figure 3. Output Saturation Voltage vs. Output Current ERROR AMPLIFIER The ML4819 error amplifier is a high open loop gain, wide bandwidth amplifier. +5V where ISINE is the current in the dropping resistor, and IEA is a current proportional to the output of the error amplifier. When the error amplifier is saturated high, the output of the gain modulator is approximately equal to the ISINE input current. The gain modulator output current is converted into the reference voltage for the PWM comparator through a resistor to ground on the gain modulator output. The gain modulator output is clamped to 5V to provide current limiting. +8V ISINE + 6 IERR ERROR VOLTAGE 0.5mA 9V 4 3 INV 6 ISINE IERR – EA OUT Figure 4. Error Amplifier Configuration GAIN MODULATOR 3 MULTIPLIER Figure 6. Gain Modulator Block Diagram REV. 1.0 10/10/2000 ML4819 SLOPE COMPENSATION Slope compensation is accomplished by adding 1/2 of the current flowing out of pin 12 to pin 1 (for the PFC section and pin 9 (for the PWM section). The amount of slope compensation is equal to (IRAMP COMP/2) × RL where RL is the impedance to GND on pin 1 or pin 9. Since most of the PWM applications will be limited to 50% duty cycle, slope compensation should not be needed for the PWM section. This can be defeated by using a low impedance load to the current sense on pin 9. ENABLE VREF VREF GEN. 5V VREF 9V INTERNAL BIAS – VCC + 20 OSC Figure 9. Under-Voltage Lockout Block Diagram CT VREF IR(SC) 9V 40 IR(SC) 2 TO PIN 9 Q1 RAMP COMP 12 ICC, SUPPLY CURRENT (mA) 10 RT TO PIN 1 IR(SC) 2 RSC SLOPE COMPENSATION Figure 7. Slope Compensation Circuit 20 10 TA = 25 C 4.5V 0 400 4.0V 3.5V 300 3.0V 200 2.5V 100 2.0V E/A OUTPUT VOLTAGE (V) MULTIPLIER OUTPUT CURRENT (µA) 500 30 0 10 20 VCC, SUPPLY VOLTAGE (V) 30 40 Figure 10a. Total Supply Current vs. Supply Voltage 1. 5V 0 0 100 200 300 SINE INPUT CURRENT (µA) 400 35 500 30 UNDER VOLTAGE LOCKOUT On power-up the ML4819 remains in the UVLO condition; output low and quiescent current low. The IC becomes operational when VCC reaches 16V. When VCC drops below 10V, the UVLO condition is imposed. During the UVLO condition, the 5V VREF pin is “off”, making it usable as a status flag. ICC — SUPPLY CURRENT Figure 8. Gain Modulator Linearity 25 OPERATING CURRENT 20 15 10 5 START-UP 0 0 10 20 30 40 50 60 70 TEMPERATURE ( C) Figure 10b. Supply Current (ICC) vs. Temperature REV. 1.0 10/10/2000 7 ∆VREF, REFERENCE VOLTAGE CHANGE (mV) ML4819 Where DON is the duty cycle [TON/(TON + TOFF)]. The input boost inductor will dry out when the following condition is satisfied: 0 VCC = 15V –4.0 [ (2) VINDRY = 1− DON(MAX) × VOUT (3) or –12 [ –16 –20 –24 0 20 40 60 80 100 120 Figure 11. Reference Load Regulation Effectively, the above relationship shows that the resetting volt-seconds are more than setting volt-seconds. In energy transfer terms this means that less energy is stored in the inductor during the ON time than it is asked to deliver during the OFF time. The net result is that the inductor dries out. The recommended maximum duty cycle is 95% at 100KHz to allow time for the input inductor to dump its energy to the output capacitors. APPLICATIONS For example: POWER FACTOR SECTION The power factor section in the ML4819 is similar to the power factor section in the ML4812 with the exception of the operation of the slope compensation circuit. Please refer to the ML4812 data sheet for more information. The following calculations refer to Figure 12 in this data sheet. The component designators in the equations below refer to the following components in Figure 12: RT = R16, CT = C6. INPUT INDUCTOR (L1) SELECTION The central component in the regulator is the input boost inductor. The value of this inductor controls various critical operational aspects of the regulator. If the value is too low, the input current distortion will be high and will result in low power factor and increased noise at the input. This will require more input filtering. In addition, when the value of the inductor is low the inductor dries out (runs out of current) at low currents. Thus the power factor will decrease at lower power levels and/or higher line voltages. If the inductor value is too high, then for a given operating current the required size of the inductor core will be large and/or the required number of turns will be high. So a balance must be reached between distortion and core size. One more condition where the inductor can dry out is analyzed below where it is shown to be maximum duty cycle dependent. if: VOUT = 380V and DON(MAX) = 0.95 then substituting in (3) yields VINDRY = 20V. The effect of drying out is an increase in distortion at low input voltages. For a given output power, the instantaneous value of the input current is a function of the input sinusoidal voltage waveform. As the input voltage sweeps from zero volts to its maximum value and back, so does the current. The load of the power factor regulator is usually a switching power supply which is essentially a constant power load. As a result, an increase in the input voltage will be offset by a decrease in the input current. By combining the ideas set forth above, some ground rules can be obtained for the selection and design of the input inductor: Step 1: Find minimum operating current. IIN(MIN)PEAK = 1.414 × PIN(MIN) VIN(MAX) (4) VIN(MAX) = 260V PIN(MIN) = 50W then: IIN(MIN)PEAK = 0.272A For the boost converter at steady state: VIN VOUT = 1− DON ] VINDRY: Voltage where the inductor dries out. VOUT: Output dc voltage. TA = 25 C IREF, REFERENCE SOURCE CURRENT (mA) 8 ] VIN(t) < VOUT × 1− DON(MAX) –8.0 (1) Step 2: Choose a minimum current at which point the inductor current will be on the verge of drying out. For this example 40% of the peak current found in step 1 was chosen. REV. 1.0 10/10/2000 REV. 1.0 10/10/2000 R14 4.7kΩ R13 4.7kΩ VREF VREF R4 C7 12kΩ 10µF 35V R1 330kΩ R15 4.3kΩ C12 1µF R3 5.6kΩ D8 3V Q4 2N2222 VREF PFC ENHANCEMENT R9 27kΩ R6 4.75kΩ R5 357kΩ R2 510kΩ C8 1 R8 4.53kΩ R7 357kΩ C1 0.6µF R10 33kΩ CT 20 R16 15kΩ ILIM 11 RAMP COMP 12 9 ISENSE B 10 RT PGND B 13 OUT B 14 VCC 15 OUT A 16 PGND A 17 VREF 18 GND 19 8 PWM B 7 DUTY CYCLE 6 ISINE 5 INV A 4 EA OUT A – PGND UI ML4819 3 GM OUT 2 OVP 1 ISENSE A B+ 380V F1 D1 - D4 + 1N5406 0.1µF VREF R11 91Ω VCC T2 PWM REGULATOR D13 D14 65kΩ R18 C13 1µF R17, 3Ω C9 C6 1000pF C5 1000pF VREF IN R22 10Ω C11 1µF C14 2200pF R21 3kΩ R20 7.5Ω D12 MUR150 C11 1µF R25 1Ω R24 1Ω C4 6800pF Q1 IRF840 T1 D6 MUR850 1N5406 D5 R23, 100Ω D11 MUR150 D10 1N4148 R19, 3kΩ NP L1 OUT R12 10Ω D7 1N4148 STARTUP CIRCUIT Q3 IRF840 T3 Q3 IRF840 MOC 8102 U3 TL431 U2 2.26kΩ R29 0.1µF C20 R26 1.5kΩ R27 1.2kΩ C16 1µF D9 MUR110 C2 330µF 400VDC T3 C19 4.7µF D13 D83 –004 C3 0.62µF R28 8.66kΩ C18 1500µF C10 330µF 25VDC + B+ 380 VDC POWER FACTOR CORRECTION VOUT– VIN+ +12V ML4819 Figure 12. Typical Application, 180W Power Factor Corrected 12V Output Power Supply 9 ML4819 then: CURRENT SENSE AND SLOPE (RAMP) COMPENSATION COMPONENT SELECTION ILDRY = 100mA Step 3: The value of the inductance can now be found using previously calculated data. L1 = = VINDRY × DON(MAX) IL(DRY) × fOSC 20V × 0.95 = 2mH 100mA × 100kHz (5) The inductor can be allowed to decrease in value when the current sweeps from minimum to maximum value. This allows the use of smaller core sizes. The only requirement is that the ramp compensation must be adequate for the lower inductance value of the core so that there is adequate compensation at high current. Step 4: The presence of the ramp compensation will change the dry out point, but the value found above can be considered a good starting point. Based on the amount of power factor correction the value of L1 can be optimized after a few iterations. Gapped Ferrites, Molypermalloy, and Powdered Iron cores are typical choices for core material. The core material selected should have a high saturation point and acceptable losses at the operating frequency. One ferrite core that is suitable at around 200W is the #4229PL00-3C8 made by Ferroxcube. This ungapped core will require a total gap of 0.180" for this application. OSCILLATOR COMPONENT SELECTION The oscillator timing components can be calculated by using the following expression: fOSC = 1.36 R T × CT (6) Slope compensation in the ML4819 is provided internally. A current equal to VCT/2(R18) is added to ISENSE A (pin 1). this is converted to a voltage by R10, adding slope to the sensed current through T1. The amount of slope compensation should be at least 50% of the downslope of the inductor current during the off time as reflected on pin 1. Note that slope compensation is a requirement only if the inductor current is continuous and the duty cycle is more than 50%. The highest inductor downslope is found at the point of inductor discontinuity: diL VB − VIN DRY 380V − 20V = = = 0.18 A / µs 2mH dt L The downslope as reflected to the input of the PWM comparator is given by: SPWM = VB − VIN DRY t ×I CT = OFF DIS = 1000pF VOSC (7) 1.36 = 1.36 fOSC × CT 100kHz × 1000pF = 13.6kΩ. Choose R T = 14kΩ. 10 R11 NC (10) Current-sensing MOSFETs or resistive sensing can also be used to sense the switch current. In these cases, the sensed signal has to be amplified to the proper level before it is applied to the ML4819. The value of the ramp compensation (SCPWM) as seen at pin 1 is: SCPWM = 2.5 × R 9 R16 × C6 × R18 (11) The required value for R18 can therefore be found by equating: SCPWM = ASC × SPWM Step 2: Calculate the required value of the timing resistor. RT = L1 × Where NC is the turns ratio of the current transformer (T1) used. In general, current transformers simplify the sensing of switch currents, especially at high power levels where the use of sense resistors is complicated by the amount of power they have to dissipate. Normally the primary side of the transformer consists of a single turn and the secondary consists of several turns of either enameled magnet wire or insulated wire. The diameter of the ferrite core used in this example is 0.5" (SPANG/Magnetics F41206-TC). The rectifying diode at the output of the current transformer can be a 1N4148 for secondary currents up to 75mA average. For example: Step 1: At 100kHz with 95% duty cycle TOFF = 500ns calculate CT using the following formula: (9) where ASC is the amount of slope compensation and solving for R18. (8) REV. 1.0 10/10/2000 ML4819 The value of R9 (pin 3) depends on the selection of R2 (pin 6). R2 = R9 > VIN(MAX) PEAK ISINE (PEAK) = 260 × 1.414 = 510kΩ 0.72mA VCLAMP × R2 4.8 × 510kΩ = = 22kΩ VIN(MIN) PEAK 80 × 1.414 (12) (13) Choose R9 = 27kΩ The peak of the inductor current can be found approximately by: ILPEAK = 1.414 × POUT 1.414 × 200 = = 3.14A VIN (MIN) RMS 90 VCLAMP × NC 4.9 × 80 = = 100Ω ILPEAK 4 2 (15) Having calculated R11 the value SPWM and of R18 can now be calculated: SPWM = 380V − 20 × 100 = 0.225V / µs 2mH 80 R18 = (17) Choose two 178kΩ, 1% connected in series. (14) Where R11 is the sense resistor, and VCLAMP is the current clamp at the inverting input of the PWM comparator. This clamp is internally set to 5V. In actual application it is a good idea to assume a value less than 5V to avoid unwanted current limiting action due to component tolerances. In this application VCLAMP was chosen as 4.8V. R18 = The values of the voltage regulation loop components are calculated based on the operating output voltage. Note that voltage safety regulations require the use of sense resistors that have adequate voltage rating. As a rule of thumb if 1/4W through-hole resistors are used, two of them should be put in series. The input bias current of the error amplifier is approximately 0.5µA, therefore the current available from the voltage sense resistors should be significantly higher than this value. Since two 1/4W resistors have to be used the total power rating is 1/2W. The operating power is set to be 0.4W then with 380V output voltage the value can be calculated as follows: R5 = (380V) / 0.4W = 360kΩ Next select NC, which depends on the maximum switch current. Assume 4A for this example. NC is 80 turns. R11 = VOLTAGE REGULATION COMPONENTS Then R6 can be calculated using the formula below: R6 = VREF × R5 5V × 356kΩ = = 4.747kΩ VB − VREF 380V − 5V (18) Choose 4.75kΩ, 1%. One more critical component in the voltage regulation loop is the feedback capacitor for the error amplifier. The voltage loop bandwidth should be set such that it rejects the 120Hz ripple which is present at the output. If this ripple is not adequately attenuated it will cause distortion on the input current waveform. Typical bandwidths range anywhere from a few Hertz to 15Hz. The main compromise is between transient response and distortion. The feedback capacitor can be calculated using the following formula: C8 = 1 3.142 × R5 × BW C8 = 1 = 0.44µF 3.142 × 356kΩ × 2Hz (19) 2.5 × R 9 ASC × SPWM × R T × CT 2.5 × 28.8k 6 0.7 × (0.225 × 10 ) × 14kΩ × 1nF ≅ 30kΩ (16) Choose R18 = 33kΩ The following values were used in the calculation: R9 = 27kΩ RT = 14kΩ REV. 1.0 10/10/2000 ASC = 0.7 CT = 1nF 11 ML4819 OVERVOLTAGE PROTECTION (OVP) COMPONENTS PWM SECTION The OVP loop should be set so that there is no interaction with the voltage control loop. Typically it should be set to a level where the power components are safe to operate. Ten to fifteen volts above VOUT seems to be adequate. This sets the maximum transient output voltage to about 395V. The PWM section in Figure 12 is a two switch forward converter, shown in Figure 14 below for clarity. This fully clamped circuit eliminates the need for very high voltage MOSFETs. Flyback topology is also possible with the ML4819. By choosing the high voltage side resistor of the OVP circuit the same way as above i.e. R7 = 356K then R8 can be calculated as: R8 = VREF × R7 = 5V × 356kΩ = 4.564kΩ VOVP − VREF 395V − 5V 385VDC Q2 T2 D12 (20) D11 T3 Choose 4.53kΩ, 1%. Note that R5, R6, R7 and R8 should be tight tolerance resistors such as 1% or better. Q3 ML4819 T2 OFF-LINE START-UP AND BIAS SUPPLY GENERATION The Start-Up circuit in Figure 12 can be either a “bleed resistor” (39kΩ, 2W) or the circuit shown in Figure 13. The bleed resistor method offers advantage of simplicity and lowest cost, but may yield excessive turn-on delay at low line. When the voltage on pin 15 (VCC) exceeds 16V, the IC starts up. The energy stored on the C21 supplies the IC with running power until the supplemental winding on T3 can provide the power to sustain operation. IN START-UP CIRCUIT R33 2kΩ VREF R30 4.3kΩ R31 510kΩ R32 2kΩ OUT C21 0.1 D16 22V This regulator (Figure 12) uses current mode control. Current is sensed through R24 and filtered for high frequency noise and leading edge transient through T23 and C14. The main regulation loop is through PWM B. The TL431 (U3) in the secondary serves as both the voltage reference and error amplifier. Galvanic isolation is provided by an optocoupler (U2) which provides a current command signal on pin 8. Loop compensation is provided by R29 and C20. The output voltage is set by: R VOUT = 2.5 1+ 29 R28 Q6 IRF821 Q5 2N2222 Figure 14. Two-Switch Forward Converter TO VCC D15 1N4001 Figure 13. Start-Up Circuit (21) The control loop is compensated using standard compensation techniques. Current is limited to a threshold of 2A (1V on R24). The duty cycle is limited in this circuit to below 50% to prevent transformer (T3) core saturation. The maximum duty cycle limit of 45% is set using a threshold of VREF/2 on pin 7. the circuit in Figure 12 can be modified for voltage mode operation by utilizing the slope current which appears on pin 9 as show in figure 15 below. ENHANCEMENT CIRCUIT The power factor enhancement circuit (inside the dotted lines) in Figure 11 is described in Application Note 11. It improves the power factor and lowers the input current harmonics. Note that the circuit meets IEC1000-3-2 specifications (with the enhancement circuit installed) on the harmonics by a large margin while correcting the input power factor to better than 0.99 under most steady state operating conditions. 12 The ramp amplitude appearing on pin 9 will be: VR = I R18 × R(V) 2 (22) where R18 is the slope compensation resistor. Since this circuit operates with a constant input voltage (as supplied by the PFC section) voltage feed-forward is unnecessary. REV. 1.0 10/10/2000 ML4819 VREF OSC SLOPE COMP. CT IRSC C6 20 2 R13 + – DUTY CYCLE ILIM + – 7 11 FROM R23, C14 R14 1V ISENSE B – 9 RV 0.7V + + – PWM B 8 FROM U2, R15 Figure 15. Voltage Mode Configuration CONSTRUCTION AND LAYOUT TIPS High frequency power circuits require special care during breadboard construction and layout. Double sided printed circuit boards with ground plane on one side are highly recommended. All critical switching leads (power FET, output diode, IC output and ground leads, bypass capacitors) should be kept as small as possible. This is to minimize both the transmission and pickup of switching noise. There are two kinds of noise coupling; inductive and capacitive. As the name implies inductive coupling is due to fast changing (high di/dt) circulating switching currents. The main source is the loop formed by Q1, D6, and C3–C4. Therefore this loop should be as small as possible, and the above capacitors should be good, high frequency types. The second form of noise coupling is due to fast changing voltages (high dv/dt). The main source in this case is the drain of the power FET. The radiated noise in this case can be minimized by insulating the drain of the FET from the heatsink and then tying the heatsink to the source of the FET with a high frequency capacitor. The IC has two ground pins named PWR GND and Signal GND. These two pins should be connected together with a very short lead at the printed circuit board exit point. In general grounding is very important and ground loops should be avoided. Star grounding schemes are preferred. REV. 1.0 10/10/2000 13 ML4819 Component Values/Bill of Materials for Figure 12 Reference Reference Description C1, C3 0.6µF, 630V Film (250 VAC) C2 330µF 25V Electrolytic C4 6800pF 1KV Ceramic C5, C6 1000pF C7 10µF 35V C8, C11, C13, C15, C16 1µF Ceramic C9, C20, C21 0.1µF Ceramic C10 1500µF 25V Electrolytic C12, C17 1µF Ceramic C14 2200 pF C18 1500µF 16V Electrolytic C19 4.7µF D1- D5 1N5406 D6 MUR850 D7, D10 1N4148 D8 3V Zener diode or 4 x 1N4148 in series D9 MUR110 D11, D12 MUR150 D13 D83-004K D15 1N4001 D16, D14 1N5818 or 1N5819 F1 5A, 250V, 3AG L1 2mH, 4A IPEAK Core: Ferroxcube 4229-3CB 150 Turns #24 AWG 0.150" gap L2 10µH Core: Spang OF 43019 UG00 8 Turns #15AWG gap 0.05" Description R4 12kΩ R5, R7 357kΩ, 1% R6 4.57kΩ, 1% R8 4.53kΩ, 1% R9 27kΩ R10, R18 33kΩ R11 91Ω R12, R22 10Ω R13, R14 4.7kΩ R15 4.3kΩ R16 15kΩ R17 3Ω R20 7.5Ω R21,R19 3kΩ R23 100Ω R24, R25 1Ω R26 1.5kΩ R27 1.2kΩ R28 8.66kΩ, 1% R29 2.26kΩ, 1% R30 2kΩ, 1W R32, R33 2kΩ T1 Spang F41206-TC or Siemens B64290-K45-X27 or X830 or Ferroxcube 768T188-38 NS = 80, NP = 1 T2 Same core as T1 NS = NP = 15 bifilar T3 Core: Ferroxcube 4229-3C8 Pri. 44 Turns #18 Litz wire Sec. 4 Turns of copper strip Aux. 2 Turns #24 AWG Q1-Q3 IRF840 Q4, Q5 2N2222 Q6 IRF821 U2 MOC8102 R1 330kΩ U3 TL431 R2, R31 510kΩ R3 5.6kΩ 14 REV. 1.0 10/10/2000 ML4819 PHYSICAL DIMENSIONS inches (millimeters) Package: P20 20-Pin PDIP 1.010 - 1.035 (25.65 - 26.29) 20 0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.26) PIN 1 ID 1 0.060 MIN (1.52 MIN) (4 PLACES) 0.055 - 0.065 (1.40 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN) 0.170 MAX (4.32 MAX) 0.125 MIN (3.18 MIN) SEATING PLANE 0.016 - 0.022 (0.40 - 0.56) 0.008 - 0.012 (0.20 - 0.31) 0º - 15º ORDERING INFORMATION PART NUMBER ML4819CP ML4819CS (Obsolete) TEMPERATURE RANGE 0°C to 70°C 0°C to 70°C PACKAGE Molded DIP (P20) Molded SOIC (S20) DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. www.fairchildsemi.com REV. 1.0 10/10/2000 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. © 2000 Fairchild Semiconductor Corporation 15