UNIVERSAL DEMULTIPLEXER/ DECODER FEATURES SY100S370 DESCRIPTION ■ Max. propagation delay of 1200ps ■ IEE min. of –92mA ■ Industry standard 100K ECL levels ■ Extended supply voltage option: VEE = –4.2V to –5.5V ■ Voltage and temperature compensation for improved noise immunity ■ Internal 75KΩ input pull-down resistors ■ 60% faster than National or Signetics ■ Approximately 40% lower power than Fairchild ■ Function and pinout compatible with Fairchild F100K ■ Available in 24-pin CERPACK and 28-pin PLCC packages The SY100S370 is a universal demultiplexer/decoder that can be used as either a dual 1-of-4 decoder or as a single 1-of-8 decoder and is designed for use in highperformance ECL systems. The Mode control (M) input determines the function. In the dual 1-of-4 mode, each 4input group has a pair of active-LOW Enable (E) inputs. The Enable pins are assigned such that in the single 1-of8 mode they can be tied together in pairs to result in two active-LOW Enable inputs. E1a will be tied to E1b and E2a to E2b. The auxiliary inputs (Hn) are used to determine whether the outputs are active-HIGH or active-LOW. The address inputs for the dual 1-of-4 mode are A0a, A 1a, A0b. A2a is unused. In the 1-of-8 mode, the address inputs are A0a, A1a, A2a. The inputs on the device have 75KΩ pull-down resistors. Z1a (Z1) Z2a (Z2) A0a PIN NAMES M A1a VEES A2a PIN CONFIGURATIONS 11 10 9 8 7 6 5 Function Common Polarity Select Input Z0 – Z 7 Single 1-of-8 Data Outputs Zna, Znb Dual 1-of-4 Data Outputs (n = 1...4) VEES VEE Substrate VCCA VCCO for ECL Outputs Hc Hb A0b A1b E1a Hc 19 20 21 22 23 24 25 E1b Z4 – Z7 (Z0b – Z3b) Polarity Select Input Z1b (Z5) Z2b (Z6) 1 24 23 22 21 20 19 18 A2a 2 3 17 16 M A1a 15 14 A0a Z1a (Z1) 13 7 8 9 10 11 12 Z2a (Z2) Z3b (Z7) 4 5 Z0b (Z4) 6 Top View Flatpack F24-1 VCCA Hb E2a Ha Z3a (Z3) Z0a (Z0) Z0 – Z3 (Z0a – Z3a) Polarity Select Input E2a E2b VEE Ha VCC VCC Ha Mode Control Input Z1b (Z5) VCC M Top View PLCC J28-1 Z0a (Z0) Z3a (Z3) VCCA Z2b (Z6) Enable Inputs (n = 1,2) 4 3 2 1 28 27 26 A1b Z3b (Z7) Z0b (Z4) Ena, Enb VEES Address Inputs (n = 0,1,2) 12 13 14 15 16 17 18 Hb A0b Ana, Anb E1a E1b VEE VEES E2b Hc Pin Rev.: G 1 Amendment: /0 Issue Date: July, 1999 SY100S370 Micrel BLOCK DIAGRAM A0a Z2a (Z2) A1a Z0a (Z0) E1a E2a Z1a (Z1) A2a M Z3a (Z3) Z2b (Z6) A0b Z0b (Z4) Z1b (Z5) Z3b (Z7) A1b E1b E2b Ha Hc Hb 2 SY100S370 Micrel TRUTH TABLES(1) Dual 1-of-4 Mode (M = A2a = Hc = LOW) Active HIGH Outputs (Ha and Hb Inputs HIGH) Inputs Active LOW Outputs (Ha and Hb Inputs LOW) E1a,E1b E2a,E2b A1a,A1b A0a,A0b Z0a,Z0b Z1a,Z1b Z2a,Z2b Z3a,Z3b Z0a,Z0b Z1a,Z1b Z2a,Z2b Z3a,Z3b H X L L X H L L X X L L X X L H L L H L L L L H L L L L L L L L H H L H H H H L H H H H H H H H L L L L H H L H L L L L H L L H H H H H L H H L Single 1-of-8 Mode (M = HIGH; A0b = A1b = Ha = Hb = LOW) Inputs Active HIGH Outputs* (Hc Input HIGH) E1 E2 A2a A1a A0a Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z7 H X X H X X X X X X L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L H H L H L H H L L L L H L L L L H L L L L H L L L L L L L L L L L L L L L L L L L L L L L L H H H H L L H H L H L H L L L L L L L L L L L L L L L L H L L L L H L L L L H L L L L H NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care * for Hc = LOW, output states are complemented E1 = E1a and E1b wired; E2 = E2a and E2b wired DC ELECTRICAL CHARACTERISTICS VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND Symbol IIH IEE Parameter Input HIGH Current Hc, A0a, A1a, A2a All Others Power Supply Current Min. Typ. Max. — — — — 310 250 –92 –73 –46 3 Unit Condition µA VIN = VIH (Max.) mA Inputs Open SY100S370 Micrel AC ELECTRICAL CHARACTERISTICS CERPACK VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Unit tPLH tPHL Propagation Delay Ena, Enb to Output 300 1300 300 1300 300 1300 ps tPLH tPHL Propagation Delay Ana, Anb to Output 500 1600 500 1600 500 1600 ps tPLH tPHL Propagation Delay Ha, Hb, Hc to Output 500 1600 500 1600 500 1600 ps tPLH tPHL Propagation Delay M to Output 600 2100 600 2100 600 2100 ps tTLH tTHL Transition Time 20% to 80%, 80% to 20% 300 900 300 900 300 900 ps Condition PLCC VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Unit tPLH tPHL Propagation Delay Ena, Enb to Output 300 1200 300 1200 300 1200 ps tPLH tPHL Propagation Delay Ana, Anb to Output 500 1500 500 1500 500 1500 ps tPLH tPHL Propagation Delay Ha, Hb, Hc to Output 500 1500 500 1500 500 1500 ps tPLH tPHL Propagation Delay M to Output 600 2100 600 2100 600 2100 ps tTLH tTHL Transition Time 20% to 80%, 80% to 20% 300 900 300 900 300 900 ps 4 Condition SY100S370 Micrel TIMING DIAGRAM 0.7 ± 0.1 ns 0.7 ± 0.1 ns –0.95V INPUT 80% 50% 20% –1.69V tPHL tPLH 80% 50% 20% OUTPUT tTLH tTHL Propagation Delay and Transition Times NOTE: VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND PRODUCT ORDERING CODE Ordering Code 5 Package Type Operating Range SY100S370FC F24-1 Commercial SY100S370JC J28-1 Commercial SY100S370JCTR J28-1 Commercial SY100S370 Micrel 24 LEAD CERPACK (F24-1) Rev. 03 6 SY100S370 Micrel 28 LEAD PLCC (J28-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. 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