HEX D-LATCH FEATURES Q1 Q1 Q0 D0 Q0 VEES PIN CONFIGURATIONS D1 11 10 9 8 7 6 5 D2 Ea 12 13 14 15 16 17 Eb 18 D3 VEE BLOCK DIAGRAM VEES MR D1 D0 R D2 24 23 22 21 20 19 18 D1 2 3 17 16 D0 Q0 15 14 Q0 Q1 13 7 8 9 10 11 12 Q1 Q4 4 5 Q4 6 Top View Flatpack F24-1 Q2 Q1 R 1 Q3 R D E Q3 Q2 D E D4 D5 Q5 Q5 Q3 D E Q4 Q2 Q2 D E D2 19 20 21 22 23 24 25 Q4 R Q3 Q3 VCC VCCA D E D3 R Q3 VCC VCC D3 Q5 26 Q2 VCCA Ea MR VEE E Q2 Eb Q5 4 3 2 1 28 27 Q4 D Q5 Q4 D5 Eb Ea MR D4 Top View PLCC J28-1 VEES ■ ■ ■ ■ ■ The SY100S350 offers six high-speed D-Latches with both true and complement outputs, and is performance compatible for use with high-performance ECL systems. When both enable signals (Ea and Eb) are at a logic LOW, the latches are transparent and the input signals( D0–D5) appear at the outputs (Q0–Q5) after a propagation delay. If either or both of the enable signals are at a logic HIGH, then the latches store the last valid data present on its inputs before Ea or Eb went to a logic HIGH. The Master Reset (MR) overrides all other input signals and takes the outputs to a logic LOW state. All inputs have 75KΩ pull-down resistors. Max. transparent propagation delay of 900ps Min. Master Reset and Enable pulse widths of 100ps IEE min. of –98mA Industry standard 100K ECL levels Extended supply voltage option: VEE = –4.2V to –5.5V Voltage and temperature compensation for improved noise immunity Internal 75KΩ input pull-down resistors More than 40% faster than Fairchild Approximately 30% lower power than Fairchild Function and pinout compatible with Fairchild F100K Available in 24-pin CERPACK and 28-pin PLCC packages D5 Q5 ■ DESCRIPTION D4 ■ ■ ■ ■ ■ SY100S350 Q1 Q0 R Q0 Rev.: G 1 Amendment: /0 Issue Date: July, 1999 SY100S350 Micrel PIN NAMES Pin Function D0 — D5 Data Inputs Ea, Eb Common Enable Inputs (Active LOW) MR Asynchronous Master Reset Input Q0 — Q5 Data Outputs Q0 — Q5 Complementary Data Outputs VEES VEE Substrate VCCA VCCO for ECL Outputs TRUTH TABLE(1) Each Latch Inputs Outputs Dn Ea Eb MR Qn Qn Operating Mode H L X X L L X H L L H X L L L L H L Latched(2) Latched(2) L H Latched(2) Latched(2) Latch X X X H L H Asynchronous NOTES: 1. H = HIGH State L = LOW State X = Don't Care 2. Retains data that is present before E positive transition. DC ELECTRICAL CHARACTERISTICS VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND Symbol IIH IEE Parameter Input HIGH Current MR Dn Ea, Eb Power Supply Current Min. Typ. Max. — — — — — — 250 250 250 –98 –78 –49 2 Unit Condition µA VIN = VIH (Max.) mA Inputs Open SY100S350 Micrel AC ELECTRICAL CHARACTERISTICS CERPACK VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Unit tPLH tPHL Propagation Delay Dn to Output 300 1000 300 1000 300 1000 ps tPLH tPHL Propagation Delay Ea, Eb to Output 300 1100 300 1100 300 1100 ps tPLH tPHL Propagation Delay MR to Output 300 1250 300 1250 300 1250 ps tTLH tTHL Transition Time 20% to 80%, 80% to 20% 300 900 300 900 300 900 ps tS Set-up Time, Dn to En 500 — 500 — 500 — ps tH Hold Time, Dn to En 500 — 500 — 500 — ps tr Release Time, MR to En 1000 — 1000 — 1000 — ps tPW (L) Pulse Width, Ea, Eb 1000 — 1000 — 1000 — ps tPW (H) Pulse Width, MR 1000 — 1000 — 1000 — ps Condition PLCC VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Unit tPLH tPHL Propagation Delay Dn to Output 300 900 300 900 300 900 ps tPLH tPHL Propagation Delay Ea, Eb to Output 300 1000 300 1000 300 1000 ps tPLH tPHL Propagation Delay MR to Output 300 1200 300 1200 300 1200 ps tTLH tTHL Transition Time 20% to 80%, 80% to 20% 300 900 300 900 300 900 ps tS Set-up Time, Dn to En 500 — 500 — 500 — ps tH Hold Time, Dn to En 500 — 500 — 500 — ps tr Release Time, MR to En 1000 — 1000 — 1000 — ps tPW (L) Pulse Width, Ea, Eb 1000 — 1000 — 1000 — ps tPW (H) Pulse Width, MR 1000 — 1000 — 1000 — ps 3 Condition SY100S350 Micrel TIMING DIAGRAMS 0.7 ± 0.1 ns –0.95V DATA –1.69V tW(L) –0.95V ENABLE LATCHES TRANSPARENT TRANSPARENT –1.69V tPHL, tPLH tPHL, tPLH tPHL, tPLH 80% 50% 20% OUTPUT tTHL, tTLH Enable Timing NOTE: VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND DATA ENABLE LATCHED TRANSPARENT TRANSPARENT tR RELEASE TIME MR tW(L) tPHL, tPLH tPHL, tPLH OUTPUT Reset Timing 4 tPHL, tPLH SY100S350 Micrel TIMING DIAGRAMS DATA tS th ENABLE Data Set-up and Hold Times NOTES: tS is the minimum time before the transition of the clock that information must be present at the data input. tH is the minimum time after the transition of the clock that information must remain unchanged at the data input. PRODUCT ORDERING CODE 5 Ordering Code Package Type Operating Range SY100S350FC F24-1 Commercial SY100S350JC J28-1 Commercial SY100S350JCTR J28-1 Commercial SY100S350 Micrel 24 LEAD CERPACK (F24-1) Rev. 03 6 SY100S350 Micrel 28 LEAD PLCC (J28-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2000 Micrel Incorporated 7