QUAD MULTIPLEXER/LATCH Micrel, Inc. FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ SY100S355 SY100S355 DESCRIPTION Max. propagation delay of 1100ps Max. enable to output delay of 1400ps IEE min. of –80mA Industry standard 100K ECL levels Extended supply voltage option: VEE = –4.2V to –5.5V Voltage and temperature compensation for improved noise immunity Internal 75KΩ input pull-down resistors 50% faster than Fairchild Function and pinout compatible with Fairchild F100K Available in 24-pin CERPACK and 28-pin PLCC packages The SY100S355 offers four transparent latches with differential outputs and is designed for use in highperformance ECL systems. The Select inputs (S0, S1) select one of the two sources of input data (D0 or D1) to the latch. The Select inputs can also force the outputs to a logic LOW when the latch is in the transparent mode. The latches are in the transparent mode when both Enables (E1, E2) are at a logic LOW state. In the transparent mode, the Select inputs can pass an input logic HIGH from D0 or D1 to the output. If the Select inputs are tied together, then input data from either D0 or D1 is always passed through. A rising edge on either Enable input will latch the outputs with the most recent data at the latch inputs being stored. The Master Reset (MR) input overrides all other inputs and takes the Q outputs to a logic LOW. The inputs on this device have 75KΩ pull-down resistors. BLOCK DIAGRAM S0 S1 D0a D Q Qa D1a E CD Qa D0b D Q Qb D1b E CD Qb D0c D Q Qc D1c E CD Qc D0d D Q Qd D1d E E1 CD Qd E2 MR M9999-032406 [email protected] or (408) 955-1690 Rev.: H 1 Amendment: /0 Issue Date: March 2006 SY100S355 Micrel, Inc. D0a Ordering Information Qa Qa D0b D1a VEES D1b PACKAGE/ORDERING INFORMATION Part Number 11 10 9 8 7 6 5 S0 S1 VEE VEES MR E1 E2 12 13 4 3 14 15 2 1 Top View PLCC J28-1 16 17 28 27 18 26 F24-1 Commercial SY100S355FC Sn-Pb SY100S355FCTR(1) F24-1 Commercial SY100S355FC Sn-Pb SY100S355JC J28-1 Commercial SY100S355JC Sn-Pb J28-1 Commercial SY100S355JC Sn-Pb SY100S355JZ J28-1 Commercial SY100S355JZ with Pb-Free bar-line indicator Matte-Sn SY100S355JZTR(1, 2) J28-1 Commercial SY100S355JZ with Pb-Free bar-line indicator Matte-Sn VCC VCC Qc Qc Qd D1d Qd VEES D0c D1c D0d S0 E1 MR VEE S1 E2 D1b D1c 2 3 17 16 D0b D1a 15 14 D0a Qa Top View Flatpack F24-1 Qa Qb Qb Qc VCC VCCA 13 7 8 9 10 11 12 Qc 6 (2) 1. Tape and Reel. 2. Pb-Free package is recommended for new designs. 24 23 22 21 20 19 18 Qd SY100S355JCTR (1) Notes: 1 4 5 Lead Finish SY100S355FC D0c Qd Package Marking Qb VCCA 28-Pin PLCC (J28-1) D1d Operating Range Qb 19 20 21 22 23 24 25 D0d Package Type 24-Pin Cerpack (F24-1) M9999-032406 [email protected] or (408) 955-1690 2 SY100S355 Micrel, Inc. PIN NAMES TRUTH TABLE(1) Pin Inputs Function E1 – E2 Enable Inputs (Active LOW) S0, S1 Select Inputs MR Master Reset Dna – Dnd Data Inputs Qa – Qd Data Outputs Qa — Qd Complementary Data Outputs VEES VEE Substrate VCCA VCCO for ECL Outputs Outputs MR E1 E2 S1 S0 D1X D0X QX QX H L L L X L L L X L L L X H H L X H H L X H L X X X X H H L H L L H L H L L L L L L L L L L L L L L H H L H L L X X H X L X X H H H L L L L H H L L L L H X L X H H X X L X X L X X L X X H L Latched Latched NOTE: 1. H = High Voltage Level L = Low Voltage Level X = Don't Care DC ELECTRICAL CHARACTERISTICS VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND Symbol IIH IEE Parameter Input HIGH Current S0, S1 E1, E2 Dna, Dnd MR Power Supply Current M9999-032406 [email protected] or (408) 955-1690 Min. Typ. Max. — — — — — — — — 220 350 340 430 –80 –57 –40 3 Unit Condition µA VIN = VIH (Max.) mA Inputs Open SY100S355 Micrel, Inc. AC ELECTRICAL CHARACTERISTICS CERPACK VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Unit tPLH tPHL Propagation Delay Dna – Dnd to Output (Transparent Mode) 300 1200 300 1200 300 1200 ps tPLH tPHL Propagation Delay S0, S1 to Output (Transparent Mode) 300 1500 300 1500 300 1500 ps tPLH tPHL Propagation Delay E1, E2 to Output 300 1500 300 1500 300 1500 ps tPLH tPHL Propagation Delay MR to Output 300 1200 300 1200 300 1200 ps tTLH tTHL Transition Time 20% to 80%, 80% to 20% 300 900 300 900 300 900 ps tS Set-up Time Dna – Dnd S0, S1 MR (Release Time) 700 1200 1000 — — — 700 1200 1000 — — — 700 1200 1000 — — — Hold Time Dna – Dnd S0, S1 400 400 — — 400 400 — — 400 400 — — tPW (L) Pulse Width LOW, E1, E2 1000 — 1000 — 1000 — ps tPW (H) Pulse Width HIGH, MR 1000 — 1000 — 1000 — ps tH Condition ps ps PLCC VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Unit tPLH tPHL Propagation Delay Dna – Dnd to Output (Transparent Mode) 300 1100 300 1100 300 1100 ps tPLH tPHL Propagation Delay S0, S1 to Output (Transparent Mode) 300 1400 300 1400 300 1400 ps tPLH tPHL Propagation Delay E1, E2 to Output 300 1400 300 1400 300 1400 ps tPLH tPHL Propagation Delay MR to Output 300 1100 300 1100 300 1100 ps tTLH tTHL Transition Time 20% to 80%, 80% to 20% 300 900 300 900 300 900 ps tS Set-up Time Dna – Dnd S0, S1 MR (Release Time) 700 1200 1000 — — — 700 1200 1000 — — — 700 1200 1000 — — — Hold Time Dna – Dnd S0, S1 300 300 — — 300 300 — — 300 300 — — tPW (L) Pulse Width LOW, E1, E2 1000 — 1000 — 1000 — ps tPW (H) Pulse Width HIGH, MR 1000 — 1000 — 1000 — ps tH M9999-032406 [email protected] or (408) 955-1690 ps ps 4 Condition SY100S355 Micrel, Inc. TIMING DIAGRAMS 0.7 ± 0.1 ns –0.95V Dna – Dnd S0, S1 –1.69V tpw –0.95V ENABLE TRANSPARENT TRANSPARENT LATCHED –1.69V tPHL, tPLH tPHL, tPLH tPHL, tPLH 80% 50% 20% OUTPUT tTHL, tTLH Enable Timing RESET TIMING DATA LATCHED TRANSPARENT ENABLE TRANSPARENT tR RELEASE TIME RESET/SET tpw tPHL, tPLH tPHL, tPLH OUTPUT Reset Timing M9999-032406 [email protected] or (408) 955-1690 5 tPHL, tPLH SY100S355 Micrel, Inc. TIMING DIAGRAMS –0.95V S0, S1 50% tS –1.69V tH –0.95V DATA 50% tS –1.69 tH –0.95V E1, E2 50% –1.69V Data Set-up and Hold Times Notes: 1. VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND 2. ts is the minimum time before the transition of the clock that information must be present at the data input. 3. tH is the minimum time after the transition of the clock that information must remain unchanged at the data input. M9999-032406 [email protected] or (408) 955-1690 6 SY100S355 Micrel, Inc. 24-PIN CERPACK (F24-1) Rev. 03 M9999-032406 [email protected] or (408) 955-1690 7 SY100S355 Micrel, Inc. 28-PIN PLCC (J28-1) Rev. 03 MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB USA http://www.micrel.com The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2006 Micrel, Incorporated. M9999-032406 [email protected] or (408) 955-1690 8