6-BIT D LATCH DESCRIPTION FEATURES ■ 700ps max. propagation delay ■ Extended 100E VEE range of –4.2V to –5.5V The SY10/100E150 are 6-bit D latches with differential outputs designed for use in new, high- performance ECL systems. When both Latch Enables (LEN1, LEN2) are at a logic LOW, the latch is in the transparent mode and input data propagates through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the input data. The Master Reset (MR) overrides all other signals to set the Q outputs to a logic LOW. ■ Differential outputs ■ Fully compatible with industry standard 10KH, 100K ECL levels ■ Internal 75KΩ input pulldown resistors ■ Fully compatible with Motorola MC10E/100E150 ■ Available in 28-pin PLCC package BLOCK DIAGRAM R Q0 VCCO Q5 Q5 D LEN1 NC PIN CONFIGURATION MR LEN2 D0 SY10E150 SY100E150 Q0 25 24 23 22 21 20 19 R D3 D R D5 Q4 Q1 D4 D3 VEE D2 27 17 15 Q4 VCC Q3 14 Q3 Q2 Q2 Q2 Q2 Q3 D R D4 18 D R 28 16 PLCC TOP VIEW J28-1 1 2 D1 3 13 D0 4 12 5 6 7 8 Q3 Q4 9 10 11 VCCO D 26 Q0 Q1 Q1 D2 D5 Q0 R Q1 VCCO D NC D1 Q4 Q5 Q5 LEN1 LEN2 PIN NAMES MR Pin Function D0–D5 Data Inputs LEN1, LEN2 Latch Enables MR Master Reset Q0–Q5 True Outputs Q0–Q5 Inverting Outputs VCCO VCC to Output Rev.: D 1 Amendment: /0 Issue Date: November, 1998 SY10E150 SY100E150 Micrel TRUTH TABLE(1) (Each Latch) INPUTS OUTPUTS Operating Dn LEN1 LEN2 MR Qn Qn Mode H L L L H L Latch L L L L L H Latched(2) X X H L Latched(2) X H X L Latched(2) Latched(2) X X X H L H Asynchronous NOTES: 1. H = HIGH state L = LOW state X = Don’t care 2. Retains Data that is present before the LEN positive transition. DC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0°C Symbol IIH IEE Parameter TA = +25°C Min. Typ. Max. Min. Typ. Input HIGH Current D LEN MR TA = +85°C Max. Min. Typ. Max. — — — — 200 150 — — — — 200 150 — — — — 200 150 — — 52 52 62 62 — — 52 52 62 62 — — 52 60 62 72 Power Supply Current 10E 100E 2 Unit Condition µA — mA — SY10E150 SY100E150 Micrel AC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. 375 500 625 550 700 750 250 375 450 550 700 750 Unit Condition ps — tPLH tPHL Propagation Delay to Output D LEN MR 250 375 450 tS Set-up Time, D 200 50 — 200 50 — 200 50 — ps — tH Hold Time, D 200 –50 — 200 –50 — 200 –50 — ps — tRR Reset Recovery Time 750 650 — 750 650 — 750 650 — ps — tPW Minimum Pulse Width, MR 400 — — 400 — — 400 — — ps — tskew Within-Device Skew — 50 — — 50 — — 50 — ps 1 tr tf Rise/Fall Time 20% to 80% 300 450 650 300 450 650 300 450 650 ps — 375 500 625 550 700 750 250 375 450 NOTE: 1. Within-device skew is defined as identical transitions on similar paths through a device. PRODUCT ORDERING CODE Ordering Code Package Type Operating Range SY10E150JC J28-1 Commercial SY10E150JCTR J28-1 Commercial SY100E150JC J28-1 Commercial SY100E150JCTR J28-1 Commercial 3 375 500 625 SY10E150 SY100E150 Micrel 28 LEAD PLCC (J28-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2000 Micrel Incorporated 4