FAIRCHILD FAN6921MR

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AN-6920MR
Integrated Critical-Mode PFC / Quasi-Resonant
Current-Mode PWM Controller FAN6920
1. Introduction
This application note presents practical step-by-step design
considerations for a power supply system employing
Fairchild’s FAN6920 PFC / PWM combination controller,
an integrated Boundary Conduction Mode (BCM) Power
Factor Correction (PFC) controller and Quasi-Resonant
(QR) PWM controller. Figure 1 shows the typical
application circuit, where the BCM PFC converter is in the
front end and the dual-switch quasi-resonant flyback
converter is in the back end.
FAN6920 achieves high efficiency with relatively low cost
for 75~200W applications where BCM and QR operation
with a two-switch flyback provides best performance. A
BCM boost PFC converter can achieve better efficiency
with lower cost than continuous conduction mode (CCM)
boost PFC converter. These benefits result from the
elimination of the reverse-recovery losses of the boost diode
and zero-voltage switching (ZVS) or near ZVS (also called
valley switching) of boost switch. The dual-switch QR
flyback converter for the DC/DC conversion achieves
higher efficiency than the conventional flyback converter
with leakage inductor energy recycles.
The FAN7382, a monolithic high- and low-side gate-driver
IC, can drive MOSFETs that operate up to +600V.
Efficiency can be further improved by using synchronous
rectification in the secondary side instead of a conventional
rectifier diode.
Figure 1. Typical Application Circuit
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • March 10, 2011
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AN-6920
APPLICATION NOTE
source. This behavior makes the boost converter in BCM
operation an ideal candidate for power factor correction.
2. Operation Principles of BCM
Boost PFC Converters
A by-product of the BCM is that the boost converter runs
with variable switching frequency that depends primarily on
the selected output voltage, the instantaneous value of the
input voltage, the boost inductor value, and the output
power delivered to the load. The operating frequency
changes as the input current follows the sinusoidal input
voltage waveform, as shown in Figure 3. The lowest
frequency occurs at the peak of sinusoidal line voltage.
The most widely used operation modes for the boost
converter are continuous conduction mode (CCM) and
boundary conduction mode (BCM). These refer to the
current flowing through the energy storage inductor of the
boost converter, as depicted in Figure 2. As the names
indicate, the inductor current in CCM is continuous; while
in BCM, the new switching period is initiated when the
inductor current returns to zero, which is at the boundary of
continuous conduction and discontinuous conduction
operations. Even though the BCM operation has higher
RMS current in the inductor and switching devices, it allows
better switching condition for the MOSFET and the diode.
As shown in Figure 2, the diode reverse recovery is
eliminated and a fast silicon carbide (SiC) diode is not
needed. MOSFET is also turned on with zero current, which
reduces switching loss.
Figure 3. Operation Waveforms of BCM PFC
The voltage-second balance equation for the inductor is:
VIN (t ) ⋅ tON = (VO.PFC − VIN (t )) ⋅ tOFF
(1)
where VIN(t) is the rectified line voltage.
The switching frequency of BCM boost PFC converter is
obtained as:
f SW =
=
1
1 VO. PFC − VIN (t )
=
⋅
tON + tOFF tON
VOUT
1 VO.PFC − VIN , PK ⋅ | sin(2π f LINE t ) |
⋅
tON
VO.PFC
(2)
where VIN,PK is the amplitude of the line voltage and fLINE is
the line frequency.
Figure 2. CCM vs. BCM Control
Figure 4 shows how the MOSFET on time and switching
frequency change as output power decreases. When the load
decreases, as shown in the right side of Figure 4, the peak
inductor current diminishes with reduced MOSFET on time
and the switching frequency increases.
The fundamental idea of BCM PFC is that the inductor
current starts from zero in each switching period, as shown
in Figure 3. When the power transistor of the boost
converter is turned on for a fixed time, the peak inductor
current is proportional to the input voltage. Since the current
waveform is triangular, the average value in each switching
period is also proportional to the input voltage. In the case
of a sinusoidal input voltage, the input current of the
converter follows the input voltage waveform with a very
high accuracy and draws a sinusoidal input current from the
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • March 10, 2011
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AN-6920
APPLICATION NOTE
3. Operation Principle of DualSwitch Quasi-Resonant Flyback
Converter
Dual-switch QR flyback converter topology derived from a
conventional square wave high/low side pulse-width
modulated (PWM), dual-switch flyback converter have
leakage inductance recycling loop, so that primary-side
snubber can remove, and can recycle the energy of the
leakage inductance stored during switch’s turn-on period.
This is especially suitable for high-power (up to 200W) and
slim-type applications. Figure 6 and Figure 7 show the
simplified circuit diagram of a dual-switch quasi-resonant
flyback converter and its typical waveforms. The basic
operation principles are:
When primary power switches turn on, input voltage
(VIN) is applied across the primary-side inductor (Lm).
MOSFET current (IDS) increases linearly from zero to
the peak value (Ipk). During this time, the energy is
drawn from the input and stored in the inductor.
When the primary power switches turn off, leakage
inductance of the transformer produces a voltage spike
on the PWM switches and causes a drain voltage
increase to the VIN voltage. Clamped to this level, the
leakage inductance energy stored during PWM switches
turning on could be released by diode (D1, D2) and the
voltage on the primary-side winding is clamped to VIN.
Therefore, the energy stored in the inductor forces the
rectifier diode (D3) to turn on. During the diode ON
time (tD), the output voltage (Vo) is applied across the
secondary-side inductor and the diode current (ID)
decreases linearly from the peak value to zero. At the
end of tD, all the energy stored in the inductor has been
delivered to the output. During this period, the output
voltage is reflected to the primary side as Vo × NP/NS.
The sum of input voltage (VIN) and reflected output
voltage (Vo× Np/Ns) is imposed across the MOSFETs.
Figure 4. Frequency Variation of BCM PFC
Since the design of line filter and inductor for a BCM PFC
converter with variable switching frequency should be at
minimum frequency condition, it is worthwhile to examine
how the minimum frequency of BCM PFC converter
changes with operating conditions.
Figure 5 shows the minimum switching frequency, which
occurs at the peak of line voltage, as a function of the RMS
line voltage for different output voltage settings. For
universal line application, the minimum switching
frequency occurs at high line (265VAC) as long as the output
voltage is lower than about 405V.
The voltage on the primary-side winding is clamped to
VIN. If the voltage of input is too low, the voltage of
secondary side could be lower than output voltage
target (VIN < NP/NS×VO), and the output voltage would
follow input voltage drop.
Figure 5. Minimum Switching Frequency vs. RMS Line
Voltage (L = 780µH, POUT = 100W)
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • March 10, 2011
When the inductor current reaches zero, the drain-tosource voltage (VDS) begins to resonate by the
resonance between the primary-side inductor (Lm) and
the MOSFET output capacitor (Coss1, Coss2) with an
amplitude of Vo× Np/Ns on the offset of VIN, as depicted
in Figure 7. Quasi-resonant switching is achieved by
turning on the MOSFET when VDS reaches its
minimum value. This reduces the MOSFET turn-on
switching loss caused by the capacitance loading
between the drain and source of the MOSFET.
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AN-6920
APPLICATION NOTE
and low cost. The bootstrap circuit is useful in a highvoltage gate driver and operates as follows. When the highside VS goes below the IC supply voltage VDD or is pulled
down to ground (the low-side switch is turned on and the
high-side switch is turned off), the bootstrap capacitor,
CBOOT, charges through the transformer primary-side, from
the VDD power supply, as shown in Figure 8. This is
provided by VBS when high-side VS is pulled to a higher
voltage by the high-side switch. The VBS supply floats and
the bootstrap diode reverses bias and blocks the rail voltage
(the low-side switch is turned off and high-side switch is
turned on) from the IC supply voltage, VDD. However, the
dual-switch flyback high-side and low-side MOSFET turn
on and off at the same time. Therefore, once the high-side
MOSFET turns on, high-side VS equals PFC VO, the VDD
can’t charge the CBOOT, even though the high-side VS is
pulled down to ground at leakage energy recycle period, but
the period is too short to charge CBOOT.
Figure 6. Schematic of Dual-Switch Flyback Converter
Ids (MOSFET Drain-to-Source Current)
Figure 8 shows the high-side gate-driver circuit with the
auxiliary power supply. If VCBOOT is less than the HV IC
under-voltage threshold, the high-side gate output (VHO)
maintains turned-off state, then the low-side MOSFET turns
on and charges the CBOOT for one cycle, high-side driver
restarts at the next PWM cycle. Finally, the voltage of
auxiliary power supply follows the output voltage rise and
continues to supply energy to the high-side circuit.
Ipk
ID (Diode Current)
Ipk Np/Ns
Vds
Vo/2 Np/Ns
VIN
VIN /2
Vo/2 Np/Ns
tON
tD
tS
Figure 7. Typical Waveforms of Dual-Switch QR
Flyback Converter
4. High-Side Gate-Drive Circuit
Figure 8 and Figure 9 show the high/low-side gate driver
circuit. The high-side gate drive IC achieves highperformance, is simple and inexpensive, but has a limitation
for dual-switch flyback application.
One of the most widely used methods to supply power to
the high-side gate driver circuitry of the high-voltage gatedrive IC is the bootstrap power supply. This bootstrap
power supply technique has the advantage of being simple
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • March 10, 2011
Figure 8. High-Side Driver Circuit and Start Waveform
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AN-6920
APPLICATION NOTE
Figure 9 shows the high-side driver circuit with standby
power supply. This circuit uses the independent power
supply for HV IC to keep the high-side driver operating.
This circuit is used for applications with standby power, like
the PC power.
The MOSFET conduction time with a given line voltage at a
nominal output power is given as:
tON =
2 ⋅ PO. PFC ⋅ L
η ⋅ VLINE 2
(4)
where:
η is the overall efficiency;
L is the boost inductance; and
POUT is the nominal output power.
Using Equation 4, the minimum switching frequency of
Equation 3 can be expressed as:
f SW , MIN =
η ⋅ VLINE 2
2 ⋅ POUT
VO .PFC − 2VLINE
⋅L
VO. PFC
⋅
(5)
Since the minimum frequency occurs at high line as long as
the PFC output voltage is lower than 405V (as observed in
Figure 5); once the output voltage and minimum switching
frequency are set, the inductor value is given as:
L=
Figure 9. High-Side Driver Circuit with Standby
Power Supply
Line Voltage Range: 90~264VAC (60Hz)
Output of DC/DC Converter: 19V/4.7A (90W)
PFC Output Voltage: 400V
Minimum PFC Switching Frequency: > 50kHz
Brownout Protection Line Voltage: 70VAC
Output Over-Voltage Protection Trip Point: 22.5V
Overall Efficiency: 90%
(PFC Stage: 95%, DC/DC Stage: 95%)
I L. PK =
tON
tON MAX =
(7)
2 ⋅ POUT ⋅ L
< 20 µ s
η ⋅ VLINE .MIN 2
(8)
The number of turns of boost inductor should be determined
considering the core saturation. The minimum number is
given as:
(3)
N BOOST ≥
where:
VLINE is RMS line voltage;
tON is the MOSFET conduction time; and
VO.PFC is the PFC output voltage.
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • March 10, 2011
2 2 ⋅ POUT
η ⋅ VLINE , MIN
Since the maximum on time is internally limited at 20µs, it
should be smaller than 20µs such as:
The boost inductor value is determined by the output power
and the minimum switching frequency. From Equation 2,
the minimum frequency with a given line voltage and
MOSFET on time is obtained as:
VO.PFC − 2VLINE
VO.PFC
(6)
where VLINE,MIN is the minimum line voltage.
[STEP-A1] Boost Inductor Design
⋅
VO . PFC − 2VLINE .MAX
VO. PFC
Once the inductance value is decided, the maximum peak
inductor current at the nominal output power is obtained at
low-line condition as:
Part A. PFC Section
1
⋅
As the minimum frequency decreases, the switching loss is
reduced, while the inductor size and line filter size increase.
Thus, the minimum switching frequency should be
determined by the trade-off between efficiency and the size
of magnetic components. The minimum switching
frequency must be above 20kHz to prevent audible noise.
This design procedure uses the schematic in Figure 1 as a
reference. A 90W PFC application with universal input
range is selected as a design example. The design
specifications are:
f SW , MIN =
2 ⋅ POUT ⋅ f SW , MIN
where VLINE,MAX is the maximum line voltage.
5. Design Considerations
-
η ⋅ (VLINE . MAX ) 2
I L, PK ⋅ L
(9)
Ae ⋅ ∆B
where is Ae is the cross-sectional area of core and ∆B is the
maximum flux swing of the core in Tesla.
∆B should be set below the saturation flux density.
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AN-6920
APPLICATION NOTE
(Design Example) Since the output voltage is 400V, the
minimum frequency occurs at high-line (264VAC) and fullload condition. Assuming the overall efficiency is 90% and
selecting the minimum frequency as 50kHz, the inductor
value is obtained as:
η ⋅ VLINE ,MAX 2 VO. PFC. H − 2 ⋅ VLINE ,MAX
L=
=
2 ⋅ POUT ⋅ f SW ,MIN
⋅
VO. PFC
0.9 ⋅ 2642
400 − 2 ⋅ 264
⋅
= 464µH
2 ⋅ 90 ⋅ 50 × 103
400
The inductance of boot inductor is determined as
450µH.
The maximum peak inductor current at nominal output
power is calculated as:
I L, PK =
tON
MAX
=
2 2 ⋅ POUT
2 2 ⋅ 90
=
= 3.14 A
η ⋅VLINE , MIN
0.9 ⋅ 90
2 ⋅ POUT ⋅ L
η ⋅ VLINE. MIN 2
= 11.1µs < 20µs
=
2 ⋅ 90 ⋅ 450 × 10
0.9 ⋅ 902
Figure 10. Internal Block for ZCD
−6
Assuming QP2512 core (3C96, Ae=110mm2) is used and
setting ∆B as 0.30T, the primary winding should be:
N BOOST ≥
I L ,PK ⋅ L
Ae ⋅ ∆B
=
3.14 × 450 × 10−6
= 42.82turns
110 × 10−6 × 0.30
N ZCD
(VO.PFC − VIN )
N BOOST
Thus, the number of turns (NBOOST) of boost inductor is
determined as 44.
N ZCD
VIN
N BOOST
[STEP-A2] Auxiliary Winding Design
Figure 11 shows the internal block for zero-current
detection (ZCD) for the PFC. FAN6920 indirectly detects
the inductor zero current instant using an auxiliary winding
of the boost inductor.
The auxiliary winding should be designed such that the
voltage of the ZCD pin rises above 2.1V when the boost
switch is turned off to trigger internal comparator as:
N ZCD
(VO. PFC . H − 2VLINE .MAX ) > 2.1V
N BOOST
Figure 11. ZCD Waveforms
(10)
(Design Example) The number of turns for the auxiliary
where VO.PFC.H is the PFC output voltage for high line
condition.
ZCD winding is obtained as:
The ZCD pin has upper and lower voltage clamping at 10V
and 0.45V, respectively. When ZCD pin voltage is clamped
at 0.45V, the maximum sourcing current is 1.5mA and,
therefore, the resistor RZCD should be designed to limit the
current of the ZCD pin below 1.5mA in the worst case as:
N ZCD >
RZCD >
VIN
N
⋅ AUX =
1.5mA N BOOST
2VLINE .MAX N AUX
⋅
1.5mA
N BOOST
2.1N BOOST
(VO . PFC . H − 2VLINE .MAX )
= 3.5 turns
With a margin, NAUX is determined as 8 turns.
Then RZCD is selected from:
RZCD >
(11)
2VLINE MAX N ZCD
2 ⋅ 264 8
⋅
=
⋅ = 45.248kΩ
1.5mA
N BOOST 1.5 ×10 −3 44
as 47.5kΩ.
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • March 10, 2011
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AN-6920
APPLICATION NOTE
[STEP-A3] Design VIN Sense Circuit
(Design Example) Choosing the margin factor as 35%,
FAN6920 senses the line voltage using the averaging circuit
shown in Figure 12, where the VIN pin is connected to the
AC line through a voltage divider and low-pass filter
capacitor. When VIN drops below 1V, the COMP pin is
clamped at 1.6V to limit the energy delivered to output.
VO.PFC decreases with the INV pin voltage. When the INV
pin voltage drops below 1V, brownout protection is
triggered, stopping gate drive signals of PFC and DC/DC.
This protection is reset when VDD drops below the turn-off
threshold (UVLO threshold). When VDD rises to the turn-on
voltage after dropping below the turn-off threshold,
FAN6920 resumes normal operation (if VIN is above 1.2V).
the sensing resistor is selected as:
[STEP-A6] Design Compensation Network
The feedback loop bandwidth must be lower than 20Hz for
the PFC application. If the bandwidth is higher than 20Hz,
the control loop may try to reduce the 120Hz ripple of the
output voltage and the line current is distorted, decreasing
power factor. A capacitor is connected between COMP and
GND to attenuate the line frequency ripple voltage by 40dB.
If a capacitor is connected between the output of the error
amplifier and the GND, the error amplifier works as an
integrator and the error amplifier compensation capacitor
can be calculated by:
The brownout protection level can be determined as:
VLINE .BO =
RVIN1 + RVIN 2
RVIN 2
2 2
π
⋅
0.82
0.82
=
= 0.19Ω
I L.PK (1 + K MARGIN ) 3.14(1 + 0.35)
RCS1 =
(12)
The minimum line voltage for PFC startup is given as:
VLINE.STR = 1.2 ⋅ VLINE.BO
100 ⋅ g M
2.5
⋅
2π ⋅ 2 f LINE VO.PFC.H
CCOMP >
(13)
(15)
To improve the power factor, CCOMP must be higher than the
calculated value. However, if the value is too high, the
output voltage control loop may become slow.
(Design Example)
CCOMP >
=
100 ⋅ g M
2.5
⋅
2π ⋅ 2 f LINE VO. PFC .H
100 ⋅125 ×10−6 2.5
⋅
= 103nF
2π ⋅ 2 ⋅ 60
400
470nF is selected for better power factor.
Figure 12. VIN Sensing Internal Block
Part B. DC/DC Section
(Design Example) Setting the brownout protection trip point
as 69VAC:
[STEP-B1] Determine the Secondary-Side Rectifier
nom
Voltage (VD )
Figure 13 shows the typical operation waveforms of a dualswitch quasi-resonant flyback converter. When the
MOSFET is turned off, the input voltage (PFC output
voltage), together with the output voltage reflected to the
primary (VRO), is imposed on the MOSFET. When the
MOSFET is turned on, the sum of input voltage reflected to
the secondary side and the output voltage is applied across
the secondary-side rectifier. Thus, the maximum nominal
voltage across the MOSFET (Vdsnom) and diode are given as:
RVIN 1 + RVIN 2
2 2
= VLINE . BO ⋅
= 62
RVIN 2
π
Determining RVIN2 as 154kΩ, RVIN1 is determined as 9.4MΩ.
The line voltage to startup the PFC is obtained as:
VLINE.STR = 1.2 ⋅ VLINE.BO = 83V AC
[STEP-A4] Current Sensing Resistor for PFC
FAN6920 has pulse-by-pulse current limit function. It is
typical to set the pulse-by-current limit level at 20~30%
higher than the maximum inductor current:
0.82
RCS1 =
I L. PK (1 + K MARGIN )
VDS
=
VO. PFC + n(VO + VF ) VO.PFC + VRO
=
2
2
(16)
where:
(14)
n=
where KMARGIN is the margin factor and 0.82V is the pulseby-pulse current limit threshold.
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • March 10, 2011
nom
VD
NP
VRO
=
N S VO + VF
nom
= VO +
VO.PFC
n
(17)
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AN-6920
APPLICATION NOTE
By increasing VRO (i.e. the turns ratio, n), the capacitive
switching loss and conduction loss of the MOSFET are
reduced. This also reduces the voltage stress of the
secondary-side rectifier. VRO should be determined by a
trade-off between the hold-up time and voltage stresses of
the secondary-side rectifier diode.
output capacitor effects the hold-up time. The minimum
PFC output voltage for required hold-up time is obtained as:
VO. PFC
min
≥
2 ⋅ t HOLD ⋅ POUT
2
+ VO. PFC . HLD
η ⋅ C O.PFC
(18)
where:
tHOLD is the required holdup time;
POUT is total nominal output power;
VO.PFC.L is the minimum PFC output voltage for required
hold-up time; and
VO.PFC.HLD is the allowable minimum PFC output voltage
during the hold-up time.
The voltage of transformer primary-side winding is clamped
to VO,PFC, so the minimum PFC output voltage during the
hold-up time is obtained as:
(19)
VO. PFC . HLD = n ⋅ (VO + V F )
where VF is the synchronous rectification MOSFET drainto-source diode forward voltage, VF, about 1V.
(Design Example) Because the PFC response is very slow,
the hold-up time needs to be more than 12ms to avoid PFC
output voltage drop effecting the output voltage at
dynamic-load condition. Assuming hold-up time is 12ms,
the VO.PFCmin as:
VO. PFC
=
Figure 13. Typical Waveforms of QR Flyback Converter
VO.PFC
n
VO. PFC
400
∴n >
=
= 11.94
0.7 ⋅ 75 − VO 0.7 ⋅ 75 − 19
nom
≥
2 ⋅ t HOLD ⋅ POUT
+ [n ⋅ (VO + VF )]2
η ⋅ CO. PFC
2 ⋅ 12 × 10 −3 × 90
+ [12 ⋅ (19 + 1)]2 = 286V
−6
0.9 ⋅ 100 × 10
[STEP-B3] Transformer Design
Figure 14 shows the typical switching timing of a quasiresonant converter. The sum of MOSFET conduction time
(tON), diode conduction time (tD), and drain voltage falling
time (tF) is the switching period (tS). To determine the
primary-side inductance (Lm), the following parameters
should be determined first.
(Design Example) Assuming 75V MOSFET
(synchronous rectification) is used for secondary side,
with 70% voltage margin:
0.7 ⋅ 75 > VD
min
= VO +
Minimum Switching Frequency (fS.QRmin)
The minimum switching frequency occurs at the minimum
input voltage and full-load condition, which should be
higher than 20kHz to avoid audible noise. By increasing
fS.QRmin, the transformer size can be reduced. However, this
results in increased switching losses. Determine fS.QRmin by a
trade-off between switching losses and transformer size.
Typically fS.QRmin is set around 70kHz.
Thus, n is determined as 12.
[STEP-B2] Calculate the Minimum PFC Output
Voltage (VO.PFC.L) for Hold-up Time
For the PFC output capacitor, it is typical to use 0.5~1µF
per 1W output power for 400V PFC output. Meanwhile, it is
reasonable to use ~1µF per 1W output power for variable
output PFC due to the larger voltage drop during the holdup time than 400V output. In this example, two 100µF
capacitors are selected for the output capacitors (CO.PFC).
Falling Time of the MOSFET Drain Voltage (tF)
As shown in Figure 14, the MOSFET drain voltage fall time
is half of the resonant period of the MOSFET’s effective
output capacitance and primary-side inductance. The typical
value for tF is 0.6~1.2µs.
Lower PFC output voltage can improve system efficiency at
low AC line voltage condition, but the energy of the PFC
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • March 10, 2011
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AN-6920
APPLICATION NOTE
Non-Conduction Time of the MOSFET (tOFF)
When designing the transformer, the maximum flux density
swing in normal operation (B) as well as the maximum flux
density in transient (Bmax) should be considered. The
maximum flux density swing in normal operation is related
to the hysteresis loss in the core, while the maximum flux
density in transient is related to the core saturation.
FAN6920 has a minimum non-conduction time of MOSFET
(5µs), during which turning on the MOSFET is prohibited.
To maximize the efficiency, it is necessary to turn on the
MOSFET at the first valley of MOSFET drain-to-source
voltage at heavy-load condition. Therefore, the MOSFET
non-conduction time at heavy load condition should be
larger than 5µs.
The minimum number of turns for the transformer primary
side to avoid over temperature in the core is given by:
After determining fS.QRmin and tF, the maximum duty cycle is
calculated as:
Dmax =
VRO
⋅ (1 − f S .QR min ⋅ t F )
VRO + VO.PFC .L
N P min =
(20)
Lm =
2 ⋅ f S .QR min POUT
If there is no reference data, use B =0.25~0.30T.
Once the minimum number of turns for the primary side is
determined, calculate the proper integer for NS so that the
resulting NP is larger than Npmin as:
(21)
N P = n ⋅ N S > N P min
Once Lm is determined, the maximum peak current and
RMS current of the MOSFET in normal operation are
obtained as:
I DS PK =
VO.PFC .L ⋅ Dmax
Lm f S .QR min
(22)
Dmax
3
(23)
I DS RMS = I DS PK
(1 − Dmax )
f S .QR min
nom
N AUX =
VO.PFC . L VO. PFC .H + VRO
⋅
VO. PFC .H VO.PFC .L + VRO
VDD + VFA
⋅ NS
(VO + VF )
(28)
where VDDnom is the nominal VDD voltage, the range about
12~20V, and the VFA is forward-voltage drop of VDD diode,
about 1V.
Once the number of turns of the primary winding is
determined, the maximum flux density when the drain
current reaches its pulse-by-pulse current limit level should
be checked to guarantee the transformer is not saturated
during transient or fault condition.
(24)
The MOSFET non-conduction time at heavy load and
higher voltage of PFC output (VO.PFC.H) is obtained as:
tOFF . H = tOFF . L ⋅
(27)
The number of turns of the auxiliary winding for VDD is
given as:
The MOSFET non-conduction time at heavy load and low
line is obtained as:
tOFF .L =
(26)
where B is the maximum flux density swing in Tesla.
Then, the primary-side inductance is obtained as:
ηQR ⋅ (VO.PFC .L ⋅ Dmax ) 2
Lm I DS PK
Ae ∆B
The maximum flux density (Bmax) when drain current
reaches ILIM is given as:
(25)
Bmax =
To guarantee the first valley switching at high line and
heavy-load condition, tOFF.H should be larger than 5µs.
Lm I LIM
< Bsat
Ae N P
(29)
Bmax should be smaller than the saturation flux density.
If there is no reference data, use Bsat =0.35~0.40T.
(Design Example) Setting the minimum frequency is
65kHz and the falling time is 1µs, and assuming
VO.PFC.L=300V:
Dmax =
=
VRO
min
⋅ (1 − f S .QR ⋅ t F )
VRO + VO. PFC . L
240
⋅ (1 − 70 × 10 3 ⋅1 × 10 −6 ) = 0.413
240 + 300
Figure 14. Switching Timing of QR Flyback Converter
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • March 10, 2011
www.fairchildsemi.com
9
AN-6920
Lm =
APPLICATION NOTE
[STEP-B3] Design the Valley Detection Circuit
η ⋅ (VO. PFC . L ⋅ Dmax ) 2
2 ⋅ f s.QR
min
⋅ PO
The valley of MOSFET voltage is detected by monitoring
the current flowing out of the DET pin. The typical
application circuit is shown as Figure 15 and typical
waveforms are shown in Figure 16. The DET pin has upper
and lower voltage clamping at 5V and 0.7V, respectively. The
valley detection circuit is blanked for 5µs after the
MOSFET is turned off. When VAUX drops below zero, VDET
is clamped at 0.7V and current flows out of the DET pin.
MOSFET is turned on with 200ns delay once the current
flowing out of DET pin exceeds 30µA. To guarantee that
valley detection circuit is triggered when the DET pin is
clamped at 0.7V, the current flowing through RDET2 should
be larger than 30µA as:
2
=
0.95 ⋅ (300 ⋅ 0.413)
= 1160µH
2 ⋅ 70 × 103 ⋅ 90
I DS
=
PK
=
VO .PFC . L ⋅ Dmax
min
Lm f S .QR
300 ⋅ 0.413
= 1.53 A
1160 × 10 −6 ⋅ 70 × 103
(1 − Dmax ) 1 − 0.413
=
= 8.39µs
min
70 × 103
f S .QR
tOFF . L =
tOFF .H = tOFF .L ⋅
= 8.39 × 10 −6 ⋅
VO .PFC .L VO. PFC . H + VRO
⋅
VO. PFC . H VO. PFC . L + VRO
0.7
> 30µ A
RDET 2
(30)
300 400 + 240
⋅
= 7.46 µs > 5µs
400 300 + 240
Assuming QP2912 (Ae=144mm2) core is used and the flux
swing is 0.28T
PK
NP
min
=
L m I DS
1160 × 10 −6 ⋅ 1.53
=
= 44
Ae ∆B
144 × 10 −6 ⋅ 0.28
N P = n ⋅ N S ⇒ 12 ⋅ 3 = 36 < N P
⇒ 12 ⋅ 4 = 48 > N P
min
min
NP is determined as 48, NS is 4.
12 + VFA
20 + VFA
⋅ N S < N AUX <
⋅ NS
(VO + VF )
(VO + VF )
12 + 1
20 + 1
⋅ 4 < N AUX <
⋅4
20
20
⇒ 2.6 < N AUX < 4.2
⇒
Figure 15. Typical Application Circuit of DET Pin
Thus, NAUX is determined as 3.
The number of turns of the high-side driver auxiliary is
given as:
NAUX.H ≦ NAUX
VO ⋅
NA
NS
− V O . PFC ⋅
NA
NP
NAUX.H is determined as 2.
Assuming the pulse-by-pulse current limit for low PFC
output voltage is 140% of peak drain current at heavy load:
Bmax =
L m I LIM 1160 × 10 −6 ⋅ 2.14
=
= 0.36T
Ae N P
144 × 10 −6 ⋅ 48
VO ⋅
NA
RA
⋅
N S RDET + RA
Figure 16.
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • March 10, 2011
Waveforms of Valley Detection and
VO OVP Detection
www.fairchildsemi.com
10
AN-6920
APPLICATION NOTE
The output is indirectly monitored for over-voltage
protection using the DET pin voltage while the MOSFET is
turned off. The ratio of RDET1 and RDET2 should be
determined as:
2. 5 =
RDET 2
NA
NA
1
VOVP =
VOVP
RDET 1 + RDET 2 N S
K DET + 1 N S
(31)
where the ratio between RDET1 and RDET2 is obtained as:
K DET =
RDET 1 N A VOVP
=
⋅
−1
RDET 2 N S 2.5
(32)
For a quasi-resonant flyback converter, the peak-drain
current with a given output power decreases as input voltage
increases. Thus, constant power limit cannot be achieved by
using pulse-by-pulse current limit with constant threshold.
FAN6920 has high/low line over-power compensation that
reduces the pulse-by-pulse current limit level as input
voltage increases. FAN6920 senses the input voltage using
the current flowing out of the DET pin while the MOSFET
is turned on. The pulse-by-pulse current limit level vs. DET
current is depicted in Figure 18.
Figure 18. IDET-VLIMIT Curve
The relationship between IDET and VLIMIT in the linear region
(IDET=100~500µA) can be approximated as:
The DET pin current for low-line and high-line PFC output
voltages are given as:
VO.PFC . L
I DET .L =
RDET 1
VO. PFC .H
I DET . H =
NA
− 0.7
NP
NA
− 0. 7
NP
RDET 1
+
0.7
≅
RDET 2
0. 7
+
≅
RDET 2
VO.PFC . L
NA
NP
VLIMIT = −877 ⋅ I DET + 0.882
Assuming two-level voltage PFC output: for a given output
power, the ratio between drain-peak currents at low line and
high line is obtained as:
(33)
RDET 1
VO. PFC .H
NA
NP
(35)
I DS PK . L VO . PFC . H VO . PFC . L + VRO
=
⋅
I DS PK . H VO . PFC . L VO . PFC . H + VRO
(34)
RDET 1
(36)
For a given output power, the ratio between pulse-by-pulse
current limit levels at low line and high line is obtained as:
N
−994 ⋅VO. PFC . L A + RDET 1
VLIMIT . L
NP
≅
NA
VLIMIT . H −994 ⋅ V
+ RDET 1
O . PFC . H
NP
(37)
To get a constant power limit, RDET1 should be determined
such that Equations (38) and (39) are equal. However, for
actual design, it is typical to use 108~115% of Equation
(38), considering the pulse-by-pulse turn-off delay and
increased PFC output voltage ripple at low line.
Once the current-limit threshold voltage is determined with
RDET1, the current-sensing resistor value is obtained as:
Figure 17. Switching Frequency and Peak-Drain
Current Change as Input Voltage Increases
VO . PFC . L
VLIMIT = −877 ⋅ (
NA
− 0.7
NP
RDET 1
+
0.7
) + 0.882
RDET 2
(38)
The current-sensing resistor value can be obtained from:
RCS 2 =
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • March 10, 2011
VLIMIT
I DS LIM
(39)
www.fairchildsemi.com
11
AN-6920
APPLICATION NOTE
[STEP-B4] Design the Feedback Circuit
(Design Example)
Figure 19 is a typical feedback circuit mainly consisting of a
shunt regulator and a photo-coupler. R01 and R02 form a
voltage divider for output voltage regulation. RF and CF are
adjusted for control-loop compensation. A small-value RC
filter (e.g. RFB = 100Ω, CFB = 1nF) placed from the FB pin
to GND can increase stability substantially. The maximum
source current of the FB pin is about 1.2mA. The
phototransistor must be capable of sinking this current to
pull the FB level down at no load. The value of the biasing
resistor, RBIAS, is determined as:
0. 7
> 30 µ A , RDET 2 < 23.3k Ω
RDET 2
Setting the OVP trip point at 22.5V,
K DET =
RDET 1 N AUX VOVP
3 22.5
=
⋅
−1 = ⋅
− 1 = 5.75
RDET 2
NS
2.5
4 2.5
Then RDET 1 = K DET ⋅R ⋅ RDET 2 < 134kΩ
PK . L
I DS
V
V
+ VRO
= O. PFC. H ⋅ O. PFC . L
PK . K
VO. PFC. L VO. PFC . H + VRO
I DS
VO − VOPD − VKA
⋅ CTR > 1.2 × 10 −3
RBIAS
400 300 + 240
=
⋅
= 1.125
300 400 + 240
where VOPD is the drop voltage of photodiode, about 1.2V;
VKA is the minimum cathode to anode voltage of shunt
regulator (2.5V); and CTR is the current transfer rate of the
opto-coupler.
Using 113% of 1.125,
− 994 ⋅ VO. PFC .L
VLIMIT . L
= 1.27 =
VLIMIT . H
− 994 ⋅ VO. PFC . H
(40)
NA
+ RDET 1
NP
NA
+ RDET 1
NP
3
+ RDET 1
− 18637.5 + RDET 1
48
=
=
3
− 24850 + RDET 1
− 994 ⋅ 400 ⋅ + RDET 1
48
− 994 ⋅ 300 ⋅
Then, RDET1 = 47.5KΩ and REDT2=8.25KΩ.
RDET1 and RDET2 are selected from the off-the-shelf
components as 150kΩ and 18kΩ, respectively.
Then, the pulse by pulse current limit threshold voltage
is obtained as:
VO. PFC . L
VLIMIT = −877 ⋅ (
NA
− 0.7
NP
RDET 1
+
Figure 19. Feedback Circuit
0.7
) + 0.882
RDET 2
(Design Example) Assuming CTR is 100%;
VO − VOPD − VKA
⋅ CTR > 1.2 × 10−3
RBIAS
= 0.474V
To set current limit level at low line as 115% of IDSPK
0.63
= 0.27Ω
1.53 A × 1.15
RBIAS <
VO − VOPD − VKA 19 − 1.2 − 2.5
=
= 12.75k Ω
1.2 ×10−3
1.2 × 10−3
330Ω resistor is selected for RBIAS.
The voltage divider resistors for VO sensing are selected as
66.5kΩ and 10kΩ.
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • March 10, 2011
www.fairchildsemi.com
12
AN-6920
APPLICATION NOTE
[STEP-B5] Design the Over-Temperature
Protection Circuit
The adjustable Over-Temperature Protection (OTP) circuit
is shown in Figure 20. As can be seen, a constant sourcing
current source (IRT) is connected to the RT pin. Once VRT is
lower than 0.8V for longer than 10ms debounce time,
FAN6920 is latched off. RRT can be determined by:
0.8V = ( RRT + RNTC @ OT ) × 100 µ A
(41)
Figure 20. Adjustable Over-Temperature Protection
and External Latched-off Function
(Design Example) Assuming the resistance of NTC at overtemperature protection point is 4.3kΩ;
RRT =
0.8V
- 4.3kΩ = 3.7kΩ
100µ A
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • March 10, 2011
www.fairchildsemi.com
13
AN-6920
APPLICATION NOTE
Final Schematic of Design Example
Table 2.
This section summaries the final design example. The key
system specifications are summarized in Table 1 and the key
design parameters are summarized in Table 2. The final
schematic is in Figure 21. To have enough hold-up time for
VDD during startup, a two-stage circuit is used for VDD. To
maximize the efficiency, the synchronous rectification using
Fairchild’s FAN6204 is used for the secondary rectifier.
PFC Stage
PFC Inductor (LBOOST)
450µH
Turns of PFC Inductor (NBOOST)
44T
Turns of ZCD Auxiliary Winding (NZCD)
8T
min
Minimum Switching Frequency (fS.PFC )
40kHz
PWM Stage
Turns of Primary Inductor of PWM Transformer (NP)
48T
Turns of Auxiliary Winding of PWM Transformer
4T
(NAUX)
Turns of Auxiliary Winding of High-Side Driver
3T
Transformer (NAUX.H)
Turns Ratio of PWM Transformer (n)
12
Primary Inductor (LP)
1160µH
min
Minimum Switching Frequency (fs.QR )
70kHz
Table 1. System Specifications
Input
Input Voltage Range
Line Frequency Range
90~264VAC
47~63Hz
Output
Output Voltage (Vo)
Output Power (Po)
19V
90W
NBOOST
44T
DPFC
NCZD
8T
CINF2
Q1
RHV
150kΩ
RPFC1
9.4MΩ
DBOOST
CO.PFC
100µF
10Ω
470nF
Key Design Parameters
CBOOT
0.1µF
NAUX.H
3T
DAUX.H
RG1
RPFC3
249kΩ
CINF1
1 RANGE
HV 16
2
NC 15
COMP
3 INV
D2
330nF
RCIN1 RCIN2
1.5MΩ 1.5MΩ
1 VCC
RVIN1
9.4MΩ
RRT
3.7kΩ
VIN 13
5 CSPWM
RT 12
HO 7
3 LIN
VS 6
4 COM
LO 5
Q4
10Ω
RLPC1
220kΩ
DR1
NP
48T
RLPC1
8.8kΩ
Q3
FB 11
7 VDD
DET 10
RG3
8 OPWM
GND 9
10Ω
RES 7
AGND
1 2 6
GND
4
NA
3T
RDET1
47.5kΩ
RDET2
8.25kΩ
RES2
12kΩ
RO1
66.5kΩ
IC4: PC817
DAUX
RES1
47.5kΩ
RBIAS
330Ω
RCS2
0.27Ω
CVIN
2.2µF
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • March 10, 2011
VDD
IC3: FAN6204
RVIN2
154kΩ
Figure 21.
5
8 LPC
NTC
CDD
68µF
3
GATE
FAN6204
DR2
CFB
47nF
VAC
-
RG2
VB 8
2 HIN
CRT
1nF
ZCD 14
4 CSPFC
6 OPFC
VOUT
19V
IC2: FAN7382
IC1: FAN6920
D1
+
Q2
RCZD 47.5kΩ
CCOMP
470nF
COUT2
820µF/25V
RSN CSN
16Ω 2.2nF
RPFC2
78.7kΩ
RCS1
0.2Ω
LOUT
47nH
COUT1
820µF/25V
NS
4T
RF
CF
1.2kΩ 10nF
IC5: KA431
RO2
10kΩ
Final Schematic of Design Example
www.fairchildsemi.com
14
AN-6920
APPLICATION NOTE
Table 3. Bill of Materials
Part
Value
Note
Resistor
RPFC1
R PFC2
R PFC3
RVIN1
RVIN2
RZCD
RHV
RRT
RCS1
RCS2
RG1
RG2
RG3
RDET1
RDET2
RCIN1
RCIN2
RLPC1
RLPC2
RRES1
RRES2
RSN
RO1
RO2
RBIAS
RF
CINF1
CINF2
CVIN
CCOMP
CDD
CRT
9.4MΩ
78.7kΩ
249kΩ
9.4MΩ
154kΩ
47.5kΩ
150kΩ
3.7kΩ
0.2Ω
0.27Ω
10Ω
10Ω
10Ω
47.5kΩ
8.25kΩ
1.5MΩ
1.5MΩ
220kΩ
8.8kΩ
47.5kΩ
12kΩ
16Ω
66.5kΩ
10kΩ
330Ω
1.2kΩ
Capacitor
330nF
470nF
2.2µF
470nF
68µF
1nF
1/4W
1/8W
1/8W
1/4W
1/8W
1/4W
1W
1/8W
2W
2W
1/4W
1/4W
1/4W
1/4W
1/8W
1/4W
1/4W
1/8W
1/8W
1/8W
1/8W
1W
1/8W
1/8W
1/4W
1/8W
Part
Value
CFB
CO.PFC
CSN
CF
COUT1
COUT2
CBOOT
47nF
100µF
2.2nF
10nF
820µF
820µF
0.1µF
Diode
D1
D2
DPFC
DBOOST
DAUX
DAUX.H
DR1
DR2
S1J
S1J
ES3J
ES1H
RS1D
RS1D
ES1H
ES1H
MOSFET
FCB11N60
FCB11N60
FCB11N60
FDB031N08
IC
FAN6921MR
FAN7382
FAN6204
PC817
KA431
Other
TTC104
47nH
Q1
Q2
Q3
Q4
IC1
IC2
IC3
IC4
IC5
XCAP
NTC
LOUT
Note
450V
25V
25V
Ultra-Fast Diode
Fast Diode
Fast Diode
Ultra-Fast Diode
Ultra-Fast Diode
50V
Lab Note
Before modifying or soldering / desoldering the power
supply, discharge the primary capacitors through the
external bleeding resistor. Otherwise, the PWM IC may be
damaged by external high-voltage.
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • March 10, 2011
This device is sensitive to electrostatic discharge (ESD). To
improve the production yield, the production line should be
ESD protected as required by ANSI ESD S1.1, ESD S1.4,
ESD S7.1, ESD STM 12.1, and EOS/ESD S6.1 standards.
www.fairchildsemi.com
15
AN-6920
APPLICATION NOTE
Printed Circuit Board Layout
Printed circuit board layout and design are very important
for switching power supplies where the voltage and current
change with high dv/dt and di/dt. Good PCB layout
minimizes EMI and prevents the power supply from being
disrupted during surge/ESD tests.
IC Side
PWM Stage
Reference ground of the INV, COMP, CSPFC,
CSPWM, and VDD pins are connected together and
then connected to the IC’s GND directly.
Reference ground of ZCD, VIN, RT, FB, and DET pins
are connected to IC’s GND directly.
Small capacitors around the IC should be connected to
the IC directly.
The trace line of CSPWM, OPFC, and OPWM should
not be paralleled and should be close to each other to
avoid introducing noise.
Connections of IC’s GND, RCS.PWM ground, HV IC’s
GND, and auxiliary winding of PWM XFMR:
Approach
Auxiliary winding’s ground IC’s GND RCS.PWM’s ground (214)
HV IC’s GND RCS.PWM’s ground (34)
Y CAP’s primary ground C1’s ground (109)
Approach Ground Loop:
System Side
PFC Stage
RCS.PWM should be connected to CBulk’s ground directly.
Keep it short and wide.
Current loop constructed by the CBulk, XFMR, PWM
MOSFET, clamp diode, and RCS.PWM should be as short
as possible.
Ground of photo-coupler should be connected to IC’s
GND.
On the secondary side, current loop constructed by
XFMR, Schottky, and output capacitor should be as
short as possible.
Connections of Y Capacitor:
Approach
External driver circuit can shorten MOSFET gate
discharge current loop and improve the surge/ESD
capability.
Current loop constructed by the PFC choke, PFC diode,
PFC MOSFET, CBulk, and C2 should be as short as
possible.
Auxiliary winding of PFC choke is connected to IC’s
GND.
RCS.PFC should be connected to C2’s ground singly
(6 & 8).
7&214
34
458
68
8 & 10 9
Figure 22. Layout Considerations
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • March 10, 2011
www.fairchildsemi.com
16
AN-6920
APPLICATION NOTE
Related Documents
FAN6920MR — Highly Integrated Quasi-Resonant Current PWM Controller
FAN6204MY — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification
FAN7382 — High- and Low-Side Gate Driver
AN-6076 — Design and Application Guide of Bootstrap Circuit for High-Voltage Gate –Driver IC
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1.
2.
Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • March 10, 2011
A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
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