PRELIMINARY MITSUBISHI ICs (AV COMMON) Notice. This is not a final specification. Some parametric limits are subject to change. M52795SP/FP AV SWITCH with I2C BUS CONTROL DESCRIPTION The M52795 is AV switch semiconductor integrated circuit with I2C bus control . This IC contains 2-channels of 4-input audio switches and 2channels of 4-input video switches. Each channel can be controled independently . The video switches contain amplifiers can be controled a gain of output 0dB or 6dB . FEATURES •Video and stereo sound switches in one package •Wide frequency range ( video switch )...........DC~20MHz •High separation ( video switch ) ..................Crosstalk -60dB ( typ. ) at 1MHz •Two types of packages are provided : SDIP with a lead pitch of 1.778mm ( M52795SP ) ; and SOP with a lead pitch of 1.27mm ( M52795FP ) . PIN CONFIGURATION ( TOP VIEW ) VCC Lch 2 IN VIDEO 2 IN Rch 2 IN Lch 3 IN VIDEO 3 IN Rch 3 IN Lch 4 IN VIDEO 4 IN Rch 4 IN SCL SDA DC DD 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 D5 D4 Lch T IN TUNER IN Rch T IN Lch 1 OUT V 1 OUT Rch 1 OUT Lch 2 OUT V 2 OUT Rch 2 OUT BIAS CHIP SELECT GND Outline 28P4B (Lead pitch :1.778mm) APPLICATION Video equipment PIN CONFIGURATION ( TOP VIEW ) RECOMMENDED OPERATING CONDITION Supply voltage Rated supply voltage Maximum output current 4.7V~9.3V 5V,9V 32mA(at 9V) VCC Lch 2 IN VIDEO 2 IN Rch 2 IN Lch 3 IN VIDEO 3 IN Rch 3 IN Lch 4 IN VIDEO 4 IN Rch 4 IN SCL SDA DC DD 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 D5 D4 Lch T IN TUNER IN Rch T IN Lch 1 OUT V 1 OUT Rch 1 OUT Lch 2 OUT V 2 OUT Rch 2 OUT BIAS CHIP SELECT GND Outline 28P2W-A (Lead pitch :1.27mm) MITSUBISHI 1-9 AUG.'98 PRELIMINARY MITSUBISHI ICs (AV COMMON) M52795SP/FP Notice. This is not a final specification. Some parametric limits are subject to change. AV SWITCH with I2C BUS CONTROL BLOCK DIAGRAM VCC TUNER IN VIDEO 2 IN VIDEO 3 IN VIDEO 4 IN 1 25 0/6dB 3 22 6 V 1 OUT V-SW1 9 0/6dB 19 V 2 OUT V-SW2 Rch T IN Rch 2 IN Rch 3 IN Rch 4 IN 24 R-MODE1 4 7 0dB R M L R-SW1 21 Rch 1 OUT 10 R-MODE2 R-SW2 Lch T IN Lch 2 IN Lch 3 IN Lch 4 IN 0dB R M L 18 Rch 2 OUT 26 L-MODE1 2 57 L M R L-SW1 0dB 23 Lch 1 OUT 8 L-MODE2 0dB L M R L-SW2 20 BIAS 17 2 Lch 2 OUT 12 SDA 11 SCL I C Control BIAS 15 13 14 27 28 GND 16 CHIP SELECT DC DD MITSUBISHI D4 D5 2-9 AUG.'98 PRELIMINARY MITSUBISHI ICs (AV COMMON) M52795SP/FP Notice. This is not a final specification. Some parametric limits are subject to change. AV SWITCH with I2C BUS CONTROL DESCRIPTION OF PIN Name Pin No. 1 VCC 2 Lch 2 IN 4 Rch 2 IN 5 Lch 3 IN 7 Rch 3 IN 8 Lch 4 IN 10 Rch 4 IN 24 Rch T IN 26 Lch T IN 3 VIDEO 2 IN 6 VIDEO 3 IN 9 VIDEO 4 IN 25 TUNER IN 11 SCL 12 SDA 13 DC 14 DD 27 D4 28 D5 Peripheral circuit pins DC voltage(V) 9V Remarks 5~9V 4.7V 30K 3.6V Clamp in VIL max.=1.5V VIH min.=3.0V VIL max.=1.5V VIH min.=3.0V VOL max.=0.4V (at Iin=3mA) VOL max.=0.4V (at Iin=1mA) MITSUBISHI 3-9 AUG.'98 PRELIMINARY MITSUBISHI ICs (AV COMMON) M52795SP/FP Notice. This is not a final specification. Some parametric limits are subject to change. AV SWITCH with I2C BUS CONTROL DESCRIPTION OF PIN (cont.) Pin No. Name 15 GND 16 CHIP SELECT Peripheral circuit pins DC voltage(V) Remarks SLAVE ADDRESS 0~1.5V-------90H 2.5V~Vcc----92H OPEN--------90H 70K 30K 17 BIAS 4.2V 30K 18 Rch 2 OUT 20 Lch 2 OUT 21 Rch 1 OUT 23 Lch 1 OUT 4.0V 1.5K 1.5K 19 V 2 OUT 22 V 1 OUT 15K SYNC CHIP DC=2.9V 5K 5K MITSUBISHI 4-9 AUG.'98 PRELIMINARY MITSUBISHI ICs (AV COMMON) M52795SP/FP Notice. This is not a final specification. Some parametric limits are subject to change. AV SWITCH with I2C BUS CONTROL 2 I C BUS I 2C BUS(Inter IC BUS)is multi master bus system developed by PHILIPS . Two wires ( SDA - serial data, SCL - serial clock ) realize functions of start , stop , transferring data , synchronization and arbitration. The output stages of device connected to the bus must have an open drain or open collector in order to perform the wired-AND function . SDA A A LSB MSB MSB LSB SCL S P 1 2 3 5 4 6 7 9 8 1 2 9 S ; Start condition, a high to low transition of the SDA line while SCL is high P ; Stop condition, a low to high transition of the SDA line while SCL is high A ; Acknownledge Every byte put on the SDA line must be 8-bits long . Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB ) first . The data on the SDA line must be stable during the HIGH period of the clock . The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW . CONTROL This IC controls 2-channel switchs with 2-byte data ( DATA1 and DATA2 ) . SW1 is controled by DATA1 , SW2 is controled by DATA2 . S SLAVE ADDRESS A DATA1 A DATA2 A P S : Start A : Acknowledge P : Stop SLAVE ADDRESS 1 0 0 1 0 0 X 0 R/W bit Usually ` 0 ` ( W : Master transmitter transmits to slave receiver ) Possible to select 16PIN Hi:1,Lo:0 MITSUBISHI 5-9 AUG.'98 PRELIMINARY MITSUBISHI ICs (AV COMMON) M52795SP/FP Notice. This is not a final specification. Some parametric limits are subject to change. AV SWITCH with I2C BUS CONTROL Data byte format M52795 FUNCTION TABLE S SLAVE ADDRESS SLAVE ADDRESS SLAVE ADDRESS A A6 A5 1 DATA1(D7~D0) CONT DATA CONT VIDEO SW1 CONT DATA V-SW1 D1 D0 0 0 1 1 I/O CONT. DATA D5 D7 OUT D5 OUT 0 HI 1 LO AUDIO SW1 CONT MODE DATA D1 D0 0 0 1 1 0 1 0 1 DATA2(DF~D8) CONT DATA CONT VIDEO SW2 CONT DATA V-SW2 D9 D8 0 0 1 1 I/O CONT. DATA DD MUTE OUT Lch OUT 1 MUTE MUTE MUTE MUTE 0 1 0 1 D5 I/O A2 1 D4 I/O DATA(DF~D8) A A1 R/W 0 D3 V AMP1 AUDIO MODE1 CONT DATA D7 D6 0 0 1 1 R/R OUT Rch OUT 1 Lch OUT 1 MUTE Rch T IN MUTE Rch 2 IN MUTE Rch 3 IN MUTE Rch 4 IN DE AUDIO MODE D2 A0 0 0/1 P 0 D1 D0 SW1 CONT DD I/O MODE 0 1 0 1 MUTE R/R L/L NORMAL L/L OUT Rch OUT 1 Lch OUT 1 Rch T IN Lch T IN Rch 2 IN Lch 2 IN Rch 3 IN Lch 3 IN Rch 4 IN Lch 4 IN NORMAL OUT Rch OUT 1 Lch OUT 1 Lch T IN Lch T IN Lch 2 IN Lch 2 IN Lch 3 IN Lch 3 IN Lch 4 IN Lch 4 IN DC I/O DA DB V AMP2 Rch OUT 1 Rch T IN Rch 2 IN Rch 3 IN Rch 4 IN D9 D8 SW2 CONT OUT2 AMP GAIN CONT. DATA AMP DB V AMP2 0 0dB 1 6dB T IN V 2 IN V 3 IN V 4 IN DATA DC A3 0 OUT D4 OUT 0 HI 1 LO OUT V OUT2 0 1 0 1 A OUT1 AMP GAIN CONT. DATA AMP D3 V AMP1 0 0dB 1 6dB T IN V 2 IN V 3 IN V 4 IN DF OUT DD OUT 0 HI 1 LO AUDIO SW2 CONT MODE DATA D9 D8 0 0 1 1 D6 AUDIO MODE DATA D4 A4 0 OUT V OUT1 0 1 0 1 DATA(D7~D0) AUDIO MODE CONT DATA DF DE 0 0 1 1 OUT DC OUT 0 HI 1 LO MUTE OUT Lch OUT 2 MUTE MUTE MUTE MUTE R/R OUT Rch OUT 2 Lch OUT 2 MUTE Rch T IN MUTE Rch 2 IN MUTE Rch 3 IN MUTE Rch 4 IN MODE 0 1 0 1 L/L OUT Rch OUT 2 Lch OUT 2 Rch T IN Lch T IN Rch 2 IN Lch 2 IN Rch 3 IN Lch 3 IN Rch 4 IN Lch 4 IN MITSUBISHI MUTE R/R L/L NORMAL NORMAL OUT Rch OUT 2 Lch OUT 2 Lch T IN Lch T IN Lch 2 IN Lch 2 IN Lch 3 IN Lch 3 IN Lch 4 IN Lch 4 IN Rch OUT 2 Rch T IN Rch 2 IN Rch 3 IN Rch 4 IN 6 -9 AUG.'98 PRELIMINARY MITSUBISHI ICs (AV COMMON) M52795SP/FP Notice. This is not a final specification. Some parametric limits are subject to change. AV SWITCH with I2C BUS CONTROL ELECTRICAL CHARACTERISTICS Parameter Symbol Supply voltage Vcc Circuit current Icc (Ta=25°C,Vcc=9V,unless otherwise noted) Min. Typ. Max. Unit 4.7 - 9.3 V Vcc=9V,Vin=0Vp-p,Rl=∞Ω - 32 42 Vcc=5V,Vin=0Vp-p,Rl=∞Ω - 28 37 Test condition mA VIDEO Voltage gain G Frequency characteristics F Dynamic Range D Input impedance ZIV Crosstalk CT f=100kHz,1Vp-p (0dB)(T V1OUT) -0.5 0 0.5 f=100kHz,1Vp-p (6dB)(T V1OUT) 5.5 6 6.5 f=10MHz/100kHz,1Vp-p (0dB)(T V1OUT) -2.0 0 2.0 f=10MHz/100kHz,1Vp-p (6dB)(T V1OUT) -2.0 0 2.0 dB dB 4 - - 2 - - Clamp in(T,V2,V3,V4) - - - kΩ f=1MHz,1Vp-p T V1OUT (at V2 mode) - -60 -54 dB Vcc=9V(0dB)(T V1OUT) Vcc=5V(0dB)(T V1OUT) f=100kHz Maximum with distortion<1.0% Vp-p AUDIO Voltage gain G Frequency characteristics F Total harmonic distortion THD Dynamic Range D Output DC offset voltage VOFF f=1kHz ,1Vp-p (Vcc9V)(RT R1OUT) -0.5 0 0.5 f=1kHz ,1Vp-p (Vcc5V)(RT R1OUT) -0.5 0 0.5 f=100kHz/1kHz , 1Vp-p(RT R1OUT) -2.0 0 1.0 dB dB f=1kHz,2Vp-p,at 400HzHPF+30kHzLPF (RT R1OUT) - 0.01 0.05 % f=1kHz ,Maximum with distortion<0.5% (RT R1OUT) (MODE:RT,R2,R3,R4 R1OUT ) 5.5 6.0 - Vp-p -20 0 20 mV Input impedance Z1 (RT,R2,R3,R4,LT,L2,L3,L4 ) 22 30 38 kΩ Crosstalk CT 1kHz,1Vp-p RT R1OUT(at R2 mode) - -90 -84 dB MITSUBISHI 7-9 AUG.'98 PRELIMINARY MITSUBISHI ICs (AV COMMON) M52795SP/FP Notice. This is not a final specification. Some parametric limits are subject to change. AV SWITCH with I2C BUS CONTROL ELECTRICAL CHARACTERISTICS (Ta=25°C,Vcc=9V,unless otherwise noted) Symbol Parameter Min. Typ. Max. 3.0 - 5.0 0.0 - 1.5 SDA = 3mA 0.0 - 0.4 SDA , SCL = 4.5 V -10 - 10 SDA , SCL = 0.4 V -10 - 10 0.0 - 100 4.7 - - 4.0 - - 4.7 - - 4.0 - - 4.7 - - 5.0 - - 250 - - - - 1000 - - 300 4.0 - - Test condition Unit I2C BUS CONTROL SIGNAL Max. input high voltage Min. input low voltage Low level output voltage(SDA) High level input current Low level input current SCL clock frequency Time of bus must be free before a new transmission can start Hold time at start condition The low period of the clock The high period of the clock Setup time for start condition Hold time DATA Setup time DATA Rise time of both SDA and SCL line Fall time of both SDA and SCL line Setup time for stop condition VIH VIL VOL IIH IIL fSCL tBUF tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tR tF tSU;STO V µA kHz µS nS µS I 2 C BUS CONTROL SIGNAL SDA tBUF tR tHD;STA tF SCL P S tLOW tHD;DAT tHIGH tSU;DAT tSU;STA tSU;STO Sr P tHD;STA MITSUBISHI 8 -9 AUG.'98 PRELIMINARY MITSUBISHI ICs (AV COMMON) M52795SP/FP Notice. This is not a final specification. Some parametric limits are subject to change. AV SWITCH with I2C BUS CONTROL Application Circuit Example 0.01µ 100µ 10K VCC 1 VCC D5 28 2 Lch 2 IN D4 27 10K 10µ 75 0.47µ 10µ 3 VIDEO 2 IN Lch T IN 26 10µ 0.47µ 4 Rch 2 IN TUNER IN 25 10µ 10µ 5 Lch 3 IN 75 75 Rch T IN 24 0.47µ 6 VIDEO 3 IN Lch 1 OUT 23 10µ 7 Rch 3 IN V 1 OUT 22 75 75 10µ 8 Lch 4 IN Rch 1 OUT 21 9 VIDEO 4 IN Lch 2 OUT 20 75 0.47µ 10µ 10 Rch 4 IN 5V 10K V 2 OUT 19 75 75 220 11 SCL Rch 2 OUT 18 12 SDA BIAS 17 10K 5V 220 10µ 10K 13 DC CHIP SELECT 16 slave address Change(VCC/GND) 10K 14 DD GND 15 Note how to use this IC Input signal with sufficient low impedance to input terminal. The capacitance of output terminal as small as possible. Set the capacitance between Vcc and GND near the pins if possible. Assign an area as large as possible for grounding. Power-on Reset The M52795 has an intermal power-on reset function that sets each control r egister to "0" during IC power ON. The power-on reset VTH has 2.5V. MITSUBISHI 9-9 AUG.'98