PRELIMINARY MITSUBISHI ICs (AV COMMON) Notice. This is not a final specification. Some parametric limits are subject to change. M52797SP/FP AV SWITCH with I2C BUS CONTROL DESCRIPTION The M52797 is AV switch semiconductor integrated circuit with I2C bus control . This IC contains 1-channel of 4-input audio switches and 1channel of 4-input video switches. Each audio switches and video switches can be controled independently . The video switches contain amplifiers can be controled a gain of output 0dB or 6dB . FEATURES •Video and stereo sound switches in one package •Wide frequency range ( video switch )...........DC~20MHz •High separation ( video switch ) .........................Crosstalk -60dB ( typ. ) at 1MHz •Two types of packages are provided : SDIP with a lead pitch of 1.778mm ( M52797SP ) ; and SOP with a lead pitch of 1.27mm ( M52797FP ) . PIN CONFIGURATION ( TOP VIEW ) VCC VCC Lch 2 IN VIDEO 2 IN Rch 2 IN Lch 3 IN VIDEO 3 IN Rch 3 IN Lch 4 IN VIDEO 4 IN Rch 4 IN SCL SDA NC 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 NC Lch T IN TUNER IN Rch T IN Lch 1 OUT V 1 OUT Rch 1 OUT BIAS V 2 OUT D4 D5 CHIP SELECT GND GND Outline 28P4B (Lead pitch :1.778mm) APPLICATION NC: No connection Video equipment PIN CONFIGURATION ( TOP VIEW ) RECOMMENDED OPERATING CONDITION Supply voltage Rated supply voltage Maximum output current 4.7V~9.3V 5V,9V 24mA(at 9V) VCC Lch 2 IN VIDEO 2 IN Rch 2 IN Lch 3 IN VIDEO 3 IN Rch 3 IN Lch 4 IN VIDEO 4 IN Rch 4 IN SCL SDA 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 Lch T IN TUNER IN Rch T IN Lch 1 OUT V 1 OUT Rch 1 OUT BIAS V 2 OUT D4 D5 CHIP SELECT GND Outline 24P2N-B (Lead pitch :1.27mm) MITSUBISHI 1-9 AUG.'98 PRELIMINARY MITSUBISHI ICs (AV COMMON) M52797SP/FP Notice. This is not a final specification. Some parametric limits are subject to change. AV SWITCH with I2C BUS CONTROL BLOCK DIAGRAM VCC TUNER IN VIDEO 2 IN VIDEO 3 IN VIDEO 4 IN 1 2 26 0/6dB 4 23 7 V 1 OUT V-SW 10 0dB 20 V 2 OUT Rch T IN 25 Rch 2 IN Rch 3 IN R-MODE 5 8 R M L R-SW Rch 4 IN 0dB 22 Rch 1 OUT 11 Lch T IN 27 Lch 2 IN L-MODE 3 6 Lch 4 IN 0dB L M R Lch 3 IN L-SW 24 Lch 1 OUT 9 BIAS 21 I2C Control BIAS 14 28 NC 15 GND 19 18 16 D4 13 SDA 12 SCL 17 D5 CHIP SELECT (at 28P4B) MITSUBISHI 2-9 AUG.'98 PRELIMINARY MITSUBISHI ICs (AV COMMON) M52797SP/FP Notice. This is not a final specification. Some parametric limits are subject to change. AV SWITCH with I2C BUS CONTROL DESCRIPTION OF PIN Pin No. Name 1 2 Vcc 3 Lch 2 IN 5 Rch 2 IN 6 Lch 3 IN 8 Rch 3 IN 9 Lch 4 IN 11 Rch 4 IN 25 Rch T IN 27 Lch T IN Peripheral circuit pins DC voltage(V) 9V Remarks 5~9V 4.7V 30K VIDEO 2 IN 7 VIDEO 3 IN 10 VIDEO 4 IN 26 TUNER IN 12 SCL VIL max.=1.5V VIH min.=3.0V 13 SDA VIL max.=1.5V VIH min.=3.0V VOL max.=0.4V (at Iin=3mA) 15 16 GND 17 3.6V Clamp in 4 CHIP SELECT 70K 30K MITSUBISHI SLAVE ADDRESS 0~1.5V-----90H 2.5V~Vcc--92H OPEN------90H 3- 9 AUG.'98 PRELIMINARY MITSUBISHI ICs (AV COMMON) M52797SP/FP Notice. This is not a final specification. Some parametric limits are subject to change. AV SWITCH with I2C BUS CONTROL DESCRIPTION OF PIN (cont.) Pin No. Name Peripheral circuit pins DC voltage(V) 18 D5 19 D4 20 V 2 OUT SYNC CHIP DC=2.2V 23 V 1 OUT SYNC CHIP DC=2.9V VOL max.=0.4V (at Iin=1mA) 5K 21 Remarks 5K BIAS 4.2V 30K 22 Rch 1 OUT 24 Lch 1 OUT 4.0V 1.5K 1.5K 15K MITSUBISHI 4 -9 AUG.'98 PRELIMINARY MITSUBISHI ICs (AV COMMON) M52797SP/FP Notice. This is not a final specification. Some parametric limits are subject to change. AV SWITCH with I2C BUS CONTROL 2 I C BUS I 2C BUS(Inter IC BUS)is multi master bus system developed by PHILIPS . Two wires ( SDA - serial data, SCL - serial clock ) realize functions of start , stop , transferring data , synchronization and arbitration. The output stages of device connected to the bus must have an open drain or open collector in order to perform the wired-AND function . SDA A A LSB MSB MSB LSB SCL S P 1 2 3 5 4 6 7 8 9 1 2 9 S ; Start condition, a high to low transition of the SDA line while SCL is high P ; Stop condition, a low to high transition of the SDA line while SCL is high A ; Acknownledge Every byte put on the SDA line must be 8-bits long . Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB ) first . The data on the SDA line must be stable during the HIGH period of the clock . The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW . CONTROL This IC controls channel switchs with 1-byte data ( DATA1) . S SLAVE ADDRESS A DATA1 A P S : Start A : Acknowledge P : Stop SLAVE ADDRESS 1 0 0 1 0 0 X 0 R/W bit Usually ` 0 ` ( W : Master transmitter transmits to slave receiver ) Possible to select 17PIN Hi:1,Lo:0 (at 28P4B) MITSUBISHI 5 -9 AUG.'98 PRELIMINARY MITSUBISHI ICs (AV COMMON) M52797SP/FP Notice. This is not a final specification. Some parametric limits are subject to change. AV SWITCH with I2C BUS CONTROL Data byte format M52797 FUNCTION TABLE S SLAVE ADDRESS SLAVE ADDRESS SLAVE ADDRESS A A6 DATA(D7~D0) A5 A4 1 DATA1 CONT DATA CONT VIDEO SW CONT DATA V-SW D1 D0 0 0 1 1 AUDIO SW CONT MODE DATA D1 D0 0 0 1 1 AMP GAIN CONT. DATA AMP D3 V AMP1 0 0dB 1 6dB D7 0 D6 AUDIO MODE 0 1 0 1 T IN V 2 IN V 3 IN V 4 IN 0 1 0 1 MUTE OUT Lch OUT 1 MUTE MUTE MUTE MUTE A3 0 D5 I/O P A2 1 D4 I/O AUDIO MODE CONT DATA D7 D6 0 0 1 1 OUT V OUT A A1 0 D3 V AMP 0 1 0 1 0 D0 SW CONT MUTE R/R L/L NORMAL L/L OUT Rch OUT 1 Lch OUT 1 Rch T IN Lch T IN Rch 2 IN Lch 2 IN Rch 3 IN Lch 3 IN Rch 4 IN Lch 4 IN I/O CONT. DATA D4 DATA D5 MITSUBISHI D1 R/W MODE R/R OUT Rch OUT 1 Lch OUT 1 MUTE Rch T IN MUTE Rch 2 IN MUTE Rch 3 IN MUTE Rch 4 IN OUT D4 OUT 0 HI 1 LO D2 A0 0 0/1 NORMAL OUT Rch OUT 1 Lch OUT 1 Lch T IN Lch T IN Lch 2 IN Lch 2 IN Lch 3 IN Lch 3 IN Lch 4 IN Lch 4 IN Rch OUT 1 Rch T IN Rch 2 IN Rch 3 IN Rch 4 IN OUT D5 OUT 0 HI 1 LO 6 -9 AUG.'98 PRELIMINARY MITSUBISHI ICs (AV COMMON) M52797SP/FP Notice. This is not a final specification. Some parametric limits are subject to change. AV SWITCH with I2C BUS CONTROL ELECTRICAL CHARACTERISTICS Parameter Symbol Supply voltage Vcc Circuit current Icc (Ta=25°C,Vcc=9V,unless otherwise noted) Min. Typ. Max. Unit 4.7 - 9.3 V Vcc=9V,Vin=0Vp-p ,Rl=∞Ω - 24 32 Vcc=5V,Vin=0Vp-p ,Rl=∞Ω - 20 27 Test condition mA VIDEO Voltage gain G Frequency characteristics F Dynamic Range D Input impedance ZIV Crosstalk CT f=100kHz,1Vp-p (0dB)(T V1OUT) -0.5 0 0.5 f=100kHz,1Vp-p (6dB)(T V1OUT) 5.5 6 6.5 f=10MHz/100kHz,1Vp-p (0dB)(T V1OUT) -2.0 0 2.0 f=10MHz/100kHz,1Vp-p (6dB)(T V1OUT) -2.0 0 2.0 dB dB 4 - - 2 - - Clamp in(T,V2,V3,V4) - - - kΩ f=1MHz,1Vp-p T V1OUT (at V2 mode) - -60 -54 dB Vcc=9V(0dB)(T V1OUT) Vcc=5V(0dB)(T V1OUT) f=100kHz Maximum with distortion<1.0% Vp-p AUDIO Voltage gain G Frequency characteristics F Total harmonic distortion THD Dynamic Range D Output DC offset voltage VOFF f=1kHz ,1Vp-p (Vcc9V)(RT R1OUT) -0.5 0 0.5 f=1kHz ,1Vp-p (Vcc5V)(RT R1OUT) -0.5 0 0.5 f=100kHz/1kHz , 1Vp-p(RT R1OUT) -2.0 0 1.0 dB dB f=1kHz,2Vp-p,at 400HzHPF+30kHzLPF (RT R1OUT) - 0.01 0.05 % f=1kHz ,Maximum with distortion<0.5% (RT R1OUT) (MODE:RT,R2,R3,R4 R1OUT ) 5.5 6.0 - Vp-p -20 0 20 mV Input impedance Z1 (RT,R2,R3,R4,LT,L2,L3,L4 ) 22 30 38 kΩ Crosstalk CT 1kHz,1Vp-p RT R1OUT(at R2 mode) - -90 -84 dB MITSUBISHI 7 -9 AUG.'98 PRELIMINARY MITSUBISHI ICs (AV COMMON) M52797SP/FP Notice. This is not a final specification. Some parametric limits are subject to change. AV SWITCH with I2C BUS CONTROL ELECTRICAL CHARACTERISTICS (Ta=25°C,Vcc=9V,unless otherwise noted) Symbol Parameter Min. Typ. Max. 3.0 - 5.0 0.0 - 1.5 SDA = 3mA 0.0 - 0.4 SDA , SCL = 4.5 V -10 - 10 SDA , SCL = 0.4 V -10 - 10 0.0 - 100 4.7 - - 4.0 - - 4.7 - - 4.0 - - 4.7 - - 5.0 - - 250 - - - - 1000 - - 300 4.0 - - Test condition Unit I2C BUS CONTROL SIGNAL Max. input high voltage Min. input low voltage Low level output voltage(SDA) High level input current Low level input current SCL clock frequency Time of bus must be free before a new transmission can start Hold time at start condition The low period of the clock The high period of the clock Setup time for start condition Hold time DATA Setup time DATA Rise time of both SDA and SCL line Fall time of both SDA and SCL line Setup time for stop condition VIH VIL VOL IIH IIL fSCL tBUF tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tR tF tSU;STO V µA kHz µS nS µS I 2 C BUS CONTROL SIGNAL SDA tBUF tR tHD;STA tF SCL P S tLOW tHD;DAT tHIGH tSU;DAT tSU;STA tSU;STO Sr P tHD;STA MITSUBISHI 8-9 AUG.'98 PRELIMINARY MITSUBISHI ICs (AV COMMON) M52797SP/FP Notice. This is not a final specification. Some parametric limits are subject to change. AV SWITCH with I2C BUS CONTROL Application Circuit Example 0.01u 100u VCC 1 VCC NC 28 2 VCC Lch T IN 27 10u 0.47u 10u 3 Lch 2 IN TUNER IN 26 75 10u 0.47u 4 VIDEO 2 IN 75 Rch T IN 25 10u 5 Rch 2 IN Lch 1 OUT 24 6 Lch 3 IN V 1 OUT 23 10u 75 75 75 0.47u 7 VIDEO 3 IN Rch 1 OUT 22 10u 10u 8 Rch 3 IN BIAS 21 9 Lch 4 IN V 2 OUT 20 10u 75 10K 0.47u 10 VIDEO 4 IN D4 19 11 Rch 4 IN D5 18 10K 10u 10K 220 5V 12 SCL CHIP SELECT 17 slave address Cange(VCC/GND) 10K 5V 220 13 SDA GND 16 14 NC GND 15 (at 28P4B) Note how to use this IC Input signal with sufficient low impedance to input terminal. The capacitance of output terminal as small as possible. Set the capacitance between Vcc and GND near the pins if possible. Assign an area as large as possible for grounding. Power-on Reset The M52797 has an intermal power-on reset function that sets each control r egister to "0" during IC power ON. The power-on reset VTH has 2.5V. MITSUBISHI 9 -9 AUG.'98