MITSUBISHI <Dig./Ana. INTERFACE> M62392P,FP 8-BIT 12CH I2C BUS D-A CONVERTER WITH BUFFER AMPLIFIERS GENERAL DESCRIPTION PIN CONFIGURATION (TOP VIEW) R 1 SCL 2 24 CS0 SDA 3 22 CS2 23 CS1 M62392P,FP The M62392P,FP is a CMOS 12-channel D-A converter with output buffer amplifiers. It can communicate with a microcontroller via few wiring thanks to the adoption of the two-line I2C BUS. The output buffer amplifier employs AB class output with sinking and sourcing capability of more than 1.0mA , and an output voltage range is nearly between ground and VrefU. Maximum 8 ICs can be connected to a bus by using three chip-select pins, so that it is possible to handle up to 96 channels. Ao7 4 Ao8 5 Ao9 6 Ao10 7 Ao11 8 FEATURES • I2C-bus serial data method 21 VDD 20 VCC 19 Ao6 18 Ao5 17 Ao4 Ao12 9 16 Ao3 VrefL 10 VrefU1 11 15 Ao2 14 Ao1 GND 12 • Wide output voltage range Nearly between ground and VrefU (0~5V) 13 VrefU2 Outline • High output current drive capability 24P4D(P) 24P2N-B(FP) over ±1.0mA • 2 setting voltage ranges by dual input pins for upper voltage references (VrefU1,U2) APPLICATION Conversion from digital data to analog control data for both consumer and industrial equipment. Gain control and automatic adjustment of DISPLAY-MONITOR or CTV. BLOCK DIAGRAM CS0 CS1 CS2 VDD Vcc 24 23 22 21 Ao6 Ao5 Ao4 Ao3 Ao2 Ao1 19 18 17 16 15 14 8bit upper segment R-2R 8bit upper segment R-2R 8bit upper segment R-2R 8bit upper segment R-2R 8bit upper segment R-2R 8bit upper segment R-2R 8bit Latch 8bit Latch 8bit Latch 8bit Latch 8bit Latch 8bit Latch 8bit Latch 8bit Latch 8bit Latch 8bit Latch 8bit Latch 8bit Latch 8bit upper segment R-2R 8bit upper segment R-2R 8bit upper segment R-2R 8bit upper segment R-2R 8bit upper segment R-2R 8bit upper segment R-2R 4 5 6 7 20 VrefU2 GND 13 12 10 11 1 R ADDRESS DECODER I2C BUS TRANSCEIVER CHIP SELECT 8 2 3 SCL SDA Ao7 Ao8 Ao9 Ao10 MITSUBISHI ELECTRIC 8 9 Ao11 Ao12 VrefL VrefU1 1997-5-27C.rev ( 1 / 7 ) MITSUBISHI <Dig./Ana. INTERFACE> M62392P,FP 8-BIT 12CH I2C BUS D-A CONVERTER WITH BUFFER AMPLIFIERS EXPLANATION OF TERMINALS PIN No. Symbol Function 3 SDA Serial data input terminal 1 R Reset signal input terminal 2 SCL Serial clock input terminal 14 Ao1 15 Ao2 16 Ao3 17 Ao4 18 Ao5 19 Ao6 4 Ao7 5 Ao8 6 Ao9 7 Ao10 8 Ao11 9 Ao12 20 VCC Analog power supply terminal 21 VDD Digital power supply terminal 12 GND Analog and digital common GND 10 VrefL D–A converter low level reference voltage input terminal 11 VrefU1 D–A converter high level reference voltage input terminal 1 13 VrefU2 D–A converter high level reference voltage input terminal 2 22 CS2 Chip select data input terminal 2 23 CS1 Chip select data input terminal 1 24 CS0 Chip select data input terminal 0 8bit D–A converter output terminal MITSUBISHI ELECTRIC 1997-5-27C.rev ( 2 / 7 ) MITSUBISHI <Dig./Ana. INTERFACE> M62392P,FP 8-BIT 12CH I2C BUS D-A CONVERTER WITH BUFFER AMPLIFIERS ABSOLUTE MAXIMUM RATING Symbol Parameter Conditions Unit Ratings VCC Supply voltage –0.3 to 7.0 V VDD Supply voltage –0.3 to 7.0 V –0.3 to 7.0 V D–A converter HIGH level VrefU1,2 reference voltage Vin Input voltage –0.3 to VDD +0.3 V Vo Output voltage –0.3 to VCC +0.3 V Pd Power dissipation 465(DIP) / 421(FP) mW Topr Operating temperature –20 to 85 °C Tstg Storage temperature –55 to 125 °C ELECTRICAL CHARACTERISTICS <Digital part> (VCC,VDD,Vref U1,2=+5V±10%,VCC≥Vref U1,2,GND=VrefL=0V,Ta=–20 to 85°C unless otherwise noted) Symbol VDD Parameter Test conditions Supply voltage IDD Supply current CLK=1MHz operation IAO=0µA IILK Input leak current VIN=0~VDD VIL Input low voltage VIH Input high voltage MIN Ratings TYP MAX 4.5 5.0 5.5 V 1.0 mA 10 µA 0.2VDD V –10 Unit 0.8VDD V <Analog part> (VCC,VDD,Vref U1,2=+5V±10%,VCC≥VrefU1,2,GND=VrefL=0V,Ta=–20 to 85°C unless otherwise noted) Ratings Test conditions Symbol Parameter Unit MIN TYP MAX VCC Supply voltage ICC Supply current 4.5 CLK=1MHz operation IAO=0µA IrefU D-A converter high level VrefU=5V,VrefL=0V reference voltage input current Data condition:at maximum current VrefU D-A converter high level reference voltage range 5.0 5.5 V 1.0 3.0 mA 1.4 3.0 mA 3.5 VCC V D-A converter low level reference voltage range Buffer amplifier output voltage range The output dose not necessarily be the values within the reference voltage setting range. GND VCC-3.5 V IAO=±100µA IAO=±500µA 0.1 0.2 VCC-0.1 VCC-0.2 V V IAO Buffer amplifier output drive range Upper side saturation voltage=0.3V Lower side saturation voltage=0.2V –1.0 1.0 mA SDL Differential nonlinearity –1.0 1.0 LSB –1.5 1.5 LSB –2.0 2.0 LSB –2.0 2.0 LSB 0.1 µF VrefL VAO SL Nonlinearity SZERO Zero code error SFULL Full scale error Co Output capacitive load Ro Buffer amplifier output impedance VrefU=4.79V VrefL=0.95V VCC=5.5V(15mV/LSB) without load (IAO=0) 5.0 MITSUBISHI ELECTRIC Ω 1997-5-27C.rev ( 3 / 7 ) MITSUBISHI <Dig./Ana. INTERFACE> M62392P,FP 8-BIT 12CH I2C BUS D-A CONVERTER WITH BUFFER AMPLIFIERS I2C BUS LINE CHARACTERISTICS Symbol Normal mode Parameter High speed mode units Min. Max. Min. Max. 0 100 0 400 KHz fSCL SCL clock frequency tBUF Time the bus must be free before a new transmission can start 4.7 - 1.3 - µs tHD:STA Hold time START Condition. After this period,the first clock pulse is generated. 4.0 - 0.6 - µs tLOW LOW period of the clock 4.7 - 1.3 - µs tHIGH HIGh period of the clock 4.0 - 0.6 - µs tSU:STA Set-up time for START condition (Only relevant for a repeated START condition) 4.7 - 4.7 - µs tHD:DAT Hold time DATA 0 - 0 0.9 µs tSU:DAT Set-up time DATA 250 - 100 - ns tR Rise time of both SDA and SCL lines - 1000 20+ 300 ns tF Fall time of both SDA and SCL lines - 300 20+ 300 ns tSU:STO Set-up time for STOP condition 4.0 - 0.6 - µs *Note that a transmitter must internally provide at least a hold time to bridge the undefined region (max.300 ns) of the falling edge of SCL. TIMING CHART tR, tF tBUF VIH SDA VIL tHD:STA tSU:DAT tHD:DAT tSU:STA tSU:STO VIH SCL VIL tLOW START tHIGH START MITSUBISHI ELECTRIC STOP START 1997-5-27C.rev ( 4 / 7 ) MITSUBISHI <Dig./Ana. INTERFACE> M62392P,FP 8-BIT 12CH I2C BUS D-A CONVERTER WITH BUFFER AMPLIFIERS I2C BUS FORMAT STA SLAVE ADDRESS W A SUB ADDRESS A DAC DATA A STP DIGITAL DATA FORMAT •SUB ADDRESS •SLAVE ADDRESS Last First 1 0 0 1 (SLAVE ADDRESS) A2 A1 Last First X A0 CHIP SELECT DATA X X X S3 Don't care S2 S1 S0 CHANNEL SELECT DATA •DAC DATA Last LSB First MSB D7 D6 D5 D4 D3 D2 D1 D0 (1)CHIP SELECT DATA (2)CHANNEL SELECT DATA MSB MSB LSB A2 A1 0 0 0 0 0 1 1 1 A0 CS2 CS1 CS0 0 1 0 1 0 0 0 1 0 0 1 1 0 1 0 1 Lower 3bits(A0,A1,A2) are a programmable address. This IC is accessed only when the lower 3 bits data of slave address coincide with the data of CS0 to CS2.(refer to the upper table) LSB S3 S2 S1 S0 Channel selection 0 0 0 0 0 0 0 0 1 0 1 0 Don't care. 1 1 1 0 1 1 1 0 0 1 0 1 ch11 selection 1 1 1 1 Don't care. ch1 selection ch2 selection ch12 selection Don't care. (3)DAC DATA First MSB Last LSB D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 (VrefU-VrefL)/256 x 1+VrefL (VrefU-VrefL)/256 x 2+VrefL (VrefU-VrefL)/256 x 3+VrefL (VrefU-VrefL)/256 x 4+VrefL 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 (VrefU-VrefL)/256 x 255+VrefL VrefU DAC output MITSUBISHI ELECTRIC 1997-5-27C.rev ( 5 / 7 ) MITSUBISHI <Dig./Ana. INTERFACE> M62392P,FP 8-BIT 12CH I2C BUS D-A CONVERTER WITH BUFFER AMPLIFIERS TIMING CHART (MODEL) •start condition to slave address bite SDA 1 2 3 4 5 6 7 W 2 3 4 5 6 7 8 A 3 4 5 6 7 8 A A SCL R DAC output start condition •sub address bite SDA 1 SCL R DAC output •DAC data bite to stop condition SDA 1 2 SCL R DAC output stop condition •Start condition ……… With SCL at HIGH,SDA line goes from HIGH to LOW •Stop condition ……… With SCL at HIGH,SDA line goes from LOW to HIGH (*Under normal circumstances,SDA is changed when SCL is LOW) •Acknowledge bit …… The receiving IC has to pull down SDA line whenever receive slave data. (The transmitting IC releases the SDA line just then transmit 8bit data.) MITSUBISHI ELECTRIC 1997-5-27C.rev ( 6 / 7 ) MITSUBISHI <Dig./Ana. INTERFACE> M62392P,FP 8-BIT 12CH I2C BUS D-A CONVERTER WITH BUFFER AMPLIFIERS PRECAUTION FOR USE M62392 have 5 terminals (VDD,VCC,VrefU1,VrefU2,VrefL) for input constant voltage at use. IF ripple or spike is input these terminals,accuracy of D-A conversion is down. So,when use this device,please connect capacitor among each terminal to GND for stable D-A conversion. This IC's output amplifier has an advantage to capacitive load.So it's no problem at device action when connect capacitor (0.1µF MAX) among output to GND for every noise eliminate. APPLICATION EXAMPLE 5V 10µF CS2 VDD VCC ch1 ch2 AO1 CHIP SELECT DATA SETTING CS1 AO2 CS0 AO3 ch3 ch4 ch5 ch6 ch7 ch8 ch9 ch10 ch11 ch12 AO4 R RESET SIGNAL AO5 AO6 VrefU1 5V 10µF 5V 10µF AO7 VrefU2 AO8 AO9 AO10 5V AO11 SCL MCU 5V 10µF AO12 SDA GND ANALOG OUTPUT TERMINALS VrefL 10µF *Purchase of MITSUBISHI ELECTRIC CORPORATION'S I2C components conveys a license under the Philips I2C Patent Rights to use these components an I2C system,provided that the system conforms to I2C Standard Specification as defined by Philips. ! Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury,fire or property damage.Remember to give due consideration to safety when making your circuit design,in order to prevent fires from spreading,redundancy,malfunction or other mishap. MITSUBISHI ELECTRIC 1997-5-27C.rev ( 7 / 7 )