MITSUBISHI LSIs M6MGB/T166S2BWG 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS 3.3V-ONLY FLASH MEMORY & 2,097,152-BIT (131,072-WORD BY 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) DESCRIPTION FEATURES The MITSUBISHI M6MGB/T166S2BWG is a Stacked Chip Scale Package (S-CSP) that contents 16M-bits flash memory and 2M-bits Static RAM in a 72-pin S-CSP. 16M-bits Flash memory is a 1,048,576 words, 3.3V-only, and high performance non-volatile memory fabricated by CMOS technology for the peripheral circuit and DINOR(DIvided bit-line NOR) architecture for the memory cell. 2M-bits SRAM is a 131,072words unsynchronous SRAM fabricated by silicon-gate CMOS technology. • Access time Flash Memory 90ns (Max.) SRAM 85ns (Max.) • Supply voltage Vcc=2.7 ~ 3.6V • Ambient temperature I version Ta=-40 ~ 85°C • Package : 72-pin S-CSP , 0.8mm ball pitch APPLICATION Mobile communication products M6MGB/T166S2BWG is suitable for the application of the mobile-communication-system to reduce both the mount space and weight . PIN CONFIGURATION (TOP VIEW) INDEX (Laser Marking) 11.0 mm 1 2 3 4 5 6 7 8 A NC NC B NC NC C DU F-A18 S-LB# F-WP# GND F-WE# A16 NC D A5 F-A17 S-UB# NC F-RP# FRY/BY# A8 A11 E A4 A7 S-OE# F-A19 DU DU A10 A15 F A0 A6 DU DQ11 DU NC A9 A14 G F-CE# A3 DQ9 DU DQ12 DQ13 DQ15 A13 DQ8 SCE2 DQ6 S-WE# A12 DQ14 F-GND H F-GND A2 DQ10 F-OE# A1 DQ0 DQ2 S-VCC DQ4 J DU SCE1# DQ1 DQ3 F-VCC DQ5 DQ7 I DU K NC NC L NC NC 8.0 mm F-VCC S-VCC F-GND GND A0-A16 :Vcc for Flash :Vcc for SRAM :GND for Flash :Flash/SRAM common GND :Flash/SRAM common Address F-A17-F-A19 :Address for Flash :Flash/SRAM DQ0-DQ15 common Data I/O F-CE# S-CE1# S-CE2 F-OE# S-OE# F-WE# S-WE# F-WP# F-RP# F-RY/BY# S-LB# S-UB# :Flash Chip Enable :SRAM Chip Enable 1 :SRAM Chip Enable 2 :Flash Output Enable :SRAM Output Enable :Flash Write Enable :SRAM Write Enable :Flash Write Protect :Flash Reset Power Down :Flash Ready /Busy :SRAM Lower Byte :SRAM Upper Byte NC:Non Connection DU:Don't Use (Note: Should be open) 1 Nov 1999 , Rev.2.3 MITSUBISHI LSIs M6MGB/T166S2BWG 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS 3.3V-ONLY FLASH MEMORY & 2,097,152-BIT (131,072-WORD BY 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) BLOCK DIAGRAM 16Mb Flash Memory 128 WORD PAGE BUFFER Main Block Bank(II) 32KW F-VCC 28 X-DECODER F-GND/GND Main Block Parameter Block7 Parameter Block6 Parameter Block5 Parameter Block4 Parameter Block3 Parameter Block2 Parameter Block1 Boot Block Bank(I) F-A19 F-A18 F-A17 A16 A15 A14 A13 A12 A11 ADDRESS A10 INPUTS A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 32KW 16KW 16KW 16KW 16KW 16KW 16KW 16KW 16KW Y-GATE / SENSE AMP. Y-DECODER STATUS / ID REGISTER MULTIPLEXER FLASH CHIP ENABLE INPUT FLASH OUTPUT ENABLE INPUT FLASH WRITE ENABLE INPUT FLASH WRITE PROTECT INPUT FLASH RESET/POWER DOWN INPUT FLASH READY/BUSY OUTPUT F-CE# F-OE# F-WE# F-WP# F-RP# CUI WSM INPUT/OUTPUT BUFFERS F-RY/BY# DQ15 DQ14DQ13DQ12 2Mb SRAM S-CE2 S-LB# S-UB# S-WE# S-OE# 2 CLOCK GENERATOR SENSE AMP. OUTPUT BUFFER OUTPUT BUFFER DATAINPUT BUFFER S-CE1# DATAINPUT BUFFER A16 131072 WORD x 16 BITS SENSE AMP. A15 ROW DECODER A1 DATA INPUTS/OUTPUTS ADDRESS INPUT BUFFER A0 DQ3DQ2DQ1DQ0 DQ 0 DQ 7 DQ 8 DQ15 S-VCC GND Nov 1999 , Rev.2.3 MITSUBISHI LSIs M6MGB/T166S2BWG 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS 3.3V-ONLY FLASH MEMORY & 2,097,152-BIT (131,072-WORD BY 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) 1. Flash Memory DESCRIPTION The Flash Memory of M6MGB/T166S2BWG is 3.3V-only high speed 16,777,216-bit CMOS boot block Flash Memories with alternating BGO (Back Ground Operation) feature. The BGO feature of the device allows Program or Erase operations to be performed in one bank while the device simultaneously allows Read operations to be performed on the other bank. This BGO feature is suitable for mobile and personal computing, and communication products. The Flash Memory of M6MGB/T166S2BWG is fabricated by CMOS technology for the peripheral circuits and DINOR(Divided bit line NOR) architecture for the memory cells. FEATURES Organization .................................1048,576 word x 16bit ............................. VCC = 2.7~3.6V Supply voltage ................................ Access time .............................. 90ns (Max.) Power Dissipation ................................. 54 mW (Max. at 5MHz) Read (After Automatic Power Down) .......... 0.33mW (typ.) Program/Erase .................................126 mW (Max.) ................................. 0.33mW (typ.) Standby Deep power down mode ....................... 0.33mW (typ.) Auto program for Bank(I) ................................. 4ms (typ.) Program Time Program Unit .........................1word (Byte Program) (Page Program) ......................... 128word Auto program for Bank(II) ................................. 4ms (typ.) Program Time ................................. 128word Program Unit Auto Erase ................................. 40 ms (typ.) Erase time Erase Unit Bank(I) Boot Block ..................... 16Kword x 1 .............. Parameter Block 16Kword x 7 ...................... 32Kword x 28 Bank(II) Main Block Program/Erase cycles 3 Boot Block M6MGB166S2BWG ........................ Bottom Boot M6MGT166S2BWG ........................ Top Boot Other Functions Soft Ware Command Control Selective Block Lock Erase Suspend/Resume Program Suspend/Resume Status Register Read Alternating Back Ground Program/Erase Operation Between Bank(I) and Bank(II) Auto Power Down Mode ......................................... 100Kcycles Nov 1999 , Rev.2.3 MITSUBISHI LSIs M6MGB/T166S2BWG 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS 3.3V-ONLY FLASH MEMORY & 2,097,152-BIT (131,072-WORD BY 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) FUNCTION The Flash Memory of M6MGB/T166S2BWG includes on-chip program/erase control circuitry. The Write State Machine (WSM) controls block erase and byte/page program operations. Operational modes are selected by the commands written to the Command User Interface (CUI). The Status Register indicates the status of the WSM and when the WSM successfully completes the desired program or block erase operation. A Deep Powerdown mode is enabled when the F-RP# pin is at GND, minimizing power consumption. Read The Flash Memory of M6MGB/T166S2BWG has three read modes, which accesses to the memory array, the Device Identifier and the Status Register. The appropriate read command are required to be written to the CUI. Upon initial device powerup or after exit from deep powerdown, the Flash Memory automatically resets to read array mode. In the read array mode, low level input to F-CE# and F-OE#, high level input to F-WE# and F-RP#, and address signals to the address inputs (F-A19-F-A17,A16-A0) output the data of the addressed location to the data input/output ( D15-D0). Deep Power-Down When F-RP# is at VIL, the device is in the deep powerdown mode and its power consumption is substantially low. During read modes, the memory is deselected and the data input/output are in a high-impedance(High-Z) state. After return from powerdown, the CUI is reset to Read Array , and the Status Register is cleared to value 80H. During block erase or program modes, F-RP# low will abort either operation. Memory array data of the block being altered become invalid. Automatic Power-Down (APD) The Automatic Power-Down minimizes the power consumption during read mode. The device automatically turns to this mode when any addresses or F-CE# isn't changed more than 200ns after the last alternation. The power consumption becomes the same as the stand-by mode. While in this mode, the output data is latched and can be read out. New data is read out correctly when addresses are changed. Write Writes to the CUI enables reading of memory array data, device identifiers and reading and clearing of the Status Register. They also enable block erase and program. The CUI is written by bringing F-WE# to low level, while F-CE# is at low level and F-OE# is at high level. Address and data are latched on the earlier rising edge of F-WE# and F-CE#. Standard micro-processor write timings are used. Alternating Background Operation (BGO) The Flash Memory of M6MGB/T166S2BWG allows to read array from one bank while the other bank operates in software command write cycling or the erasing / programming operation in the background. Read array operation with the other bank in BGO is performed by changing the bank address without any additional command. When the bank address points the bank in software command write cycling or the erasing / programming operation, the data is read out from the status register. The access time with BGO is the same as the normal read operation. Output Disable When F-OE# is at VIH, output from the devices is disabled. Data input/output are in a high-impedance(High-Z) state. Standby When F-CE# is at VIH, the device is in the standby mode and its power consumption is reduced. Data input/output are in a high-impedance(High-Z) state. If the memory is deselected during block erase or program, the internal control circuits remain active and the device consume normal active power until the operation completes. 4 Nov 1999 , Rev.2.3 MITSUBISHI LSIs M6MGB/T166S2BWG 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS 3.3V-ONLY FLASH MEMORY & 2,097,152-BIT (131,072-WORD BY 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) SOFTWARE COMMAND DEFINITIONS The device operations are selected by writing specific software command into the Command User Interface. Read Array Command (FFH) The device is in Read Array mode on initial device power up and after exit from deep powerdown, or by writing FFH to the Command User Interface. After starting the internal operation the device is set to the read status register mode automatically. Read Device Identifier Command (90H) It can normally read device identifier codes when Read Device Identifier Code Command(90H) is written to the command latch. Following the command write, the manufacturer code and the device code can be read from address 00000H and 00001H, respectively. Read Status Register Command (70H) The Status Register is read after writing the Read Status Register command of 70H to the Command User Interface. Also, after starting the internal operation the device is set to the Read Status Register mode automatically. The contents of Status Register are latched on the later falling edge of F-OE# or F-CE#. So F-CE# or F-OE# must be toggled every status read. Clear Status Register Command (50H) The Erase Status, Program Status and Block Status bits are set to "1"s by the Write State Machine and can only be reset by the Clear Status Register command of 50H. These bits indicates various failure conditions. C)Single Data Load to Page Buffer (74H) / Page Buffer to Flash (0EH/D0H) Single data load to the page buffer is performed by writing 74H followed by a second write specifying the column address and data. Distinct data up to 128word can be loaded to the page buffer by this two-command sequence. On the other hand, all of the loaded data to the page buffer is programed simultaneously by writing Page Buffer to Flash command of 0EH followed by the confirm command of D0H. After completion of programing the data on the page buffer is cleared automatically. This command is valid for only Bank(I) alike Word/Byte Program. Clear Page Buffer Command (55H) Loaded data to the page buffer is cleared by writing the Clear Page Buffer command of 55H followed by the Confirm command of D0H. This command is valid for clearing data loaded by Single Data Load to Page Buffer command. Suspend/Resume Command (B0H/D0H) Writing the Suspend command of B0H during block erase operation interrupts the block erase operation and allows read out from another block of memory. Writing the Suspend command of B0H during program operation interrupts the program operation and allows read out from another block of memory. The Bank address is required when writing the Suspend/Resume Command. The device continues to output Status Register data when read, after the Suspend command is written to it. Polling the WSM Status and Suspend Status bits will determine when the erase operation or program operation has been suspended. At this point, writing of the Read Array command to the CUI enables reading data from blocks other than that which is suspended. When the Resume command of D0H is written to the CUI, the WSM will continue with the erase or program processes. DATA PROTECTION Block Erase / Confirm Command (20H/D0H) Automated block erase is initiated by writing the Block Erase command of 20H followed by the Confirm command of D0H. An address within the block to be erased is required. The WSM executes iterative erase pulse application and erase verify operation. Program Commands A)Word Program (40H) Word program is executed by a two-command sequence. The Word Program Setup command of 40H is written to the Command Interface, followed by a second write specifying the address and data to be written. The WSM controls the program pulse application and verify operation. The Word Program Command is valid for only Bank(I). B)Page Program for Data Blocks (41H) Page Program for Bank(I) and Bank(II) allows fast programming of 128words of data. Writing of 41H initiates the page program operation for the Data area. From 2nd cycle to 129th cycle, write data must be serially inputted. Address A6-A0 have to be incremented from 00H to 7FH. After completion of data loading, the WSM controls the program pulse application and verify operation. 5 The Flash Memory of M6MGB/T166S2BWG provides selectable block locking of memory blocks. Each block has an associated nonvolatile lock-bit which determines the lock status of the block. In addition, the Flash Memory has a master Write Protect pin (F-WP#) which prevents any modifications to memory blocks whose lock-bits are set to "0", when F-WP# is low. When F-WP# is high, all blocks can be programmed or erased regardless of the state of the lock-bits, and the lock-bits are cleared to "1" by erase. See the BLOCK LOCKING table on P.9 for details. Power Supply Voltage When the power supply voltage (F-VCC) is less than VLKO, Low V CC Lock-Out voltage, the device is set to the Read-only mode. Regarding DC electrical characteristics of VLKO, see P.10. A delay time of 2ms is required before any device operation is initiated. The delay time is measured from the time F-Vcc reaches F-Vccmin (2.7V). During power up, F-RP#=GND is recommended. Falling in Busy status is not recommended for possibility of damaging the device. MEMORY ORGANIZATION The Flash Memory of M6MGB/T166S2BWG has one 16Kword boot block, seven 16Kword parameter blocks, for Bank(I) and twenty-eight 32Kword main blocks for Bank(II). A block is erased independently of other blocks in the array. Nov 1999 , Rev.2.3 MITSUBISHI LSIs M6MGB/T166S2BWG 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS 3.3V-ONLY FLASH MEMORY & 2,097,152-BIT (131,072-WORD BY 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) MEMORY ORGANIZATION F0000H-F7FFFH 32Kword MAIN BLOCK 34 F8000H-FBFFFH 16Kword PARAMETER BLOCK 34 E8000H-EFFFFH 32Kword MAIN BLOCK 33 F4000H-F7FFFH 16Kword PARAMETER BLOCK 33 E0000H-E7FFFH 32Kword MAIN BLOCK 32 F0000H-F3FFFH 16Kword PARAMETER BLOCK 32 D8000H-DFFFFH 32Kword MAIN BLOCK 31 EC000H-EFFFFH 16Kword PARAMETER BLOCK 31 D0000H-D7FFFH 32Kword MAIN BLOCK 30 E8000H-EBFFFH 16Kword PARAMETER BLOCK 30 C8000H-CFFFFH 32Kword MAIN BLOCK 29 E4000H-E7FFFH 16Kword PARAMETER BLOCK 29 C0000H-C7FFFH 32Kword MAIN BLOCK 28 E0000H-E3FFFH 16Kword PARAMETER BLOCK 28 B8000H-BFFFFH 32Kword MAIN BLOCK 27 D8000H-DFFFFH 32Kword MAIN BLOCK 27 B0000H-B7FFFH 32Kword MAIN BLOCK 26 D0000H-D7FFFH 32Kword MAIN BLOCK 26 A8000H-AFFFFH 32Kword MAIN BLOCK 25 C8000H-CFFFFH 32Kword MAIN BLOCK 25 A0000H-A7FFFH 32Kword MAIN BLOCK 24 C0000H-C7FFFH 32Kword MAIN BLOCK 24 98000H-9FFFFH 32Kword MAIN BLOCK 23 B8000H-BFFFFH 32Kword MAIN BLOCK 23 90000H-97FFFH 32Kword MAIN BLOCK 22 B0000H-B7FFFH 32Kword MAIN BLOCK 22 88000H-8FFFFH 32Kword MAIN BLOCK 21 A8000H-AFFFFH 32Kword MAIN BLOCK 21 32Kword MAIN BLOCK 20 78000H-7FFFFH 32Kword MAIN BLOCK 19 98000H-9FFFFH 32Kword MAIN BLOCK 19 70000H-77FFFH 32Kword MAIN BLOCK 18 90000H-97FFFH 32Kword MAIN BLOCK 18 68000H-6FFFFH 32Kword MAIN BLOCK 17 88000H-8FFFFH 32Kword MAIN BLOCK 17 60000H-67FFFH 32Kword MAIN BLOCK 16 80000H-87FFFH 32Kword MAIN BLOCK 16 58000H-5FFFFH 32Kword MAIN BLOCK 15 78000H-7FFFFH 32Kword MAIN BLOCK 15 50000H-57FFFH 32Kword MAIN BLOCK 14 70000H-77FFFH 32Kword MAIN BLOCK 14 48000H-4FFFFH 32Kword MAIN BLOCK 13 68000H-6FFFFH 32Kword MAIN BLOCK 13 40000H-47FFFH 32Kword MAIN BLOCK 12 60000H-67FFFH 32Kword MAIN BLOCK 12 38000H-3FFFFH 32Kword MAIN BLOCK 11 58000H-5FFFFH 32Kword MAIN BLOCK 11 30000H-37FFFH 32Kword MAIN BLOCK 10 50000H-57FFFH 32Kword MAIN BLOCK 10 28000H-2FFFFH 32Kword MAIN BLOCK 9 48000H-4FFFFH 32Kword MAIN BLOCK 9 20000H-27FFFH 32Kword MAIN BLOCK 8 40000H-47FFFH 32Kword MAIN BLOCK 8 1C000H-1FFFFH 16Kword PARAMETER BLOCK 7 38000H-3FFFFH 32Kword MAIN BLOCK 7 18000H-1BFFFH 16Kword PARAMETER BLOCK 6 30000H-37FFFH 32Kword MAIN BLOCK 6 14000H-17FFFH 16Kword PARAMETER BLOCK 5 28000H-2FFFFH 32Kword MAIN BLOCK 5 10000H-13FFFH 16Kword PARAMETER BLOCK 4 20000H-27FFFH 32Kword MAIN BLOCK 4 0C000H-0FFFFH 16Kword PARAMETER BLOCK 3 18000H-1FFFFH 32Kword MAIN BLOCK 3 08000H-0BFFFH 16Kword PARAMETER BLOCK 2 10000H-17FFFH 32Kword MAIN BLOCK 2 04000H-07FFFH 16Kword PARAMETER BLOCK 1 08000H-0FFFFH 32Kword MAIN BLOCK 1 00000H-07FFFH 32Kword MAIN BLOCK 0 16Kword BOOT BLOCK 0 BANK(II) 32Kword MAIN BLOCK 20 A0000H-A7FFFH BANK(I) 80000H-87FFFH BANK(I) FC000H-FFFFFH BANK(II) 32Kword MAIN BLOCK 35 00000H-03FFFH F-A19-F-A17,A16-A0 F-A19-F-A17,A16-A0 Flash Memory of M6MGB166S2BWG Memory Map 6 16Kword BOOT BLOCK 35 F8000H-FFFFFH Flash Memory of M6MGT166S2BWG Memory Map Nov 1999 , Rev.2.3 MITSUBISHI LSIs M6MGB/T166S2BWG 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS 3.3V-ONLY FLASH MEMORY & 2,097,152-BIT (131,072-WORD BY 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) BUS OPERATIONS Bus Operations for Word-Wide Mode Mode Pins Array Status Register Lock Bit Status Identifier Code Output disable Stand by Program Write Erase Others Deep Power Down Read F-CE# VIL VIL VIL VIL VIL VIH VIL VIL VIL X F-OE# VIL VIL VIL VIL VIH X 2) VIH VIH VIH X F-WE# F-RP# DQ0-15 F-RY/BY# VIH VIH VIH VIH VIH X VIL VIL VIL X VIH VIH VIH VIH VIH VIH VIH VIH VIH VIL Data out Status Register Data Lock Bit Data (DQ6) Identifier Code Hi-Z Hi-Z Command/Data in Command Command Hi-Z VOH (Hi-Z) X 1) X VOH (Hi-Z) X X X X X VOH (Hi-Z) 1) X at F-RY/BY# is VOL or VOH(Hi-Z). *The F-RY/BY# is an open drain output pin and indicates status of the internal WSM. When low,it indicates that the WSM is Busy performing an operation. A pull-up resistor of 10K-100K Ohms is required to allow the F-RY/BY# signal to transition high indicating a Ready WSM condition. 2) X can be VIH or VIL for control pins. 7 Nov 1999 , Rev.2.3 MITSUBISHI LSIs M6MGB/T166S2BWG 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS 3.3V-ONLY FLASH MEMORY & 2,097,152-BIT (131,072-WORD BY 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) SOFTWARE COMMAND DEFINITION Command List 2nd bus cycle 1st bus cycle Command Read Array Device Identifier Read Status Register Clear Status Register Clear Page Buffer Word Program 5) Page Program 7) Single Data Load to Page Buffer 5) Page Buffer to Flash 5) Block Erase / Confirm Suspend Resume Read Lock Bit Status Lock Bit Program / Confirm Erase All Unlocked Blocks Mode Address Write Write Write Write Write Write Write Write Write Write Write Write Write X X Bank3) X X Bank(I) 5) Bank Bank(I) 5) Bank(I) 5) Bank Bank Bank X Bank X Write Write Data (DQ15-0) FFH 90H 70H 50H 55H 40H 41H 74H 0EH 20H B0H D0H 71H 77H A7H Mode Address 3rd ~129th bus cycles (Word Mode) Data Read IA 2) Read Bank ID 2) SRD4) Write Write Write Write Write Write X WA 6) WA0 7) WA WA 8) BA 9) D0H 1) WD 6) WD0 7) WD D0H 1) D0H 1) Read Write Write BA BA X Mode Address Write WAn 7) (DQ15-0) Data (DQ15-0) WDn 7) DQ6 10) D0H 1) D0H 1) 1) Upper byte data (DQ8-DQ15) is ignored. 2) IA=ID Code Address : A0=VIL (Manufacturer's Code) : A0=VIH (Device Code), ID=ID Code 3) Bank = Bank Address (Bank(I) or Bank(II)) : F-A19-F-A17. 4) SRD = Status Register Data 5) Word Program, Single Data Load and Page Buffer to Flash Command is valid for only Bank(I). 6) WA = Write Address,WD = Write Data 7) WA0,WAn=Write Address, WD0,WDn=Write Data. Write Address and Write Data must be provided sequentially from 00H to 7FH for A6-A0. Page size is 128word (128word x 16bit). and also F-A19-F-A17,A16-A7(Block Address, Page Address) must be valid. 8) WA = Write Address : Upper page address, F-A19-F-A17,A16-A7(Block Address, Page Address) must be valid. 9) BA = Block Address : BA = Block Address : F-A19-F-A17,A16-A14(Bank1) F-A19-F-A17,A16-A15(Bank2) 10) DQ6 provides Block Lock Status, DQ6 = 1 : Block Unlock, DQ6 = 0 : Block Locked. 8 Nov 1999 , Rev.2.3 MITSUBISHI LSIs M6MGB/T166S2BWG 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS 3.3V-ONLY FLASH MEMORY & 2,097,152-BIT (131,072-WORD BY 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) BLOCK LOCKING Lock Bit F-RP# F-WP# (Internally) VIL X VIL VIH VIH X 0 1 X Write Protection Provided BANK(I) BANK(II) Note Lock Bit Boot Parameter Data Locked Locked Locked Locked Deep Power Down Mode Locked Locked Locked Locked Locked Locked Unlocked Unlocked Unlocked Unlocked Unlocked Unlocked All Blocks Unlocked 1) DQ6 provides Lock Status of each block after writing the Read Lock Status command (71H). F-WP# pins must not be switched during performing Erase / Write operations or WSM Busy (WSMS = 0). 2) Erase/Write command for locked blocks is aborted. At this time read mode is not array read mode but status read mode and 00B0H is read. Please issue Clear Status Register command plus Read Array command to change the mode from status read mode to array read mode. STATUS REGISTER Symbol SR.7 SR.6 SR.5 SR.4 SR.3 SR.2 SR.1 SR.0 (DQ7) (DQ6) (DQ5) (DQ4) (DQ3) (DQ2) (DQ1) (DQ0) Status Write State Machine Status Suspend Status Erase Status Program Status Block Status after Program Reserved Reserved Reserved Definition "1" Ready Suspended Error Error Error - "0" Busy Operation in Progress / Completed Successful Successful Successful - *The F-RY/BY# is an open drain output pin and indicates status of the internal WSM. When low,it indicates that the WSM is Busy performing an operation. A pull-up resistor of 10K-100K Ohms is required to allow the F-RY/BY# signal to transition high indicating a Ready WSM condition. *DQ3 indicates the block status after the page programming, word programming and page buffer to flash. When DQ3 is "1", the page has the over-programed cell . If over-program occurs, the device is block fail. However if DQ3 is "1", please try the block erase to the block. The block may revive. 9 Nov 1999 , Rev.2.3 MITSUBISHI LSIs M6MGB/T166S2BWG 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS 3.3V-ONLY FLASH MEMORY & 2,097,152-BIT (131,072-WORD BY 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) DEVICE IDENTIFIER CODE Pins A0 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Hex. Data Manufacturer Code VIL 0 0 0 1 1 1 0 0 1CH Device Code (-T166S2BWG) VIH 1 0 1 0 0 0 0 0 A0H Device Code (-B166S2BWG) VIH 1 0 1 0 0 0 0 1 A1H Code The upper data(D15-8) is "0". ABSOLUTE MAXIMUM RATINGS Symbol F-Vcc Conditions Min Max Unit With respect to Ground -0.2 -0.6 4.6 4.6 V V VI1 Parameter Flash Vcc voltage All input or output voltage 1) Ta Ambient temperature -40 85 °C Tbs Temperature under bias -50 95 °C Tstg I OUT Storage temperature Output short circuit current -65 125 100 °C mA 1) Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input/output pins is (F-VCC)+0.5V which, during transitions, may overshoot to (F-VCC)+1.5V for periods <20ns. CAPACITANCE Parameter Symbol CIN COUT Test conditions Input capacitance (Address, Control Pins) Output capacitance Min Limits Typ Ta = 25°C, f = 1MHz, Vin = Vout = 0V Max 8 12 Unit pF pF Note: The value of common pins to Flash Memory is the sum of Flash Memory and SRAM. DC ELECTRICAL CHARACTERISTICS (Ta = -40~ 85°C, F-Vcc = 2.7V ~ 3.6V, unless otherwise noted) Symbol ILI ILO ISB1 ISB2 ISB3 ISB4 Parameter Unit Input leakage current Output leakage current 0V£VIN£F-VCC F-VCC = 3.6V, VIN=VIL/VIH, F-CE# = F-RP# =F-WP# = VIH 50 F-VCC standby current F-VCC = 3.6V, VIN=GND or F-VCC, F-CE# = F-RP# = F-WP# = (F-VCC)±0.3V 0.1 5 mA 5 15 mA 0.1 8 2 5 15 4 mA F-VCC deep powerdown current 0V£VOUT£F-VCC F-VCC = 3.6V, VIN=VIL/VIH, F-RP# = VIL F-VCC = 3.6V, VIN=GND or F-VCC, F-RP# =GND±0.3V F-VCC = 3.6V, VIN=VIL/VIH, F-CE# = VIL, read current for Word or Byte F-RP#=F-OE#=VIH, IOUT = 0mA F-VCC ICC2 F-VCC Write current for Word or Byte F-VCC program current F-VCC erase current F-VCC suspend current Input low voltage Input high voltage Output low voltage Output high voltage Low VCC Lock-Out voltage 2) Min Limits Typ1) Max ±2.0 ±11 200 ICC1 ICC3 ICC4 ICC5 VIL VIH VOL VOH1 VOH2 VLKO Test conditions 5MHz 1MHz F-VCC = 3.6V,VIN=VIL/VIH, F-CE# =F-WE#= VIL, F-RP#=F-OE#=VIH F-VCC = 3.6V, VIN=VIL/VIH, F-CE# = F-RP# =F-WP# = VIH F-VCC = 3.6V, VIN=VIL/VIH, F-CE# = F-RP# =F-WP# = VIH F-VCC = 3.6V, VIN=VIL/VIH, F-CE# = F-RP# =F-WP# = VIH – 0.5 2.0 IOL = 4.0mA IOH = –2.0mA IOH = –100mA mA 15 mA 35 35 200 0.8 mA mA mA V V V V V V (F-Vcc)+0.5 0.45 0.85X(F-Vcc) (F-Vcc)–0.4 1.5 mA mA mA 2.2 All currents are in RMS unless otherwise noted. 1) Typical values at F-Vcc=3.3V, Ta=25°C 2) To protect against initiation of write cycle during F-Vcc power-up/ down, a write cycle is locked out for F-Vcc less than VLKO. If F-Vcc is less than VLKO, Write State Machine is reset to read mode. When the Write State Machine is in Busy state, if F-Vcc is less than VLKO, the alteration of memory contents may occur. 10 Nov 1999 , Rev.2.3 MITSUBISHI LSIs M6MGB/T166S2BWG 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS 3.3V-ONLY FLASH MEMORY & 2,097,152-BIT (131,072-WORD BY 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) AC ELECTRICAL CHARACTERISTICS (Ta = -40 ~85°C, F-Vcc = 2.7V ~3.6V) Read-Only Mode Limits Symbol F-Vcc=2.7-3.6V Parameter tRC tAVAV ta (AD) ta (CE) ta (OE) tCLZ tDF(CE) tOLZ tDF(OE) tPHZ tAVQV tELQV tGLQV tELQX tEHQZ tGLQX tGHQZ tPLQZ tOH tOH tPS tPHEL Read cycle time Address access time Chip enable access time Output enable access time Chip enable to output in low-Z Chip enable high to output in high Z Output enable to output in low-Z Output enable high to output in high Z F-RP# low to output high-Z Output hold from F-CE#, F-OE#, addresses F-RP# recovery to F-CE# low Unit 90ns Min 90 Typ Max 25 ns ns ns ns ns ns ns ns 150 ns 90 90 30 0 25 0 0 ns 150 ns Timing measurements are made under AC waveforms for read operations. AC ELECTRICAL CHARACTERISTICS (Ta = -40 ~85°C, F-Vcc = 2.7V ~3.6V) Write Mode (F-WE# control) Symbol tWC tAS tAH tDS tDH tOEH Limits F-Vcc=2.7-3.6V Parameter tRE tCS tCH tWP tWPH tGHWL tBLS tBLH tAVAV tAVWH tWHAX tDVWH tWHDX tWHGL tELWL tWHEH Write cycle time Address set-up time Address hold time Data set-up time Data hold time F-OE# hold from F-WE# high Latency between Read and Write FFH or 71H Chip enable set-up time Chip enable hold time tWLWH tWHWL tGHWL tPHHWH tQVPH Write pulse width Write pulse width high F-OE# hold to F-WE# Low Block Lock set-up to write enable high Block Lockhold from valid SRD tDAP tDAE tWHRL tPS tWHRH1 tWHRH2 tWHRL tPHWL Duration of auto-program operation Duration of auto-block erase operation Write enable high to F-RY/BY# low F-RP# high recovery to write enable low Min 90 50 0 50 0 90ns Typ Unit Max ns ns ns ns ns ns ns 10 30 0 0 50 30 0 90 0 150 ns ns ns ns ns ns ns 4 80 40 600 90 ms ms ns ns Read timing parameters during command write operations mode are the same as during read-only operations mode. Typical values at F-Vcc=3.3V, Ta=25°C 11 Nov 1999 , Rev.2.3 MITSUBISHI LSIs M6MGB/T166S2BWG 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS 3.3V-ONLY FLASH MEMORY & 2,097,152-BIT (131,072-WORD BY 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) AC ELECTRICAL CHARACTERISTICS (Ta = -40 ~ 85°C, F-Vcc = 2.7V ~ 3.6V) Write Mode (F-CE# control) Parameter Symbol tWC tAS tAH tDS tDH tOEH tRE tWS tWH tCEP tCEPH tGHEL tBLS tAVAV tAVWH tEHAX tDVWH tEHDX tEHGL - Write cycle time Address set-up time Address hold time Data set-up time Data hold time F-OE# hold from F-CE# high Latency between Read and Write FFH or 71H Write enable set-up time Write enable hold time F-CE# pulse width tBLH tWLEL tEHWH tELEH tEHEL tGHEL tPHHEH tQVPH tDAP tDAE tEHRL tPS tEHRH1 tEHRH2 Duration of auto-block erase operation tEHRL F-CE# high to F-RY/BY# low tPHWL F-RP# high recovery to write enable low F-CE# pulse width high F-OE# hold to F-CE# Low Block Lock set-up to write enable high Block Lockhold from valid SRD Duration of auto-program operation Min 90 50 0 50 0 Limits F-Vcc=2.7-3.6V 90ns Typ Max Unit ns ns ns ns ns ns ns 10 30 0 0 60 30 90 90 0 ns ns ns ns ns ns ns 4 80 40 600 90 ms ms ns ns 150 Read timing parameters during command write operation mode are the same as during read-only operation mode. Typical values at F-Vcc=3.3V, Ta=25°C Erase and Program Performance Min Parameter Block Erase Time Main Block Write Time (Page Mode) Page Write Time Typ Max Unit 40 1.0 4 600 1.8 80 ms sec ms Typ Max Unit 15 15 ms Max Unit Program Suspend Latency / Erase Suspend Time Min Parameter Program Suspend Latency Erase Suspend Time ms Please see page 20. Vcc Power Up / Down Timing Symbol tVCS Parameter F-RP# =VIH set-up time from Vccmin Min 2 Typ ms Please see page 13. During power up/down, by the noise pulses on control pins, the device has possibility of accidental erasure or programming. The device must be protected against initiation of write cycle for memory contents during power up/down. The delay time of min.2msec is always required before read operation or write operation is initiated from the time F-Vcc reaches F-Vccmin during power up/down. By holding F-RP# VIL, the contents of memory is protected during F-Vcc power up/down. During power up, F-RP# must be held VIL for min.2ms from the time F-Vcc reaches F-Vccmin. During power down, F-RP# must be held VIL until Vcc reaches GND. F-RP# doesn't have latch mode ,therefore F-RP# must be held VIH during read operation or erase/program operation. 12 Nov 1999 , Rev.2.3 MITSUBISHI LSIs M6MGB/T166S2BWG 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS 3.3V-ONLY FLASH MEMORY & 2,097,152-BIT (131,072-WORD BY 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) Vcc POWER UP / DOWN TIMING Read /Write Inhibit Read /Write Inhibit F-VCC Read /Write Inhibit 3.3V GND tVCS F-RP# VIH VIL F-CE# VIH VIL F-WE# tPS tPS VIH VIL AC WAVEFORMS FOR READ OPERATION AND TEST CONDITIONS TEST CONDITIONS FOR AC CHARACTERISTICS VIH ADDRESSES ADDRESS VALID VIL F-CE# ta (AD) VIL F-OE# tRE tDF(CE) ta (CE) VIH VIL F-WE# Input voltage : VIL = 0V, VIH = 3.0V Input rise and fall times : £5ns Reference voltage at timing measurement : 1.5V tRC VIH Output load : 1TTL gate + CL(30pF) or tDF(OE) tOEH VIH ta (OE) VIL tOH tOLZ DATA VOH VOL F-RP# tCLZ HIGH-Z OUTPUT VALID tPS 1.3V HIGH-Z 1N914 tPHZ VIH 3.3kW DUT VIL CL =30pF AC WAVEFORMS FOR WRITE FFH or 71H AND READ OPERATION VIH ADDRESSES ADDRESS VALID VIL F-CE# tRC VIH ta (AD) VIL F-OE# ta (CE) VIH VIL F-WE# tRE tDF(OE) VIH ta (OE) VIL DATA VOH HIGH-Z FFH or 71H Valid VOL tPS F-RP# tDF(CE) VIH tOH tOLZ tCLZ OUTPUT VALID HIGH-Z tPHZ VIL In the case of application F-CE# is Low fixed, it is allowed to define a timming specification of tRE from rising edge of F-WE# to falling edge of F-OE#, and valid data is read after spec of tRE+ta(CE). (This is only for FFH,71H program and read) 13 Nov 1999 , Rev.2.3 MITSUBISHI LSIs M6MGB/T166S2BWG 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS 3.3V-ONLY FLASH MEMORY & 2,097,152-BIT (131,072-WORD BY 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) AC WAVEFORMS FOR PAGE PROGRAM OPERATION (F-WE# control) The other bank address F-A19~F-A17, VIH A16~A7 VIL BANK ADDRESS VALID VALID VALID 00H VALID PROGRAM READ STATUS WRITE READ REGISTER ARRAY COMMAND ADDRESS VALID BANK ADDRESS VALID VIH A6 ~A0 VIL tWC F-CE# tCS F-OE# ta(CE) ta(CE) tCH ta(OE) tWPH VIH tWP VIH tDAP tDH tDS 41H tOEH tGHWL ta(OE) tOEH VIL DATA 7FH VIH VIL F-WE# tAH tAS VIH VIL 01H~7EH DOUT DIN DIN F-RY/BY# SRD DIN VIL FFH tWHRL VOH VOL tPS F-RP# VIH VIL F-WP# tBLH tBLS VIH VIL AC WAVEFORMS FOR PAGE PROGRAM OPERATION (F-CE# control) F-A19~F-A17, VIH A16~A7 VIL The other bank address BANK ADDRESS VALID VALID VALID 00H VALID VIH A6 ~A0 VIL tWC F-CE# F-OE# tCEPH tOEH tWH 7FH ta(CE) ta(OE) tOEH tGHEL tDAP VIH tDH tDS VIH 41H DIN VIL F-RY/BY# 01H~7EH BANK ADDRESS VALID ta(OE) VIL DATA ADDRESS VALID tCEP tWS READ STATUS WRITE READ REGISTER ARRAY COMMAND tAH ta(CE) VIH VIL F-WE# tAS VIH VIL PROGRAM DOUT DIN DIN SRD FFH tEHRL VOH VOL tPS F-RP# VIH VIL VIH F-WP# 14 tBLS tBLH VIL Nov 1999 , Rev.2.3 MITSUBISHI LSIs M6MGB/T166S2BWG 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS 3.3V-ONLY FLASH MEMORY & 2,097,152-BIT (131,072-WORD BY 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) AC WAVEFORMS FOR WORD PROGRAM OPERATION (F-WE# control) (to only BANK(I)) PROGRAM VIH VIL F-CE# tWC tAS tCS VIL F-WE# tAH tCH tWP VIH WRITE READ ARRAY COMMAND BANK(I) ADDRESS VALID ta(CE) VIH VIL F-OE# ADDRESS VALID BANK ADDRESS VALID ADDRESSES READ STATUS REGISTER ta(OE) tOEH tWPH VIH VIL tDS VIH DATA 40H DIN SRD FFH VIL tDH VIH F-RY/BY# tWHRL VIL tPS VIH F-RP# tDAP VIL F-WP# tBLS tBLH VIH VIL AC WAVEFORMS FOR WORD PROGRAM OPERATION (F-CE# control) VIH ADDRESSES VIL F-CE# PROGRAM BANK ADDRESS VALID tWC ADDRESS VALID tAS (to only BANK(I)) READ STATUS REGISTER WRITE READ ARRAY COMMAND BANK(I) ADDRESS VALID tAH ta(CE) VIH VIL F-OE# VIL F-WE# ta(OE) VIH tCEP tWS tOEH tWH VIH VIL tDS VIH 40H DATA DIN SRD FFH VIL tDH VIH F-RY/BY# VIL VIH F-RP# F-WP# VIL tEHRL tPS tDAP tBLS tBLH VIH VIL 15 Nov 1999 , Rev.2.3 MITSUBISHI LSIs M6MGB/T166S2BWG 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS 3.3V-ONLY FLASH MEMORY & 2,097,152-BIT (131,072-WORD BY 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) AC WAVEFORMS FOR ERASE OPERATIONS (F-WE# control) ERASE VIH BANK ADDRESS VALID ADDRESSES VIL tAH tAS ta(CE) VIH VIL tCS tCH ta(OE) VIH F-OE# VIL tOEH tWPH tDAE VIH F-WE# VIL tWP F-RY/BY# tDH tDS VIH DATA WRITE READ ARRAY COMMAND BANK ADDRESS VALID ADDRESS VALID tWC F-CE# READ STATUS REGISTER 20H SRD D0H VIL FFH tWHRL VOH VOL tPS F-RP# VIH tBLS VIL F-WP# tBLH VIH VIL AC WAVEFORMS FOR ERASE OPERATIONS (F-CE# control) ERASE ADDRESSES VIH VIL BANK ADDRESS VALID ADDRESS VALID tWC tAH tAS ta(CE) VIL tCEPH tCEP ta(OE) VIH F-OE# tOEH VIL tWS VIL F-RY/BY# tDH tDS VIH DATA tDAE tWH VIH F-WE# WRITE READ ARRAY COMMAND BANK ADDRESS VALID VIH F-CE# READ STATUS REGISTER 20H VIL SRD D0H FFH tEHRL VOH VOL tPS F-RP# VIH VIL F-WP# 16 tBLS tBLH VIH VIL Nov 1999 , Rev.2.3 MITSUBISHI LSIs M6MGB/T166S2BWG 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS 3.3V-ONLY FLASH MEMORY & 2,097,152-BIT (131,072-WORD BY 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) AC WAVEFORMS FOR PAGE PROGRAM OPERATION WITH BGO (F-WE# control) Change Bank Address ARRAY READ FROM THE OTHER BANK WITH BGO PROGRAM DATA TO ONE BANK F-A19~F-A17, VIH A16~A7 VIL BANK ADDRESS VALID ~ ~ ~ ~ ADDRESS VALID VIH VIL F-OE# tWC tAS VIH tCS ta(OE) tOEH VIH ~ ~ F-WE# VIL 41H ~ ~ tDS VIH DATA DIN DIN DIN SRD VIL DOUT DOUT tWHRL tDH VIH F-RY/BY# VALID ta(CE) tWP tWPH VIL VALID tAH tCH VIH 7FH VALID ~ ~ ~ ~ VIL F-CE# 01H~7EH 00H A6 ~A0 VALID VIL AC WAVEFORMS FOR PAGE PROGRAM OPERATION WITH BGO (F-CE# control) Change Bank Address PROGRAM DATA TO ONE BANK F-A19~F-A17, VIH A16~A7 VIL BANK ADDRESS VALID ~ ~ ~ ~ ADDRESS VALID VIH F-CE# tWC VIH VIL tCEP VALID VALID ta(OE) tOEH tWS tCH VIL 41H DIN ~ ~ tDS VIH DIN VIL VIH VALID ta(CE) tAH tCEPH VIH DATA 7FH VALID ~ ~ F-WE# tAS VIH VIL F-OE# 01H~7EH 00H VIL ~ ~ ~ ~ A6 ~A0 ARRAY READ FROM THE OTHER BANK WITH BGO tDH DIN SRD DOUT DOUT tEHRL F-RY/BY# VIL 17 Nov 1999 , Rev.2.3 MITSUBISHI LSIs M6MGB/T166S2BWG 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS 3.3V-ONLY FLASH MEMORY & 2,097,152-BIT (131,072-WORD BY 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) AC WAVEFORMS FOR WORD PROGRAM OPERATION WITH BGO (F-WE# control) Change Bank Address READ STATUS REGISTER PROGRAM DATA TO BANK(I) F-A19~F-A17, VIH A16~A7 VIL BANK ADDRESS VALID ADDRESS VALID ARRAY READ FROM BANK(II) WITH BGO VALID VALID VALID VALID VIH A6 ~A0 VALID VIL F-CE# tAS tCS tCH VIH ta(OE) tOEH tWP tWPH VIL F-WE# ta(CE) VIH VIL F-OE# tWC tAH VIH VIL tDS VIH 40H DATA DIN SRD DOUT DOUT VIL tDH VIH F-RY/BY# VIL tWHRL AC WAVEFORMS FOR WORD PROGRAM OPERATION WITH BGO (F-CE# control) F-A19~F-A17, VIH A16~A7 VIL PROGRAM DATA TO BANK(I) BANK ADDRESS VALID READ STATUS REGISTER ADDRESS VALID Change Bank Address ARRAY READ FROM BANK(II) WITH BGO VALID VALID VALID VALID VIH A6 ~A0 F-CE# VALID VIL tWC VIH VIL F-WE# ta(CE) tCEPH VIL F-OE# tAS VIH tCEP tWS ta(OE) tOEH tCH VIH VIL tDS VIH 40H DATA DIN SRD DOUT DOUT VIL VIH tDH F-RY/BY# VIL tEHRL 18 Nov 1999 , Rev.2.3 MITSUBISHI LSIs M6MGB/T166S2BWG 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS 3.3V-ONLY FLASH MEMORY & 2,097,152-BIT (131,072-WORD BY 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) AC WAVEFORMS FOR BLOCK ERASE OPERATION WITH BGO (F-WE# control) Change Bank Address BANK ADDRESS VALID ADDRESSES VIL ADDRESS VALID tWC F-CE# tAH tAS tCS tCH VIH VIH VALID VALID ta(OE) tOEH tWP tWPH VIL ARRAY READ FROM THE OTHER BANK WITH BGO ta(CE) VIH VIL F-OE# READ STATUS REGISTER BLOCK ERASE IN ONE BANK VIH F-WE# VIL tDS VIH 20H DATA D0H SRD DOUT DOUT VIL tDH VIH F-RY/BY# VIL tWHRL AC WAVEFORMS FOR BLOCK ERASE OPERATION WITH BGO (F-CE# control) Change Bank Address VIH ADDRESSES VIL F-CE# BLOCK ERASE IN ONE BANK BANK ADDRESS VALID tWC F-OE# ADDRESS VALID tAS tAH VIH tCEPH VIL VIH VIL tCEP tWS READ DATA FROM THE OTHER BANK WITH BGO READ STATUS REGISTER VALID VALID ta(CE) ta(OE) tOEH tCH VIH F-WE# VIL tDS VIH DATA 20H D0H SRD DOUT DOUT VIL VIH tDH F-RY/BY# VIL tEHRL 19 Nov 1999 , Rev.2.3 MITSUBISHI LSIs M6MGB/T166S2BWG 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS 3.3V-ONLY FLASH MEMORY & 2,097,152-BIT (131,072-WORD BY 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) AC WAVEFORMS FOR SUSPEND OPERATION (F-WE# control) READ STATUS REGISTER VIH ADDRESSES VIL BANK ADDRESS VALID tAS tAH VIH F-CE# tCS tCH ta(OE) tOEH VIL Program Suspend Latency VIH F-WE# ta(CE) VIL VIH F-OE# BANK ADDRESS VALID VIL tWP S.R.6,7=1 VIH DATA F-RY/BY# F-RP# VALID SRD B0H VIL VOH VOL VIH tBLS VIL tBLH VIH F-WP# VIL AC WAVEFORMS FOR SUSPEND OPERATION (F-CE# control) READ STATUS REGISTER VIH ADDRESSES VIL BANK ADDRESS VALID tAS tAH VIH F-CE# BANK ADDRESS VALID ta(CE) tCEP VIL ta(OE) VIH F-OE# VIH F-WE# tOEH VIL Program Suspend Latency tWS tWH VIL S.R.6,7=1 VIH DATA F-RY/BY# F-RP# B0H VALID SRD VIL VOH VOL VIH VIL tBLS tBLH VIH F-WP# 20 VIL Nov 1999 , Rev.2.3 MITSUBISHI LSIs M6MGB/T166S2BWG 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS 3.3V-ONLY FLASH MEMORY & 2,097,152-BIT (131,072-WORD BY 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) FULL STATUS CHECK PROCEDURE LOCK BIT PROGRAM FLOW CHART STATUS REGISTER READ SR.4 =1 and SR.5 =1 ? NO START WRITE 77H YES COMMAND SEQUENCE ERROR WRITE D0H BLOCK ADDRESS SR.5 = 0 ? BLOCK ERASE ERROR NO SR.7 = 1 ? YES NO YES SR.4 = 0 ? NO PROGRAM ERROR (PAGE, LOCK BIT) LOCK BIT PROGRAM FAILED SR.4 = 0 ? NO YES YES SR.3 = 0 ? NO PROGRAM ERROR (BLOCK) LOCK BIT PROGRAM SUCCESSFUL YES SUCCESSFUL (BLOCK ERASE, PROGRAM) WORD PROGRAM FLOW CHART PAGE PROGRAM FLOW CHART START START WRITE 40H WRITE 41H n=0 WRITE ADDRESS , DATA SR.7 = 1 ? n = n+1 WRITE ADDRESS n, DATA n STATUS REGISTER READ NO WRITE B0H ? NO n = FFH ? or n = 7FH ? NO YES YES FULL STATUS CHECK IF DESIRED WORD PROGRAM COMPLETED YES STATUS REGISTER READ SUSPEND LOOP WRITE D0H YES SR.7 = 1 ? NO * Word program is admitted to only BANK(I). YES FULL STATUS CHECK IF DESIRED PAGE PROGRAM COMPLETED 21 WRITE B0H ? NO YES SUSPEND LOOP WRITE D0H YES Nov 1999 , Rev.2.3 MITSUBISHI LSIs M6MGB/T166S2BWG 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS 3.3V-ONLY FLASH MEMORY & 2,097,152-BIT (131,072-WORD BY 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) SUSPEND / RESUME FLOW CHART CLEAR PAGE BUFFER START START SUSPEND WRITE B0H WRITE 55H STATUS REGISTER READ WRITE D0H SR.7 = 1? NO PAGE BUFFER CLEAR COMPLETED YES SR.6 =1? PROGRAM / ERASE COMPLETED NO SINGLE DATA LOAD TO PAGE BUFFER YES WRITE FFH START WRITE 74H READ ARRAY DATA WRITE ADDRESS , DATA DONE READING ? NO YES DONE LOADING? NO RESUME WRITE D0H OPERATION RESUMED YES SINGLE DATA LOAD TO PAGE BUFFER COMPLETED * The bank address is required when writing this command. Also, there is no need to suspend the erase or program operation when reading data from the other bank. Please use BGO function. BLOCK ERASE FLOW CHART PAGE BUFFER TO FLASH START START WRITE 20H WRITE 0EH WRITE D0H BLOCK ADDRESS WRITE D0H PAGE ADDRESS STATUS REGISTER READ STATUS REGISTER READ NO NO SR.7 = 1 ? WRITE B0H ? NO YES FULL STATUS CHECK IF DESIRED SUSPEND LOOP SR.7 = 1 ? YES FULL STATUS CHECK IF DESIRED WRITE B0H ? NO YES SUSPEND LOOP WRITE D0H WRITE D0H PAGE BUFFER TO FLASH COMPLETED 22 YES BLOCK ERASE COMPLETED YES Nov 1999 , Rev.2.3 Clear Status Register Read Array Read Status Register 50H 90H Read Device Identifier 70H 70H 70H Change Bank Address (From The Other Bank) 71H 90H Read Lock Status 71H 71H 90H FFH FFH FFH Read Array Setup State Clear Page Buffer Setup D0H 55H WD 0EH 74H Single Data Load to Page Buffer Setup Page Buffer to Flash Setup 41H Page Program Setup D0H OTHER 40H Internal State Word Program Setup WDi i=0-127 WD 20H 77H Lock Bit Program Setup D0H B0H D0H Suspend State Read Array (From The Other Bank) Change Bank Address 70H FFH Read Array 70H MITSUBISHI LSIs Nov 1999 , Rev.2.3 Read State with BGO Read Status Register M6MGB/T166S2BWG B0H OTHER 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS 3.3V-ONLY FLASH MEMORY & 2,097,152-BIT (131,072-WORD BY 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) Read Status Register D0H Erase All Unlocked Blocks Setup OTHER D0H Erase & Verify Read Status Register Change Bank Address Block Erase Setup D0H OTHER Program & Verify Ready A7H OPERATION STATUS and EFFECTIVE COMMAND 23 Read/Standby State MITSUBISHI LSIs M6MGB/T166S2BWG 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS 3.3V-ONLY FLASH MEMORY & 2,097,152-BIT (131,072-WORD BY 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) 2. SRAM The SRAM of M6MGB/T166S2BWG is organized as 131,072-word by 16-bit. These devices operate on a single +2.7~3.6V powersupply, and are directly TTL compatible to both input and output. Its fully static circuit needs no clocks and no refresh, and makes it useful. The operation mode are determined by a combination of the device control inputs , S-LB#,S-UB#,S-CE1#,S-CE2, S-WE# and S-OE#. Each mode is summarized in the function table. A write operation is executed whenever the low level S-WE# overlaps with the low level S-LB# and/or S-UB# and the low level S-CE1#the high level S-CE2. The address A0~A16 must be set up before the write cycle and must be stable during the entire cycle. A read operation is executed by setting S-WE# at a high level and S-OE# at a low level while S-LB# and/or S-UB# and S-CE1# and S-CE2 are in an active state(S-CE1#=L,S-CE2=H). When setting S-LB# at the high level and other pins are in an active stage, upper-byte are in selectable mode in which both reading and writing are enabled, and lower-byte are in non-selectable mode. And when setting S-UB# at a high level and other pins are in an active stage, lower-byte are in a selectable mode and upper-byte are in a non-selectable mode. When setting S-LB# and S-UB# at a high level or S-CE1# at high level or S-CE2 at a low level, the chips are in a nonselectable mode in which both reading and writing are disabled. In this mode, the output stage is in a highimpedance state, allowing OR-tie with other chips and memory expansion by S-LB#,S-UB# and S-CE1#,S-CE2. The power supply current is reduced as low as 0.3mA(25°C,typical), and the memory data can be held at +2V powersupply, enabling battery back-up operation during power failure or power-down operation in the non-selected mode. FUNCTION TABLE S-CE1# S-CE2 24 S-LB# Mode DQ0~7 DQ8~15 Non selection High-Z High-Z X Non selection High-Z High-Z X Non selection High-Z High-Z High-Z High-Z S-UB# S-WE# S-OE# X X X H L X L L X X X H H X X X Icc Standby Standby Standby Standby X X H H X X Non selection L H L H L X Write Din High-Z Active L H L H H Read Dout High-Z Active L H H H High-Z High-Z Active L H L H L H L L X Write High-Z Din Active L H H L H L Read L H H L H H High-Z High-Z L H L L L X Write Din Din Active L H L L H L Read Dout Dout Active L H L L H H High-Z High-Z Active Dout Active High-Z Active Nov 1999 , Rev.2.3 MITSUBISHI LSIs M6MGB/T166S2BWG 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS 3.3V-ONLY FLASH MEMORY & 2,097,152-BIT (131,072-WORD BY 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) ABSOLUTE MAXIMUM RATINGS Symbol S-Vcc VI VO Pd Ta Tstg Conditions With respect to GND Parameter Ratings Units Power dissipation Ta=25°C -0.5* ~ +4.6 -0.5* ~ S-Vcc + 0.5 0 ~ S-Vcc 700 Operating temperature I-version - 40 ~ +85 °C - 65 ~ +150 °C Supply voltage Input voltage With respect to GND With respect to GND Output voltage Storage temperature V mW * -3.0V in case of AC (Pulse width< = 30ns) DC ELECTRICAL CHARACTERISTICS Symbol VIH VIL VOH1 VOH2 VOL II Parameter Limits Conditions Min High-level input voltage Low-level input voltage Low-level output voltage Input leakage current Output leakage current Icc1 Active supply current ( AC,MOS level ) Active supply current Icc2 ( AC,TTL level ) Stand by supply current ( AC,MOS level ) Icc4 Stand by supply current ( AC,TTL level ) CI CO Input capacitance Output capacitance Units (S-Vcc)+0.3V 0.6 V IOL=2mA VI =0 ~ S-Vcc 0.4 +/- 1 S-LB# and S-UB#=VIH or S-CE1#=VIH or S-CE2=VIH or S-OE#=VIH, VI/O=0 ~ S-Vcc +/- 1 < S-LB# and S-UB# < = 0.2V,S-CE1# = 0.2V, > (S-Vcc)-0.2V other inputs < > S-CE2 = = 0.2V or = (S-Vcc)-0.2V Output-open(duty 100%) f= 10MHz f= 1MHz S-LB# and S-UB#=VIL,S-CE1#=VIL, S-CE2=VIH other inputs=VIH or VIL Output-open(duty 100%) S-CE2 <= 0.2V Other inputs=0~S-Vcc f= 10MHz f= 1MHz - 45 5 45 5 60 15 60 15 - 30 +70 ~ +85 °C - +40 ~ +70 °C - - 10 +25 ~ +40 °C - 1 5 - 40 ~ +25 °C - 0.3 2 - - 1.0 S-LB# and S-UB#=VIH or S-CE1#=VIH or S-CE2=VIL Other inputs= 0 ~ S-Vcc CAPACITANCE Parameter Max (S-Vcc)-0.5V Note 1: Direction for current flowing into IC is indicated as positive (no mark) Note 2: Typical value is for S-Vcc=3.0V and Ta=25°C Symbol Typ 2.0 -0.3 * 2.4 High-level output voltage 1 IOH= -0.5mA High-level output voltage 2 IOH= -0.05mA IO Icc3 ( S-Vcc=2.7 ~ 3.6V, unless otherwise noted) mA mA mA mA * -3.0V in case of AC (Pulse width< = 30ns) (S-Vcc=2.7 ~ 3.6V, unless otherwise noted) Limits Conditions VI=GND, VI=25mVrms, f=1MHz VO=GND,VO=25mVrms, f=1MHz Min Typ Max Units 8 10 pF Note: The value of common pins to SRAM is the sum of Flash Memory and SRAM. 25 Nov 1999 , Rev.2.3 MITSUBISHI LSIs M6MGB/T166S2BWG 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS 3.3V-ONLY FLASH MEMORY & 2,097,152-BIT (131,072-WORD BY 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) (S-Vcc=2.7 ~ 3.6V, unless otherwise noted) AC ELECTRICAL CHARACTERISTICS (1) TEST CONDITIONS Supply voltage Input pulse Input rise time and fall time Reference level Output loads 2.7V~3.6V VIH=2.2V, VIL=0.4V 5ns 1TTL DQ CL VOH=VOL=1.5V Transition is measured +- 500mV from steady state voltage.(for ten,tdis) Including scope and jig capacitance Fig.1,CL=30pF CL=5pF (for ten,tdis) Fig.1 Output load (2) READ CYCLE Limits Symbol tCR ta(A) ta(CE1) ta(CE2) ta(LB) ta(UB) ta(OE) tdis(CE1) tdis(CE2) tdis(LB) tdis(UB) tdis(OE) ten(CE1) ten(CE2) tdis(LB) tdis(UB) ten(OE) tV(A) SRAM Parameter Read cycle time Address access time Chip enable 1 access time Chip enable 2 access time Lower Byte control access time Upper Byte control access time Output enable access time Output disable time after S-CE1# high Output disable time after S-CE2 low Output disable time after S-LB# high Output disable time after S-UB# high Output disable time after S-OE high Output enable time after S-CE1# low Output enable time after S-CE2 high Output enable time after S-LB# low Output enable time after S-UB# low Output enable time after S-OE low Data valid time after address Min 85 Units Max 85 85 85 85 85 45 30 30 30 30 30 10 10 10 10 5 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (3) WRITE CYCLE Limits Symbol tCW tw(W) tsu(A) tsu(A-WH) tsu(LB) tsu(UB) tsu(CE1) tsu(CE2) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE) 26 Parameter Write cycle time Write pulse width Address setup time Address setup time with respect to S-WE# Lower Byte control setup time Upper Byte control setup time Chip enable 1 setup time Chip enable 2 setup time Data setup time Data hold time Write recovery time Output disable time from S-WE# low Output disable time from S-OE# high Output enable time from S-WE# high Output enable time from S-OE# low Units SRAM Min 85 50 0 70 70 70 70 70 35 0 0 Max 30 30 5 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Nov 1999 , Rev.2.3 MITSUBISHI LSIs M6MGB/T166S2BWG 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS 3.3V-ONLY FLASH MEMORY & 2,097,152-BIT (131,072-WORD BY 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) (4)TIMING DIAGRAMS Read cycle tCR A0~16 ta(A) ta(LB) S-LB#, S-UB# tv ta(UB) or (Note3) (A) tdis (LB) or tdis (UB) (Note3) ta(CE1) S-CE1# (Note3) tdis (CE1) (Note3) tdis (CE2) (Note3) ta(CE2) S-CE2 (Note3) ta (OE) S-OE# (Note3) ten (OE) S-WE# = "H" level tdis (OE) ten (LB) ten (UB) ten (CE1) ten (CE2) DQ0~15 (Note3) VALID DATA Write cycle (S-WE# control mode) tCW A0~16 tsu (LB) or tsu(UB) S-LB#, S-UB# (Note3) (Note3) tsu (CE1) S-CE1# (Note3) (Note3) S-CE2 tsu (CE2) (Note3) (Note3) S-OE# tsu (A) tsu (A-WH) tw (W) trec (W) tdis (W) S-WE# ten(OE) ten (W) tdis(OE) DQ0~15 DATA IN STABLE tsu (D) 27 th (D) Nov 1999 , Rev.2.3 MITSUBISHI LSIs M6MGB/T166S2BWG 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS 3.3V-ONLY FLASH MEMORY & 2,097,152-BIT (131,072-WORD BY 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) Write cycle (S-LB#,S-UB# control mode) tCW A0~16 tsu (A) tsu (LB) or tsu(UB) trec (W) S-LB#, S-UB# S-CE1# (Note3) (Note3) S-CE2 (Note3) S-WE# (Note3) (Note5) (Note4) (Note3) (Note3) tsu (D) DQ0~15 th (D) DATA IN STABLE Note 3: Hatching indicates the state is "don't care". Note 4: A Write occurs during S-CE1# low, S-CE2 high overlaps S-LB# and/or S-UB# low and S-WE# low. Note 5: When the falling edge of S-WE# is simultaneously or prior to the falling edge of S-LB# and/or S-UB# or the falling edge of S-CE1# or rising edge of S-CE2, the outputs are maintained in the high impedance state. Note 6: Don't apply inverted phase signal externally when DQ pin is in output mode. 28 Nov 1999 , Rev.2.3 MITSUBISHI LSIs M6MGB/T166S2BWG 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS 3.3V-ONLY FLASH MEMORY & 2,097,152-BIT (131,072-WORD BY 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) Write cycle (S-CE1# control mode) tCW A0~16 S-LB#, S-UB# (Note3) tsu (A) trec (W) tsu (CE1) (Note3) S-CE1# S-CE2 (Note3) (Note3) (Note5) S-WE# (Note4) (Note3) tsu (D) DQ0~15 th (D) (Note3) DATA IN STABLE Write cycle (S-CE2 control mode) tCW A0~16 S-LB#, S-UB# (Note3) tsu (A) tsu (CE2) trec (W) (Note3) S-CE1# S-CE2 (Note3) (Note3) (Note5) S-WE# (Note4) (Note3) DQ0~15 29 tsu (D) th (D) (Note3) DATA IN STABLE Nov 1999 , Rev.2.3 MITSUBISHI LSIs M6MGB/T166S2BWG 16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS 3.3V-ONLY FLASH MEMORY & 2,097,152-BIT (131,072-WORD BY 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS Symbol Parameter Test conditions Min S-Vcc (PD) Power down supply voltage VI (S-BC) Byte control input S-LB#,S-UB# VI (S-CE1#) Chip enable input S-CE1# Limits Typ S-Vcc=3.0V S-CE2 < = 0.2V other inputs=0~3V Power down supply current Units 2.0 2.0 V 2.0 V V VI (S-CE2) Chip enable input S-CE2 Icc (PD) Max 0.2 V +70 ~ +85°C - - 24 mA +40 ~ +70°C - - 8 mA +25 ~ +40°C - 1 3 mA - 40 ~ +25 °C - 0.3 1 mA -I Typical value is for Ta=25°C (2) TIMING REQUIREMINTS Limits Symbol Parameter tsu (PD) trec (PD) Power down set up time Test conditions Min Typ Units ns 0 5 Power down recovery time Max ms (3) TIMING DIAGRAM S-LB#,S-UB# control mode S-Vcc tsu (PD) S-LB#, S-UB# 2.7V 2.7V trec (PD) 2.2V 2.2V S-LB#,S-UB# > = (S-Vcc) - 0.2V S-CE1# control mode S-Vcc tsu (PD) S-CE1# 2.7V 2.7V trec (PD) 2.2V 2.2V S-CE1# > = (S-Vcc) - 0.2V S-CE2 control mode S-Vcc 2.7V S-CE2 0.2V 0.2V tsu (PD) 30 2.7V S-CE2 < = 0.2V trec (PD) Nov 1999 , Rev.2.3