MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM Preliminary This document is a preliminary Target Spec. and some of the contents are subject to change without notice. PINCONFIGURATION (TOP VIEW) DESCRIPTION 1. 2. The M5M4V16169DTP/RT is a 16M-bit Cached DRAM which integrates input registers, a 1,048,576-word by 16-bit dynamic memory array and a 1024- word by 16-bit static RAM array as a Cache memory (block size 8x16) onto a single monolithic circuit. The block data transfer between the DRAM and the data transfer buffers (RB1/RB2/WB1/WB2) is performed in one instruction cycle, a fundamental advantage over a conventional DRAM/SRAM cache. The RAM is fabricated with a high performance CMOS process, and is ideal for large-capacity memory systems where high speed, low power dissipation, and low cost are essential. The use of quadruple-layer polysilicon process combined with silicide and double layer aluminum wiring technology, a single-transistor dynamic storage stacked capacitor cell, and a six-transistor static storage cache cell provide high circuit density at reduced costs. FEATURES Type name M5M4V16169TP/RT-7 M5M4V16169TP/RT-8 M5M4V16169TP/RT-10 M5M4V16169TP/RT-15 SRAM Access/cycle 5.6ns/7ns 6.4ns/8ns 8.0ns/10ns 8.0ns/15ns DRAM Access/cycle 49ns/70ns 56ns/80ns 60ns/90ns 75ns/120ns # 70-pin,400-mil TSOP (type II ) with 0.65mm lead pitch and 23.49mm package length. # Multiplexed DRAM address inputs for reduced pin count and higher system densities. # Selectable output operation (transparent / latched / registered) using set command register cycle. # Single 3.3V +/- 0.3V Power Supply. (3.3V +/- 0.15V for -7 part) # 2048 refresh cycles every 64ms (Ad0->Ad10). # Programmable burst length (1,2,4,8) and burst sequence (sequential,interleave) with no latency. # Synchronous design for precise control with an external clock (K). # Output retention by advanced mask clock (CMs#). # All inputs/outputs low capacitance and LVTTL compatible. # Separate DRAM and SRAM address inputs for fast SRAM access. # Page Mode capability. # Auto Refresh capability. # Self Refresh capability. Power Dissipation (Typ) DRAM: 530 SRAM: 860 DRAM: 500 SRAM: 800 DRAM: 430 SRAM: 660 DRAM: 330 SRAM: 420 Vcc DQCl DQCu CC1# CC0# WE# CS# CMd# CMs# K DQ0 Vss DQ1 DQ2 VddQ DQ3 Vss DQ4 VccQ DQ5 DQ6 Vss DQ7 MCL As0 As1 As2 RAS# CAS# DTD# Ad0 Ad1 Ad2 Vcc 1 70 2 69 3 68 4 67 5 66 6 65 7 64 8 63 9 62 10 11 61 60 12 59 13 14 15 16 17 58 400 mil 70Pin TSOP Type II 19 20 21 22 23 57 56 55 54 52 0.65mm Lead Pitch 51 50 49 48 24 47 25 46 26 45 27 28 44 43 29 42 30 41 31 40 32 39 33 38 34 37 36 35 Vss Ad9 Ad8 Ad7 Ad11 Ad10 As9 As8 As7 As6 DQ15 Vss DQ14 DQ13 VccQ DQ12 Vcc DQ11 VccQ DQ10 DQ9 Vss DQ8 MCH G# As5 As4 As3 Ad6 Ad5 Ad4 Ad3 ADF# Vss Package code:70P3S-L Vss Ad9 Ad8 Ad7 Ad11 Ad10 As9 As8 As7 As6 DQ15 Vss DQ14 DQ13 VccQ DQ12 Vcc : Master Clock K : Chip Select CS# : DRAM Clock Mask CMd# : Row Addr. Strobe RAS# : Column Addr. Strobe CAS# : Data Transfer Direction DTD# : DRAM Address Ad : SRAM Clock Mask CMs# CC0#,CC1# : Control Clocks : Write Enable WE# : I/O Byte Control DQC(u/l) : SRAM Address As DQ11 : Output Enable G# VccQ : Data I/O DQ DQ10 : Power Supply Vcc DQ9 : DQ Power Supply VccQ Vss : Ground Vss DQ8 :Address Fetch clock ADF# MCH This pin can be None-Connect. G# :Must Connect Low MCL As5 :Must Connect High MCH As4 As3 Ad6 Ad5 Ad4 Ad3 ADF# Vss 70 1 69 2 68 3 67 4 66 5 65 6 64 7 63 8 62 9 61 60 10 11 59 12 58 57 56 55 54 13 400 mil 70Pin TSOP Type II 52 51 50 49 48 14 15 16 17 19 0.65mm Lead Pitch 20 21 22 23 47 24 46 25 45 26 44 43 27 42 29 41 30 40 31 39 32 38 33 37 34 28 36 35 Vcc DQCl DQCu CC1# CC0# WE# CS# CMd# CMs# K DQ0 Vss DQ1 DQ2 VccQ DQ3 Vss DQ4 VccQ DQ5 DQ6 Vss DQ7 MCL As0 As1 As2 RAS# CAS# DTD# Ad0 Ad1 Ad2 Vcc Package code:70P3S-M MITSUBISHI ELECTRIC (REV 1.0) Jul. 1998 1 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM Vcc BLOCK DIAGRAM 1 VccQ Vss 1 54 35 12 23 48 59 70 17 36 15 20 51 56 29 RAS# Ad11 66 (Row Address strobe) Ad10 65 Col.3-7 DRAM Address Input Ad9 69 Ad8 68 Ad7 67 Ad6 41 Ad5 40 Ad4 39 30 CAS# Column Block Decoder (Column Address strobe) Row 0-11 31 DTD# (Data Transfer Direction) 1M bit DRAM Array Mask 0 1 (Clock Mask for DRAM) 1M x 16= 16M DRAM 7 KBuffer Ad3 38 Ad2 34 Ad1 33 Ad0 32 Timing control Sense Amplifier and I/O control Mask Command (0-6) 0 RB1 1 2 WB1 Mask WB2M WB1M WB1 (Control Clock 0) (Control Clock 1) 37 ADF# (Address Fetch) As3-9 7 S/A and I/O 16 Din Buffer Col.Decoder As5 44 As4 43 As3 42 As1 27 As0 26 (Clock Mask for SRAM) 4 CC1# Write Buffer 1 01 2 As6 61 As2 28 9 CMs# 3 DQCu(Enable upper) 2 DQCl(Enable lower) As8 63 SRAM Address input (Master ClocK) 5 CC0# Read Buffer1 As9 64 As7 62 (Chip Select) 10 K (Write Enable) Read Buffer2 Write Buffer 2 WB2 7 CS# 6 WE# 7 RB2 WB2 Mask 8 CMd# As0-2 1KBit SRAM Array MITSUBISHI ELECTRIC 1Kx16=16K SRAM Main Amp. 11 13 14 16 19 21 22 24 47 49 50 52 55 57 58 60 45 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 G# (Output Enable) (REV 1.0) Jul. 1998 2 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM BLOCK DIAGRAM 2 DRAM 1MX16 8X16 Block Ad3-7 1 of 32 Decode DRAM Row Decoder 8X16 Ad0-11 1 of 4096 Decode 8X16 RB1 Lower Byte WB2 Lower Byte Upper Byte Upper Byte DQ0-7 As0-2 1of8Decode DQ8-15 8X16 As0-2 1of8 Decode RB2 Lower Byte Upper Byte 16 bits DQs WB1 Lower Byte Upper Byte 16 bits 8X16 8X16 Block 16 bits 8X16 16 bits SRAM 1KX16 As0-2 1of8Decode SRAM Row Decoder As3 - 9 1 of 128 Decode MITSUBISHI ELECTRIC (REV 1.0) Jul. 1998 3 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM FUNCTION TRUTH TABLE SRAM Mnemonic CODE CS# As DQC CMs# CC0# CC1# (u/l) WE# (SRAM address) DRAM Ad As0-9 CMd# RAS# CAS# DTD# Ad0-11 NOP H H X X X X X H X X X X SPD X L X X X X X X X X X X LBM L H H H H L X X X X X X DES L H H H X X X X X X X X SR L H H L H H As0-9 X X X X X SW L H H L H L As0-9 X X X X X X X X X X X X X X X (2) BRT L H L H L H As3-9 BWT L H L H L L As3-9 BRTR L H L H H H As0-9 X X X X X BWTW L H L H H L As0-9 X X X X X X X X X X X X X X X X (1) X (1) X H X BR L H L L H H (DRAM address) Previous Previous (2) As0-2 (2) (2) BW L H L L H L As0-2 DPD X X X X X X X L X DNOP L X X X X X X H H (1) Ad2 Ad1 Ad0 X DRT L X X X X X X H H L H Ad3-7 (2) (Col.Block) DWT1 L X X X X X X H H L L Ad3-7 (2) (Col.Block) 0 0 0 L Ad3-7 (2) (Col.Block) 0 0 1 L Ad3-7 (2) (Col.Block) 0 1 0 L Ad3-7 (2) (Col.Block) 0 1 1 L Ad3-7 (2) (Col.Block) 1 0 0 L Ad3-7 (2) (Col.Block) 1 0 1 L Ad3-7 (2) (Col.Block) 1 1 0 1 1 1 DWT1R DWT2 DWT2R DWT3 DWT3R DWT4 L L L L L L X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X H H H H H H H H H H H H L L L L L L DWT4R L X X X X X X H H L L Ad3-7 (2) (Col.Block) ACT L X X X X X X H L H H Ad0-11 (Row Add.) PCG L X X X X X X H L H L X ARF L X X X X X X H (7) L L H X (8) L L H X L L L SRF L X X X X X X H SCR L X X X X X X H NOTES 1) For the DPD function, the RAS#, CAS# and DTD# inputs are DON'T CARE except for the L,L,H combination. (Respectively). 2) The unused addresses must be set to Low. 3) Use New: If BW or BWT or BWTW is initiated the same cycle as DWT1 or DWT1R, new data is loaded into the buffer and transferred to DRAM. 4) Clear 1 or 2 Transfer Mask Bits (as addressed by As0-2 and DQCU/L). MITSUBISHI ELECTRIC 0 0 0 Command 5) Actual number of bits transfer depends on the state of the DTBW Mask and the DQCU/DQCL inputs. Note: If DQC(U/L) is Low, the corresponding DQ(s) is(are) disabled (Input and Output Buffer). SR,SW,BR and BW cycles with DQCU and DQCL Low result in a Deselect SRAM operation. 6) Following a DWT1 or DWT1R cycle, the entire WB1 Transfer Mask is Set . (i.e. , data can no longer be transferred from WB1 to DRAM.) Succeeding Buffer-Writes or Buffer Write Transfers will Clear Mask bits. 7) CMd# during current cycle must be High (see timing diagram for Auto-Refresh). 8) CMd# during current cycle must be Low (see timing diagram for Self-Refresh). (REV 1.0) Jul. 1998 4 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM FUNCTION TRUTH TABLE Data Transfer Buffers Write Buffers Xfer Masks WB1 WB2 Mask Mask DQ pin Read Buffer RB1,2 Din Dout - Hi-Z WB1 WB2 - - - - - - - - - - Function No Operation Hi-Z SRAM Power Down& Data retention DRAM Power Down Suspend No operation - - - - - Byte mask - - - - - - Hi-Z Deselect SRAM No operation - - - - - - Valid SRAM Read SRAM->DO - - - - - Valid Hi-Z SRAM Write DIN->SRAM - - - - Use - Hi-Z Buffer Read Xfer RB2->SRAM Load - Clear Mask - - - Hi-Z Buffer Write Xfer SRAM->WB1 - - - - Use - Valid Buffer Read Xfer & Read RB2->SRAM->DO Load - Clear Mask - - Valid Hi-Z Buffer Read Xfer & Read DIN->SRAM->WB1 - - - - Use - Valid Buffer Read RB2->DO Load - Clear 1 (4) or 2 bits - - Valid Hi-Z - - - - - - - DRAM Power Down No operation - - - - - - - DRAM No OPeration No operation - - - - Load - - DRAM Read Xfer DRAM->RB1->RB2 Load/ Use - - - DRAM Write Xfer1 WB1->WB2->DRAM (6) Buffer Write No operation DIN->WB1 (3) Use Load/ Use Use Use Load/ Use Use Load/ Use Load - - DRAM Write Xfer1& Read WB1->WB2 (3) ->DRAM->RB1->RB2 - Use - Use - - - DRAM Write Xfer2 WB2->DRAM - Use - Use Load - - DRAM Write Xfer2& Read WB2->DRAM ->RB1->RB2 Use Load/ Use - Load - - - Use Load/ Use - - Use - - - Use - - - - (6) DRAM Write Xfer3 WB1->WB2->DRAM - - DRAM Write Xfer3& Read WB1->WB2 (3) ->DRAM->RB1->RB2 - - - DRAM Write Xfer4 WB2->DRAM - Load - - DRAM Write Xfer4& Read WB2->DRAM->RB - - - - - DRAM Activate Page Call - - - - - - DRAM Precharge - - - - - - - Auto Refresh - - - - - - - Self Refresh Entry - - - - - - - Set Command Register Function Din --> SRAM Din --> WB1 SRAM --> WB1 WB1 --> WB2 WB2 --> DRAM Load Load Data Transferred (max) (5) 8/16 bits (5) 8/16bits 128 bits (8X16bit-block) 128 bits (8X16bit-block) 128 bits (8X16bit-block) MITSUBISHI ELECTRIC Function WB2 --> RB DRAM --> RB RB --> Dout RB --> SRAM Data Transferred (max) 128 bits (8X16bit-block) 128 bits (8X16bit-block) (5) 8/16 bits 128 bits (8X16bit-block) DO: Data Out DIN: Data In WB1: Write Buffer 1 WB2: Write Buffer 2 RB: Read Buffer (REV 1.0) Jul. 1998 5 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM PIN DESCRIPTIONS(1) K CMd# RAS# CAS# DTD# Ad0-Ad11 CS# CMs# Input Master Clock Provides the fundamental timing and the internal clock frequency for the CDRAM. All external timing parameters (with the exception of G# in read cycle and CMd# in Self refresh cycle) are specified with respect to the rising edge of K. Input DRAM Clock Mask controls the operation of the internal DRAM master clock (K). When CMd# is Low at the rising edge of K, the internal DRAM master clock (K) for the following cycle is ceased and input stages are powered-off, resulting in a DRAM Power Down. Input Row Address Strobe is used in conjunction with Master clock K (depending on the states of CMd#, CAS#, and DTD#) to activate the DRAM (latching the Row Address lines and accessing 1 of 4096 rows), initiate a DRAM precharge cycle, perform a DRAM Read or Write Transfer, DRAM Write Transfer & Read, set the command registers, start an Auto-Refresh cycle, enter a Self-Refresh cycle,create a DRAM NOP cycle, or power down the DRAM. Input Column Address Strobe is used in conjunction with the Master Clock K to latch the Column addresses. When preceded by RAS# in a DRAM access cycle, CAS# initiates a DRAM Write Transfer (WB1/2 -> DRAM, if DTD#=L), DRAM Write Transfer & Read (WB1/2 -> DRAM -> RB, if DTD#=L) or DRAM Read Transfer (DRAM -> RB, if DTD#=H), depending on the state of DTD# (see DTD# pin description). Input Data Transfer Direction controls DRAM-to-RB(read) / WB-to-DRAM (write) direction. If preceded by a RAS# low cycle, both CAS# and DTD# low (on the rising edge of K) initiate a DRAM Write Transfer cycle. If DTD# stays High with the above conditions, a DRAM Read Transfer cycle results. DTD# can also initiate DRAM Activate, DRAM Precharge, Auto-Refresh, Set-Command Register, and Self Refresh cycles. Input DRAM Address Lines are Multiplexed to reduce pin count. Ad0-Ad11 (@ RAS=low,CAS=high,DTD=high, K=Rising edge) specify the Row Address of the DRAM to activate and refresh the selected page and Ad3-Ad7 (@ RAS=high,CAS=low,K=Rising edge) specify the Block Address of the DRAM. In addition, Ad0-Ad2 (@ RAS=high,CAS=low, K=Rising edge) specify the transfer operation of the DRAM . Also Ad0-Ad9 (@RAS=low,CAS=low, DTD=low, K=Rising Edge) are used as the command in set command register cycle. Input The Chip Select controls the operation of the CDRAM. When CS#=H at the rising edge of K and the previous CMd# or CMs# is high, the chip is in No Operation mode. Input SRAM Clock Mask controls the operation of the internal SRAM master clock (Ks). When CMs# is asserted at a rising edge of K, the internal SRAM master clock for the following cycle is suspended, resulting in the power down of the SRAM portion of the circuit, including the Sense Amps. CMs# can also be used to retain output data during SRAM power-down. MITSUBISHI ELECTRIC (REV 1.0) Jul. 1998 6 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM PIN DESCRIPTIONS(2) Input DQCu/l are I/OByte control signals. If G#=Low, DQCu/l have a control of output impedence: DQCu controls upper DQs (DQ8-15) & DQCl controls lower DQs (DQ0-7). DQCu/l also control both input data during SRAM Writes or Buffer Writes and transfer mask during Buffer Writes. (WB1 transfer Masks for each byte are written (bits are cleared) during Buffer Writes depending on DQCu/l inputs.) WE# Input Write Enable controls SRAM and Buffer read and write operations. A high on the WE# pin causes either a Buffer Read, SRAM Read, Buffer Read Transfer and/or a Buffer Read Transfer & Read to occur (depending on the state of the CC0# and CC1# bits). A low on the WE# pin causes either a Buffer Write, SRAM Write, Buffer Write Transfer and/or a Buffer Write Transfer & Write to occur (depending on the state of the CC0# and CC1# inputs) CC0#,CC1# Inputs The Control Clock Inputs control SRAM and Buffer operations. CC0# is Low for all Buffer Writes, Reads, and Transfers, and High for all other SRAM operations. CC1# is high for all Buffer Read Transfers and Buffer Write Transfers , and Deselect SRAM. As0-As9 Inputs SRAM Addresses are non-multiplexed, and access 1024 - 16-bit words ( configured as 128 Rows X 8 Columns X 16 Bits, where the Block Size is 8 X 16) in the SRAM array. As0-As3 select word address within a block, and As3-As9 select the SRAM row(block). G# Input The Output Enable is an asynchronous input. G#=high forces the outputs to high impedence. DQ0-DQ15 Inputs / Outputs DQCl,DQCu VccQ Supply Output operation is either transparent, latched, or registered depending on the state of the command register. The Data Lines for the CDRAM are asynchronously controlled by G#. VccQ is the DQ power supply and allows the device to operate in a mixed voltage system (e.g., 5V data bus). As specified in the Table: Recommended Operating Conditions, VccQ must be greater-than or equal-to the highest voltage experienced by the data bus. For 3.3V system operation, VccQ may be tied to Vcc. MITSUBISHI ELECTRIC (REV 1.0) Jul. 1998 7 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM MODE DESCRIPTIONS (1) No Operation. Outputs are high-impedance. All input buffers remain active. NOP SRAM Power-Down If CMs#=Low at the rising edge of K, the SRAM enters SRAM Power Down at the next rising edge of K. During this mode, the internal SRAM K clock becomes inactive. The Output Buffers remain enabled and are controlled by G#. All input buffers of SRAM clocks and SRAM addresses are inactive. Deselect SRAM All transfer functions and input/output operations to and from the SRAM and Buffer are disabled. This cycle is useful for output impedance control (Hi-Z,Low-Z) without G#. Output buffers are active during this cycle for registered output mode control. SRAM Read Data is read from the SRAM to the I/O pins. Addresses As0-As9 are used to select the data to be read. As3-As9 decode the SRAM Row (=Block), and As0-As2 decode (1 of 8) the 16bit word. DQCu and DQCl control the impedence (High-Z/Low-Z) of the upper and lower bytes, respectively. Data is written from the I/O pins to the SRAM. Addresses As0-As9 are used to select the location to be written. As3-As9 decode the SRAM Row (=Block), and As0-As2 decode (1of8) the 16-bit word to be written. DQCUu and DQCl control Upper and Lower byte writes, respectively. 8X16Block DRAM 1MX16 Ad3-7 1of32 Decode DRAM RowDecoder 8X16 Ad0-9 1of4096Decode 8X16 SRAM Write DQ0-7 WB2 Lower Byte Upper Byte RB1 DQ8-15 Lower Byte Upper Byte 8X16 As0-2 1of8Decode RB2 Lower Byte As0-2 1of8 Decode WB1 Lower Byte 16bits Upper Byte DQs 16bits Upper Byte X 16bits 8X16 8X16 8X16Block 16bits SRAM 1KX16 SRAM RowDecoder As0-2 1of8Decode As3-9 1of128Decode MITSUBISHI ELECTRIC (REV 1.0) Jul. 1998 8 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM MODE DESCRIPTIONS (2) Data is transferred from the Read Buffer (RB2) to the SRAM. Addresses As3-9 select the SRAM row to which the 8X16 bit block is to be written. Addresses As0-As2 must be set low. 8X16Block DRAM 1M X 16 Ad3-7 1of32 Decode DRAM RowDecoder 8X16 Ad0-11 1of4096Decode 8X16 Buffer Read Transfer DQ0-7 RB1 WB2 Lower Byte Upper Byte Lower Byte DQ8-15 8X16 As0-2 1of8Decode RB2 Lower Byte Upper Byte As0-2 1of8 Decode WB1 Lower Byte Upper Byte 16bits DQs 16bits Upper Byte X 16bits 8X16 8X16 8X16Block 16bits SRAM 1KX16 As0-2 1of8Decode SRAM RowDecoder As3-9 1of128Decode Data is transferred from the SRAM to the Write-Buffer1 (WB1). Addresses As3-As9 decode the SRAM Row (=8X16 bit block) to be transferred. Addresses As0-As2 must be set low. The Buffer Write Transfer cycle "clears" all transfer mask bits in the WB1 Mask (allowing all data to be transferred in a successive DRAM Write Transfer cycle). 8X16Block DRAM 1M X 16 Ad3-7 1of32 Decode DRAM RowDecoder 8X16 Ad0-11 1of4096Decode 8X16 Buffer Write Transfer DQ0-7 RB1 WB2 Lower Byte Upper Byte DQ8-15 Lower Byte 8X16 Lower Byte As0-2 1of8Decode RB2 Lower Byte As0-2 1of8 Decode WB1 Upper Byte 16bits Upper Byte DQs 16bits Upper Byte 8X16 X 16bits 8X16 8X16Block 16bits SRAM 1KX16 As0-2 1of8Decode SRAM RowDecoder As3-9 1of128Decode MITSUBISHI ELECTRIC (REV 1.0) Jul. 1998 9 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM MODE DESCRIPTIONS (3) Data is transferred from the Read Buffer (RB2) to the SRAM, and simultaneously, data (16 bit word) is read from the RB2 to the I/O pins. Addresses As3-9 select the SRAM Row to which the 8X16 bit block is to be written. Addresses As0-As2 decode the 16-bit word to be read. 8X16Block DRAM 1M X 16 Ad3-7 1of32 Decode DRAM RowDecoder Ad0-11 1of4096Decode 8X16 8X16 Buffer Read Transfer & SRAM Read DQ0-7 WB2 Lower Byte Upper Byte RB1 Upper Byte As0-2 1of8Decode Lower Byte DQ8-15 RB2 8X16 Lower Byte 16bits Upper Byte DQs As0-2 1of8Decode 16bits WB1 Lower Byte X Upper Byte 16bits 8X16 8X16 8X16Block 16bits SRAM 1KX16 As0-2 1of8Decode SRAM RowDecoder As3-9 1of128Decode Data is first written from the I/O pins to SRAM as decoded by As0-As9. Then, the SRAM Row (=Block) decoded by As3-As9 is transferred to the Write-Buffer1 (WB1). The Buffer Write Transfer cycle "clears" all transfer mask bits in the WB1 Mask (allowing all data to be transferred in a successive DRAM Write Transfer cycle). DQCu and DQCl control Upper and Lower byte writes respectively, however all transfer mask bits in the WB1 are cleared. Buffer Write Transfer & SRAM Write 8X16Block DRAM 1M X 16 Ad3-7 1of32 Decode DRAM RowDecoder 8X16 Ad0-11 1of4096Decode 8X16 DQ0-7 RB1 WB2 Lower Byte Upper Byte Lower Byte DQ8-15 Upper Byte As0-2 1of8Decode RB2 Lower Byte As0-2 1of8 Decode 8X16 WB1 Lower Byte 16bits Upper Byte DQs 16bits Upper Byte 8X16 X 16bits 8X16 8X16Block 16bits SRAM 1KX16 As0-2 1of8Decode SRAM RowDecoder As3-9 1of128Decode MITSUBISHI ELECTRIC (REV 1.0) Jul. 1998 10 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM MODE DESCRIPTIONS (4) Data is read from the Read Buffer (RB2) to the I/O pins. Addresses As0-As2 are used to select (1 of 8) the 16-bit word to be read. Addresses As3-As9 must be set low for this operation. 8X16Block DRAM 1M X 16 Ad3-7 1of32 Decode DRAM RowDecoder Ad0-11 1of4096Decode 8X16 8X16 Buffer Read DQ0-7 RB1 WB2 Lower Byte DQ8-15 Lower Byte Upper Byte As0-2 1of8Decode RB2 8X16 Lower Byte 16bits Upper Byte As0-2 1of8 Decode WB1 Lower Byte Upper Byte DQs 16bits X Upper Byte 16bits 8X16 8X16 8X16Block 16bits SRAM 1KX16 As0-2 1of8Decode SRAM RowDecoder As3-9 1of128Decode Data is written from the I/O pins to the Write-Buffer1. Addresses As0-A2 are used to select (1of8) the 16-bit word to be written. Addresses As3-As9 must be set low for this operation. The transfer mask bits associated with the Upper and Lower bytes are cleared in the WB1 Mask. DQCu and DQCl control Upper and Lower byte writes (and associated tranfer mask bits), respectively. 8X16Block DRAM 1M X 16 Ad3-7 1of32 Decode DRAM RowDecoder Ad0-11 1of4096Decode 8X16 8X16 Buffer Write DQ0-7 RB1 WB2 Lower Byte Upper Byte Lower Byte DQ8-15 Lower Byte Lower Byte As0-2 1of8Decode RB2 8X16 As0-2 1of8 Decode WB1 Upper Byte 16bits Upper Byte DQs 16bits Upper Byte 8X16 X 16bits 8X16 8X16Block 16bits SRAM 1KX16 As0-2 1of8Decode SRAM RowDecoder As3-9 1of128Decode MITSUBISHI ELECTRIC (REV 1.0) Jul. 1998 11 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM MODE DESCRIPTIONS (5) DRAM Power-Down If CMd#=Low at the rising edge of K, the DRAM enters DRAM Power Down at the next rising edge of K. During this mode, the internal DRAM K clock becomes inactive. Also all input buffers of DRAM clocks and DRAM addresses are inactive. Note that the latency of DRAM Read Transfer cycle is not counted up in this cycle. DRAM NOP The DNOP cycle is used when no other DRAM operations are desired, holding the DRAM in its present (precharge/activate) state. A Block (8x16) is transferred from the DRAM to the Read Buffer1 and 2 (RB1,RB2) as specified by Addresses Ad3-Ad7. Addresses Ad8-Ad11 and Ad0-Ad2 must be set to Low. After the Latency Period (specified in the Access Latency Table) new data will be present in the Read Buffer2. Prior to the Latency timeout, old data will be present in the RB2. (Notes 1,2,4) 8X16Block DRAM 1M X 16 Ad3-7 1of32 Decode DRAM RowDecoder Ad0-11 1of4096Decode 8X16 DRAM Read Transfer 8X16 DQ0-7 RB1 WB2 Lower Byte Upper Byte Lower Byte DQ8-15 Lower Byte Lower Byte As0-2 1of8Decode RB2 8X16 As0-2 1of8 Decode WB1 Upper Byte 16bits Upper Byte DQs 16bits Upper Byte 8X16 X 16bits 8X16 8X16Block 16bits SRAM 1KX16 As0-2 1of8Decode SRAM RowDecoder As3-9 1of128Decode MITSUBISHI ELECTRIC (REV 1.0) Jul. 1998 12 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM MODE DESCRIPTIONS (6) Data (8X16 Block) is transferred from WB1 through WB2 to the DRAM block specified by Addresses Ad3-Ad7. Addresses Ad8-Ad11 must be set to Low. The Mask present in WB1 is also transferred to WB2 and controls the data written to the DRAM. After data has been transferred from WB1 to WB2 in the present cycle, the entire WB1 Mask is Set. (Notes 3,4) 8X16Block DRAM 1M X 16 Ad3-7 1of32 Decode DRAM RowDecoder 8X16 DRAM Write Transfer1 Ad0-11 1of4096Decode 8X16 DQ0-7 RB1 WB2 Lower Byte Upper Byte Lower Byte DQ8-15 8X16 As0-2 1of8Decode RB2 Lower Byte 16bits Upper Byte As0-2 1of8 Decode WB1 Lower Byte Upper Byte DQs 16bits X Upper Byte 16bits 8X16 8X16 8X16Block 16bits SRAM 1KX16 As0-2 1of8Decode SRAM RowDecoder As3-9 1of128Decode Data (8X16 Block) is transferred from WB1 through WB2 to the DRAM block specified by Addresses Ad3-Ad7. Addresses Ad8-A11 must be set to Low. The transfer mask present in WB1 is also transferred to WB2 and controls the data written to the DRAM. The block to which the data is written in DRAM is simultaneously transferred to the Read Buffer.(Notes 2,3,4) 8X16Block DRAM 1M X 16 Ad3-7 1of32 Decode DRAM RowDecoder Ad0-11 1of4096Decode 8X16 DRAM Write Transfer1 & Read 8X16 DQ0-7 RB1 WB2 Lower Byte Upper Byte Lower Byte DQ8-15 Lower Byte Lower Byte As0-2 1of8Decode RB2 8X16 As0-2 1of8 Decode WB1 Upper Byte 16bits Upper Byte DQs 16bits Upper Byte 8X16 X 16bits 8X16 8X16Block 16bits SRAM 1KX16 As0-2 1of8Decode SRAM RowDecoder As3-9 1of128Decode MITSUBISHI ELECTRIC (REV 1.0) Jul. 1998 13 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM MODE DESCRIPTIONS (7) Data (8X16 Block) is transferred from WB2 to the DRAM block specified by Addresses Ad3Ad7. Addresses Ad8-Ad11 must be set to Low. The WB2 Mask controls the data written to the DRAM. With the DWT2 function, the WB2 data and WB2 transfer mask remain unchanged. (Note 4) 8X16Block DRAM 1M X 16 Ad3-7 1of32 Decode DRAM RowDecoder 8X16 Ad0-11 1of4096Decode 8X16 DRAM Write Transfer2 DQ0-7 RB1 WB2 Lower Byte Lower Byte DQ8-15 Upper Byte 8X16 Upper Byte As0-2 1of8Decode RB2 Lower Byte WB1 16bits Upper Byte As0-2 1of8 Decode DQs 16bits X Upper Byte Lower Byte 16bits 8X16 8X16 8X16Block 16bits SRAM 1KX16 As0-2 1of8Decode SRAM RowDecoder As3-9 1of128Decode Data (8X16 Block) is transferred from WB2 to the DRAM block specified by Addresses Ad3Ad7. Addresses Ad8-Ad11 must be set to Low. The WB2 transfer mask controls the data written to the DRAM. With the DWT2 function, the WB2 data and WB2 transfer mask remain unchanged. The block to which the data is written in DRAM is simultaneously transferred to the Read Buffer1 and 2. (Notes 1,2,4) 8X16Block DRAM 1MX16 Ad3-7 1of32 Decode DRAM RowDecoder 8X16 DRAM Write Transfer2 & Read Ad0-11 1of4096Decode 8X16 DQ0-7 RB1 WB2 Lower Byte Upper Byte Lower Byte DQ8-15 8X16 As0-2 1of8 Decode WB1 As0-2 1of8Decode RB2 Lower Byte Lower Byte Upper Byte 16bits Upper Byte DQs 16bits Upper Byte 8X16 X 16bits 8X16 8X16Block 16bits SRAM 1KX16 As0-2 1of8Decode SRAM RowDecoder As3-9 1of128Decode MITSUBISHI ELECTRIC (REV 1.0) Jul. 1998 14 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM MODE DESCRIPTIONS (8) Data (8X16 Block) is transferred from WB1 through WB2 to the DRAM block specified by Addresses Ad3-Ad7. Addresses Ad8-Ad9 must be set to Low. The Mask present in Byte MaskRegister controls the data written to the DRAM. The Byte Mask Register is set at Load Byte Mask cycle,where corresponding byte masks are set depending on DQ data in the cycle. (Note 4,5) The data of WB1 and the mask data of WBM1 are tranferred to WB2 and WBM2, however WBM1/2 is not used in this cycle. 8X16Block DRAM 256KX16 Ad3-7 1of32 Decode DRAM RowDecoder 8X16 Ad0-11 1of4096Decode DRAM Write Transfer3 8X16 DQ0-7 RB1 WB2 Lower Byte DQ8-15 Lower Byte Upper Byte As0-2 1of8Decode RB2 8X16 Lower Byte 16bits Upper Byte As0-2 1of8 Decode WB1 Lower Byte Upper Byte DQs 16bits X Upper Byte 16bits 8X16 8X16 8X16Block 16bits SRAM 1KX16 As0-2 1of8Decode SRAM RowDecoder As3-9 1of128Decode Data (8X16 Block) is transferred from WB1 through WB2 to the DRAM block specified by Addresses Ad3-Ad7. Addresses Ad8-Ad9 must be set to Low. The Mask present in Byte MaskRegister controls the data written to the DRAM. The block to which the data is written in DRAM is simultaneously transferred to the Read Buffer.(Notes 1,2,4,5) 8X16Block DRAM 256KX16 Ad3-7 1of32 Decode DRAM RowDecoder 8X16 DRAM Write Transfer3 & Read Ad0-11 1of4096Decode 8X16 DQ0-7 RB1 WB2 Lower Byte Upper Byte Lower Byte DQ8-15 Lower Byte Lower Byte As0-2 1of8Decode RB2 8X16 As0-2 1of8 Decode WB1 Upper Byte 16bits Upper Byte DQs 16bits Upper Byte 8X16 X 16bits 8X16 8X16Block 16bits SRAM 1KX16 As0-2 1of8Decode SRAM RowDecoder As3-9 1of128Decode MITSUBISHI ELECTRIC (REV 1.0) Jul. 1998 15 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM MODE DESCRIPTIONS (9) Data (8X16 Block) is transferred from WB2 to the DRAM block specified by Addresses Ad3Ad7. Addresses Ad8-Ad9 must be set to Low. The Mask present in Byte MaskRegister controls the data written to the DRAM. With the DWT4 function, the WB2 data and WB2 Mask remain unchanged. (Note 4,5) 8X16Block DRAM 256KX16 Ad3-7 1of32 Decode DRAM RowDecoder Ad0-11 1of4096Decode 8X16 DRAM Write Transfer4 8X16 RB1 WB2 DQ0-7 Lower Byte DQ8-15 Upper Byte As0-2 1of8Decode Lower Byte Upper Byte RB2 8X16 Lower Byte WB1 Lower Byte 16bits Upper Byte As0-2 1of8 Decode DQs 16bits X Upper Byte 16bits 8X16 8X16 8X16Block 16bits SRAM 1KX16 As0-2 1of8Decode SRAM RowDecoder As3-9 1of128Decode Data (8X16 Block) is transferred from WB2 to the DRAM block specified by Addresses Ad3Ad7. Addresses Ad8-Ad9 must be set to Low. The Mask present in Byte MaskRegister controls the data written to the DRAM. With the DWT4R function, the WB2 data and WB2 transfer mask remain unchanged. The block to which the data is written in DRAM is simultaneously transferred to the Read Buffer. (Notes 1,2,4,5) 8X16Block DRAM 256KX16 Ad3-7 1of32 Decode DRAM RowDecoder DRAM Write Transfer4 & Read Ad0-11 1of4096Decode 8X16 8X16 DQ0-7 RB1 WB2 Lower Byte Upper Byte Lower Byte DQ8-15 Lower Byte Lower Byte As0-2 1of8Decode RB2 8X16 As0-2 1of8 Decode WB1 Upper Byte 16bits Upper Byte DQs 16bits Upper Byte 8X16 X 16bits 8X16 8X16Block 16bits SRAM 1KX16 As0-2 1of8Decode SRAM RowDecoder As3-9 1of128Decode MITSUBISHI ELECTRIC (REV 1.0) Jul. 1998 16 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM MODE DESCRIPTIONS (10) DRAM Activate Addresses are latched from the Ad0-Ad11 inputs by the rising edge of K. Internally, a DRAM row is selected (Page Call) in preparation for a DRAM Read or Write Transfer cycle. A DRAM Precharge cycle must separate all DRAM Activate cycles. DRAM Precharge Internally, the active DRAM Row is deselected (completing the refresh process) and page-mode is disabled. The DRAM is precharged prior to another DRAM Activate cycle. DRAM Auto-Refresh Internally, a DRAM row is selected and refreshed (as addressed by an internal, self-incrementing counter), followed by an internally generated Precharge cycle. The Auto refresh cycle can be implemented only if the DRAM is in Precharge state (i.e., a Precharge or Auto-Refresh cycle occurred more recently than an Acitvate cycle). DRAM Auto-Refresh is similar to a CAS-BeforeRAS (CBR) mode in standard DRAMs. DRAM Self Refresh All clock buffers are suspended, and CMd# asynchronously controls Self Refresh (CMd# rising edge initiates exit from Self Refresh). During Self Refresh, device enters a low power mode, with 2048 automatic refresh cycles. Set Command Register When SCR is initiated,the addresses present on the Ad0-Ad11 DRAM Address pins determine the DRAM Read Transfer Latency, the Output Mode (transparent / latched / registered), and WB1 transfer mask mode (set-all/ no change). No DRAM operation is executed in this cycle. Refer to the SCR Truth Table for legal Address values. During SCR cycle and the following 3 clock cycles(totally 4 clock cycles), only NOP,DNOP orDPD are allowed in DRAM portion and only NOP,DES or SPD are done in SRAM portion. The set commands are valid at least after the above 4 clocks later and the previous function is not guaranteed to work if it has not been completed.(i.e. DRT ,DWT1&R,DWT2&R and SR,BR and BRTR with registered output mode.) Notes: 1) This function is performed in a Latency period specified in the Access Latency Table. 2) After the Latency Period (specified in the Access Latency Table) new data will be present in the Read Buffer2. Prior to the Latency timeout, old data will be present in the RB2. 3) After data has been transferred from WB1, the entire WB1 Mask is Set. 4) Valid Ad0-Ad2 addresses are shown in the FUNCTION TRUTH TABLE. Power-On sequence Before starting normal operation, the following power on sequence is necessary. 1) Apply power and maintain stable power (pause) for 500us. 2) Perform a precharge (PCG) operation. 3) After tRP, perform 8 auto refresh commands (ARF) with adequate interval (tRC). 4) Issue set command register (SCR) to initilize the mode register. After this sequence, the RAM is in idle state and ready for normal operation. Note that DNOP / DPD and DES / SPD or NOP command will be the stand-by command for the above power sequence. Vcc must be powered-on at the same time or before VccQ is on. And Vcc must be powered-off at the same time or after VccQ is off. MITSUBISHI ELECTRIC (REV 1.0) Jul. 1998 17 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM Output Operations Output appears from the rising edge of K clock. Transparent SR DES SR DES SR K K DQC DQC SR tKHA tKHA G# G# tGLA tKHQZ tKHQX Q DQ0-15 Q DQ0-15 tGLQ Latched DES tGHQ Output appears from the falling edge of K clock. SR SR DES K SR SR K DQC This outputmode was deleted. DQC tKHA tKHA G# tKLA G# tKLA tKLQZ tKLQX Q DQ0-15 tGLA DQ0-15 tGLQ Registered Output appears from the rising edge of K clock. DES SR SR DES SR K K DQC DQC tK Q SR SR tK tKHAR tKHAR G# G# tKHQZ tKHQX DQ0-15 SR tGHQ Q tKHQZ tGLA tGHQ Q DQ0-15 tGLQ MITSUBISHI ELECTRIC (REV 1.0) Jul. 1998 18 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM tK tKH tKL K,K# tS tH CMd# tCMDS tCMDH CS# tCSS tCSH RAS# tRS tRH CAS# tCS tCH DTD# tDTS tDTH CMs# tCMSS CC0# tC0S tC0H CC1# tC1S tC1H WE# tWS tWH tCMSH DQC(u / l) tDQCS tDQCH ADF# tSADF tHADF Ad0-11 As0-9 DQ0-15 (Input) MITSUBISHI ELECTRIC tAS tDS tAH tDH (REV 1.0) Jul. 1998 19 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM Load Byte Mask Byte mask allocation during DWT3 and DWT4 Byte Mask Register Lower DQs DQ0 DQ1 Upper DQs DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 Lower Upper Block address 0 1 2 3 4 5 6 7 Column Block (16 byte) 0 : mask, no write 1 : unmask, write enable MITSUBISHI ELECTRIC (REV 1.0) Jul. 1998 20 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM DWT3 / DWT4 0 --- Write data / Mask data DRAM row 1023 0 DRAM column 128 set 0 1 2 3 4 5 6 7 0 1 0 1 1 1 0 0 Lower 8bit Upper8 bit SRAM byte mask written Byte mask WB1/WB2 255 lower byte Byte mask bit upper byte 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 DQ0-> ->DQ15 Write / Mask logic DWT2 DWT1 addition As0-2 DQCl DQCu SRAM DWT3/DWT4 WM1 WB1 DQ0-15 Load Byte Mask (LBM) WM2 WB2 DRAM DWT1/DWT3 DWT2/DWT4 MITSUBISHI ELECTRIC (REV 1.0) Jul. 1998 21 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM DWT3-DWT4 for Window clear(Block Write) shadow clear / window clear Window Boundary Page boundary ACT DNOP DWT3 DNOP DWT4 DNOP DWT4 DNOP DWT4 DNOP DWT4 PCG BWT DES LBM DES LBM DES DES DES DES DES LBM DES Color data is transferred from WB2 to DRAM column block with new byte mask. Color data is transferred from WB2 to DRAM column block with byte mask. Color data is transferred from WB1 through WB2 to DRAM column block with byte mask, which is loaded by Load Byte Mask cycle(LBM). The byte mask data is valid from the LBM cycle immediately and lasts until the next LBM cycle is initiated. Color data is loaded from SRAM cache to WB1.(BWT) MITSUBISHI ELECTRIC Page call.(ACT) (REV 1.0) Jul. 1998 22 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM Burst Mode (1) 1 2 4 3 6 5 7 8 10 9 12 11 14 13 K CMs# ADF# CC0# CC1# Accept interrupt for inputting new address w/o gap. WE# DQC(u / l) As0-2 C1 C2 C3 As3-11 C1 C2 C3 G# L DQ0-15 Q1 Q2 Q1+1 Q1+2 Q1+3 DES SR SR SR SR DES SR Q3 Q3 Q3+1 Q3+2 Q3+3 Q2+1 SR SR SR SR SR SR SRAM address and DRAM address can be multiplexed using this duration for DRAM control MITSUBISHI ELECTRIC (REV 1.0) Jul. 1998 23 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM Burst Mode (2) 1 2 3 4 6 5 7 8 9 10 12 11 14 13 K CMs# ADF# CC0# CC1# WE# DQC(u / l) As0-2 C1 C2 C3 C4 C5 C6 As3-11 C1 C2 C3 C4 C5 C6 G# L DQ0-15 Q1 D2 Q1+1 DES SR DES SR Burst address is not incremented by DES, SPD. "Insert wait" is possible. Q3 Q4 Q5 Q6 D1+2 SPD SPD DES SW SW SR SR SR SR ADF#=Low is equal to non-burst mode. M5M4V16169D keeps compatibility setting ADF# low or setting Burst length=1 by SCR cycle. (Ad7, Ad8 and Ad9=0) MITSUBISHI ELECTRIC (REV 1.0) Jul. 1998 24 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM **-15 spec is the same as M5M4V16169TP/RT-15 ABSOLUTE MAXIMUM RATINGS (Ta=0~70°C , Vdd=3.3±0.3V for -8,and -10, Vdd=3.3±0.15V for -7 Vss=0V, unless otherwise noted) Symbol Vcc Parameter Conditions Ratings Unit Supply Voltage Input Voltage Output Voltage Output Current With respect to Vss V V V mA VO IO Pd Topr Power Dissipation Operating Temperature -0.5 ~ 4.6 -0.5 ~ 4.6 -0.5 ~ 4.6 50 1000 0 ~ 70 Tstg Storage Temperature -65 ~ 150 VI mW °C °C RECOMMENDED OPERATING CONDITIONS (Ta=0~70°C , Vdd=3.3±0.3V for -8,and -10, Vdd=3.3±0.15V for -7 Vss=0V, unless otherwise noted) Symbol Vcc Vss VccQ Limits Parameter Min. Typ. Max Unit Supply Voltage 3.0 3.3 3.6 V 0 3.0 2.0 0 3.3 0 3.6 Vdd+0.3 V V V Vdd+0.3 VddQ+0.3 V 0.8 V V IH (LVTTL) Supply Voltage Supply Voltage for Output High-level Input Voltage clock and add. V IH V IH (LVTTL) High-level Input Voltage master clock (K) (LVTTL) High-level Input Voltage data pin 2.2 2.0 V IL (LVTTL) Low-level Input Voltage all inputs -0.3 V CAPACITANCE (Ta=0~70°C , Vdd=3.3±0.3V for -8,and -10, Vdd=3.3±0.15V for -7 Vss=0V, unless otherwise noted) Symbol CI(A) CI(C) CI/O Parameter Input Capacitance, Address pin Input Capacitance, Clock pin Input Capacitance, I/O pin MITSUBISHI ELECTRIC Test Condition V I=Vss f=1MHz V I =25mVrms Limits (MAX) 5 5 Unit pF pF 7 pF (REV 1.0) Jul. 1998 25 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM **-15 spec is the same as M5M4V16169TP/RT-15 AVERAGE SUPPLY CURRENT from Vcc (Ta=0~70°C , Vdd=3.3±0.3V for -8,and -10, Vdd=3.3±0.15V for -7 Vss=0V, unless otherwise noted) Symbol Condition IccS IccD IccD(PG) Limits (MAX) Unit -7 -8 -10 -15 Average supply current of SRAM operating, tK=min. DRAM=DPD output open data input=H or L 260 240 200 140 mA Average supply current of DRAM operating, tRC=min. SRAM=SPD 160 150 130 100 mA Average supply current of DRAM page-mode tPC=min. SRAM=SPD 140 130 110 80 mA LVTTL standby, tK=min, DRAM=DNOP&SRAM=DES, output open data input=H or L 60 60 50 30 mA 50 50 40 25 mA Icc(STN1) or NOP all input=stable. CMOS standby, tK=min, DRAM=DNOP&SRAM+DES, Icc(STN2) or NOP all input=stable. output open data input=H or L Icc(PD) CMOS Power Down current, CMd#=CMs#=L,tK=min. 5 5 5 5 mA Icc(SRF) CMOS Self Refresh current, CMd#=CMs#=L,tK= 1 1 1 1 mA AC OPERATING CONDITIONS AND CHARACTERISTICS (Ta=0~70°C , Vdd=3.3±0.3V for -8,and -10, Vdd=3.3±0.15V for -7 Vss=0V, unless otherwise noted) Symbol Parameter VOH(DC)*(LVTTL) High-level Output Voltage (DC) VOL(DC)*(LVTTL) Low-level Output Voltage (DC) Off-state Output Current Input Current IOZ II Limits Test Condition Min. Max 2.4 - 0.4 -10 -10 10 10 IOH= -2mA IOL= 2mA Q floating V O =0 ~VddQ VIH =0 ~ VddQ+0.3V Unit V V uA uA * VOH(AC) and VOL(AC) are the reference levels for AC measurements. VOH(DC) and VOL(DC) are the final levels the outputs reach. VTT 50ohm VOUT 30pF AC Condition (Access Time) MITSUBISHI ELECTRIC (REV 1.0) Jul. 1998 26 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM **-15 spec is the same as M5M4V16169TP/RT-15 TIMING REQUIREMENTS (CLK pulse, input signals setup / hold time to CLK edge) (Ta=0~70°C , Vdd=3.3±0.3V for -8,and -10, Vdd=3.3±0.15V for -7 Vss=0V, unless otherwise noted) Input Pulse Levels: Input Timing Measurement Reference Level: VIH=3.0V,VIL=0.0V (LVTTL) 1.5V (LVTTL) Limits Symbol -7 Parameter Min. tK tKH tKL tS tH Clock Cycle Time Clock High Pulse Width Clock Low Pulse Width Setup Time for Inputs Hold Time for Inputs MITSUBISHI ELECTRIC 7 3 3 3 1 -8 Max Min. 8 3 3 3 1 Max -10 Min. Max -15 Min. Max 10 3.5 4 3 1 15 5 5 4 1 (REV 1.0) Jul. 1998 Unit ns ns ns ns ns 27 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM **-15 spec is the same as M5M4V16169TP/RT-15 TIMING REQUIREMENTS (Read, Write, Refresh) (Ta=0~70°C , Vdd=3.3±0.3V for -8,and -10, Vdd=3.3±0.15V for -7 Vss=0V, unless otherwise noted) Input Pulse Levels: Input Timing Measurement Reference Level: VIH=3.0V,VIL=0.0V (LVTTL) 1.5V (LVTTL) Limits Symbol Min. tREF Refresh Cycle Time tRP tRCD Precharge Time Delay Time, Add Strb. Row to Col. tRC* DRAM Activate-Read Cycle Time DRAM Activate-Write Cycle Time Page Cycle Time tWC* tPC tRAS tRASP tRWL tRSH Activate Time Page mode Activate Time Write to Precharge Lead Time Read to Precharge Hold Time -8 -7 Parameter Max Min. 64 21 21 70 70 14 49 49 14 14 10,000 100,000 Max -10 Min. Max 64 24 24 80 80 16 56 56 16 16 10,000 100,000 -15 Min. Max 64 30 30 90 90 20 60 60 20 20 10,000 100,000 64 40 30 120 120 30 70 70 20 20 Unit ms ns ns ns ns 12,000 100,000 ns ns ns ns ns *Note: When tRP and tRAS = Min. values, tRC and tWC = tRP + tRAS. MITSUBISHI ELECTRIC (REV 1.0) Jul. 1998 28 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM **-15 spec is the same as M5M4V16169TP/RT-15 SWITCHING CHARACTERISTICS (Ta=0~70°C , Vdd=3.3±0.3V for -8,and -10, Vdd=3.3±0.15V for -7 Vss=0V, unless otherwise noted) Limits Symbol Parameter tCBF tKHA tKHQX tKHQZ tKHAR tKHQXR Buffer-Fill from DRAM Read Transfer tKHQZR tGLA tGLQ tGHQ Output Disable Time from K-High Edge -7 Min. Max -8 Min. 20 Max -10 Min. Max 20 20 10 Access Time from K-High Edge 2 2 Output Active Time from K-High Edge Output Disable Time from K-High Edge Access Time from K-High Edge Output Active Time from K-High Edge Access Time from G#-Low Edge Output Active Time from G#-Low Edge Output Disable Time from G#-High Edge MITSUBISHI ELECTRIC 5.6 2 2 0 2 7 5.6 5.6 6.4 2 2 0 2 8 6.4 6.4 -15 Min. Max 2 2 0 2 10 7 10 7 20 15 3 3 12 3 3 8 (REV 1.0) Jul. 1998 5 Unit ns ns ns ns ns ns ns ns ns ns 29 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM non-G# controlled Write & Read (DES control) ( SRAM Read/Deselect SRAM/SRAM Write/SRAM Power-down ) 2 3 As0-2 C1 As3-9 C1 1 4 5 6 8 9 C2 C3 C4 C5 C6 C2 C3 C4 C5 C6 7 10 11 12 13 14 K CMs# CS# CC0# CC1# WE# DQC(u / l) G# L DQ0-15 D1 DES SW Q2 SR DES SW Note : Output is transparent. MITSUBISHI ELECTRIC Q4 D3 SR Q6 D5 DES SW SR SPD SPD SPD DES DRAM operation can be freely performed. (REV 1.0) Jul. 1998 30 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM G# controlled Write & Read ( SRAM Read/Deselect SRAM/SRAM Write/SRAM Power-down ) 2 3 As0-2 C1 As3-9 C1 1 4 8 9 10 11 12 C2 C3 C4 C5 C6 C7 C2 C3 C4 C5 C6 C7 5 6 7 14 13 K CMs# CS# H L CC0# CC1# WE# DQC(u / l) G# DQ0-15 Q2 D1 Q5 D4 Q6 Q7 Q3 DES SW SR Note : Output is transparent. MITSUBISHI ELECTRIC SPD SPD SPD DES SR SW SR SR SR DES DRAM operation can be freely performed. (REV 1.0) Jul. 1998 31 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM DQC controlled Write & Read ( SRAM Read/Deselect SRAM/SRAM Write/SRAM Power-down ) 2 3 As0-2 C1 C2 C3 As3-9 C1 C2 C3 1 4 6 8 9 C4 C5 C6 C4 C5 C6 5 7 10 11 12 13 14 K CMs# CS# CC0# CC1# WE# DQCu DQCl L G# DQ8-15 D1 Q2 DQ0-7 D1 Q2 DES SW (u/l) SR Q6 D5 D3 Q4 DES SW (u/l) (l) SR (l) DES SW (u) SR SPD SPD SPD DES (u) H or L Note : Output is transparent. MITSUBISHI ELECTRIC DRAM operation can be freely performed. (REV 1.0) Jul. 1998 32 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM Registered Output control ( SRAM Read/Deselect SRAM/SRAM Write/SRAM Power-down ) 2 3 4 5 6 7 8 9 As0-2 C1 C2 C3 C4 C5 C6 C7 C8 As3-9 C1 C2 C3 C4 C5 C6 C7 C8 1 10 11 12 13 14 K CMs# CS# CC0# CC1# WE# DQC(u / l) L G# DQ0-15 D1 DES SW D3 SR Note : Output is registered. MITSUBISHI ELECTRIC Q2 SW D5 SR Q4 SW D7 SR Q6 SW Q8 SR DES SPD SPD DES DRAM operation can be freely performed. (REV 1.0) Jul. 1998 33 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM Buffer Read Transfer (RB2 -> SRAM) Buffer Read Transfer & SRAM Read (RB2 -> SRAM -> Output) 1 2 3 4 5 6 7 8 9 10 C1 C2 C3 C4 C5 C6 C7 C8 (C1) (C1) (C1) (C1) (C5) (C5) (C5) (C5) Q5 Q6 Q7 11 12 13 14 K CMs# CS# H L CC0# CC1# WE# DQC(u / l) As0-2 As3-9 G# (C1) L Q2 Q1 DQ0-15 DES BRT SR Note : Output is transparent. MITSUBISHI ELECTRIC SR Q3 SR Q4 SR BRTR SR SR Q8 SR DES DES DES DES DRAM operation can be freely performed. (REV 1.0) Jul. 1998 34 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM Buffer Write Transfer (SRAM -> WB1) Buffer Write Transfer & SRAM Write (Input -> SRAM -> WB1) 2 1 4 3 5 6 7 8 9 10 11 12 13 14 K CMs# CS# H L CC0# CC1# WE# DQC(u / l) C2 As0-2 As3-9 G# C1 C2 C3 L WB1(0-7) D1 old DQ0-15 D3 D2 D2 DES DES BWT DES Note : Output is transparent. MITSUBISHI ELECTRIC DES BWTW DES DES BWT DES DES DES DES DES DRAM operation can be freely performed. (REV 1.0) Jul. 1998 35 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM Buffer Write (Input -> WB1) Buffer Read (RB2 -> Output) 1 2 3 4 C1 C2 C3 C4 5 6 7 8 9 10 11 C5 C6 C7 12 13 14 K CMs# CS# H L CC0# CC1# WE# DQC(u / l) As0-2 C8 As3-9 G# L WB1(0-7) D1 D2 D3 D4 WB1 Mask(0-7) D1 D2 D3 D4 DQ0-15 D2 D1 BW BW Q5 D4 D3 BW Note : Output is transparent. MITSUBISHI ELECTRIC BW DES DES DES DES BR Q7 Q6 BR BR Q8 BR DES DES DRAM operation can be freely performed. (REV 1.0) Jul. 1998 36 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM NO - Operation of SRAM 1 2 3 4 5 6 7 8 9 10 11 12 13 14 K CMs# H CS# CC0# CC1# WE# DQC(U / l) AS0-9 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NO-Operation Mode CMd# RAS# CAS# DRAM operation can be freely performed. DTD# Ad0-11 MITSUBISHI ELECTRIC (REV 1.0) Jul. 1998 37 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM NO - Operation of DRAM 1 2 3 4 5 6 7 8 9 10 11 12 13 14 K CS# H CMd# RAS# CAS# DTD# Ad0-11 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NO-Operation Mode CMs# CC0# CC1# WE# SRAM operation can be freely performed. DQC(u/l) G# As0-9 DQ0-15 MITSUBISHI ELECTRIC (REV 1.0) Jul. 1998 38 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM DRAM Power Down / DRAM Activate / DRAM Precharge 1 2 3 4 5 6 7 8 9 10 11 12 13 14 K CMd# CS# RAS# CAS# DTD# Ad0-11 Row DPD DPD DPD ACT DNOP DNOP DNOP DNOP PCG DPD DPD DPD DPD CMs# CC0# CC1# WE# DQC(u/l) SRAM operation can be freely performed. G# As0-9 DQ0-15 DPD is recommended during no operation to save power. MITSUBISHI ELECTRIC (REV 1.0) Jul. 1998 39 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM RAS only Refresh cycle DRAM Power Down / DRAM Activate / DRAM Precharge 1 2 4 3 6 5 7 8 9 10 11 12 13 14 K CMd# CS# tRC tRAS tRP RAS# CAS# DTD# Ad0-11 Row DPD PCG DPD DPD ACT DNOP DNOP DNOP DNOP PCG DPD DPD DPD CMs# CC0# CC1# WE# DQC(u/l) SRAM operation can be freely performed. G# As0-9 DQ0-15 MITSUBISHI ELECTRIC (REV 1.0) Jul. 1998 40 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM DRAM Auto Refresh 1 2 3 H H 4 5 6 7 8 9 10 11 12 13 14 K CMd# H H tRC CS# RAS# CAS# DTD# Ad0-11 DPD DPD ARF DNOP DPD DPD DPD DPD DPD DPD ARF DNOP DNOP DNOP CMs# Note: DRAM must be in Precharge state prior to Auto-Refresh cycle. DRAM new commands except for NOP,DNOP and DPD can be set after tRC later from ARF command input. CC0# CC1# WE# DQC(u/l) SRAM operation can be freely performed. G# As0-9 DQ0-15 MITSUBISHI ELECTRIC (REV 1.0) Jul. 1998 41 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM DRAM Self Refresh 1 2 3 1 4 2 3 4 5 6 K Inhibit falling edge. CMd# H L CS# L RAS# L CAS# L DTD# H H Row Ad0-11 DNOP DNOP SRF Halt Halt Halt DNOP DNOP DNOP DNOP ACT DNOP Self Refresh Mode SRAM Power Down Mode Self Refresh Entry tRC for Recovery Self Refresh SRAM Power Down Exit Self Refresh Entry: (Note: DRAM must be in Precharge state prior to Self-Refresh Entry) Previous CMd#=H, Present CMd#=L, CS#=RAS#=CAS#=L, DTD#=H (CMd# must remain low to maintain Self Refresh). Self Refresh Exit (in order): a) resume K clock b) CMd#=H c) Wait tRC for recovery d) Resume normal operation MITSUBISHI ELECTRIC (REV 1.0) Jul. 1998 42 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM DRAM Read Transfer (DRAM -> RB1-> RB2) Latency set=1 2 1 4 3 6 5 8 7 10 9 11 12 13 14 K tRC CMd# CS# tRAS tRP RAS# tRCD tRSH CAS# DTD# Row Ad0-2 Ad0-Ad2=Low **Col Row Ad3-11 tCBF New Data Old Data RB1 Latency x tK DRAM SRAM DQ0-15 New Data Old Data RB2 DPD DPD PCG DPD DPD DPD ACT BR Old BR Old BR BR Old SRAM operation can be freely performed. MITSUBISHI ELECTRIC Old BR Old BR Old BR Old DNOP DRT DNOP BR BR BR Old Old PCG DPD DPD DPD BR BR BR BR New New New New New ** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998 43 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM DRAM Read Transfer (DRAM -> RB1-> RB2) Latency set=2 2 1 4 3 6 5 8 7 10 9 11 12 13 14 K tRC CMd# CS# tRAS tRP RAS# tRCD tRSH CAS# DTD# Row Ad0-2 Ad0-Ad2=Low Row Ad3-9 **Col tCBF New Data Old Data RB1 Latency x tK RB2 DRAM SRAM DQ0-15 New Data Old Data DPD DPD PCG DPD DPD DPD ACT BR Old BR Old BR Old BR Old SRAM operation can be freely performed. MITSUBISHI ELECTRIC BR Old BR Old BR Old DNOP DRT DNOP BR BR BR Old Old PCG DPD DPD DPD BR BR BR BR Old New New New New ** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998 44 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM DRAM Read Transfer (DRAM -> RB1-> RB2) Latency set=3 2 1 4 3 6 5 8 7 10 9 12 11 13 14 K tRC CMd# CS# tRAS tRP RAS# tRCD tRSH CAS# DTD# Ad0-2 Row Ad0-Ad2=Low Row Ad3-11 **Col tCBF Old Data RB1 New Data Latency x tK RB2 DRAM SRAM DQ0-15 Old Data New Data DPD DPD PCG DPD DPD DPD ACT BR Old BR Old BR Old BR Old SRAM operation can be freely performed. MITSUBISHI ELECTRIC BR Old BR Old BR Old DNOP DRT DNOP BR BR BR Old Old Old PCG DPD DPD DPD BR BR BR BR Old New New New ** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998 45 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM DRAM Read Transfer (DRAM -> RB1-> RB2) Latency set=4 2 1 4 3 6 5 8 7 10 9 11 12 13 14 K tRC CMd# CS# tRAS tRP RAS# tRCD tRSH CAS# DTD# Row Ad0-2 Ad0-Ad2=Low Row Ad3-11 **Col tCBF Old Data RB1 New Data Latency x tK RB2 DRAM DPD DPD PCG DPD DPD DPD ACT SRAM BR DQ0-15 New Data Old Data Old BR Old BR Old BR Old SRAM operation can be freely performed. MITSUBISHI ELECTRIC BR BR Old Old DNOP DRT DNOP PCG DNOP DPD DPD BR BR BR BR BR BR BR Old Old Old Old Old BR Old New New ** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998 46 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM Page-Mode DRAM Read Transfer (Pipe-lined Page-Mode) Latency set=1 2 1 4 3 6 5 8 7 10 9 12 11 13 14 K CMd# CS# tRASP RAS# tPC tPC tPC tPC tPC tRSH tRCD CAS# DTD# Ad0-2 Row Ad0-Ad2=Low Ad3-11 Row **C1 **C2 tCBF tCBF RB1 **C3 DRAM DPD ACT SRAM BR DQ0-15 C1 Old Data Old BR Old DNOP BR **C6 C3 C4 C5 C3 C2 C4 C5 DRT DNOP DRT DNOP DRT DRT DRT DRT BR BR BR BR BR Old Old Q1 Q1 C6 Latency Latency Latency Latency x tK x tK x tK x tK Latency x tK Latency x tK RB2 **C5 tCBF tCBF tCBF tCBF C2 C1 Old Data **C4 Q2 Q2 BR BR Q3 Q4 BR Q5 C6 DNOP PCG BR BR Q6 Q6 BR Q6 Pipe-lined Page mode SRAM operation can be freely performed. MITSUBISHI ELECTRIC ** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998 47 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM Page-Mode DRAM Read Transfer Latency set=2 2 1 4 3 6 5 8 7 10 9 12 11 13 14 K CMd# CS# tRASP RAS# tPC tPC tRSH tRCD CAS# DTD# Ad0-2 Row Ad0-Ad2=Low Ad3-11 Row **C1 **C2 tCBF tCBF RB1 C1 Old Data Old Data DRAM SRAM DQ0-15 DPD ACT BR Old BR Old C2 **C6 C4 C3 DNOP DRT DNOP BR BR BR BR BR Q1 C6 C2 DRT Old C6 C5 tCBF DNOP Old **C5 tCBF tCBF tCBF tCBF C1 Old **C4 tCBF tCBF RB **C3 Q1 DRT DRT DRT DRT BR BR Q2 BR Q2 Q2 BR Q2 DNOP PCG BR BR Q2 BR Q6 Q6 If next DRT happens within the latency, new data does not transferred to RB. However this operation is not guaranteed. SRAM operation can be freely performed. MITSUBISHI ELECTRIC ** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998 48 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM Page-Mode DRAM Read Transfer Latency set=3 2 1 4 3 6 5 8 7 10 9 12 11 14 13 K CMd# CS# tRASP RAS# tPC tRCD tPC tRSH CAS# DTD# Ad0-2 Row Ad0-Ad2=Low Ad3-11 Row **C1 **C2 C1 Old Data C2 Latency x tK RB2 Latency x tK C1 DPD ACT DNOP DRT DNOP DNOP DRT DNOP DNOP SRAM BR BR BR BR BR BR DQ0-15 Old Old Old Old Old Old Q1 C4 C2 DRAM BR C4 C3 Latency x tK Old Data BR **C4 tCBF tCBF tCBF tCBF RB1 **C3 Q1 DRT DRT BR BR Q1 Q2 BR Q2 DNOP PCG BR BR Q2 Q2 BR Q4 If next DRT happens within the latency, new data does not transferred to RB. However this operation is not guaranteed. SRAM operation can be freely performed. MITSUBISHI ELECTRIC ** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998 49 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM Page-Mode DRAM Read Transfer Latency set=4 2 1 4 3 6 5 8 7 9 10 12 11 14 13 K CMd# CS# tRASP RAS# tPC tRCD tRSH CAS# DTD# Ad0-2 Row Ad0-Ad2=Low Ad3-11 Row **C1 **C2 tCBF tCBF Old Data RB **C3 tCBF C3 C2 C1 Latency x tK Latency x tK RB C1 Old Data DRAM DPD ACT SRAM BR DQ0-15 Old BR Old DNOP DRT BR BR Old Old DNOP DNOP BR Old BR Old C3 DNOP DRT DNOP DRT BR BR BR BR Old Q1 Q1 DNOP DNOP Q1 BR Q1 BR Q1 PCG BR Q1 BR Q3 If next DRT happens within the latency, new data does not transferred to RB. However this operation is not guaranteed. SRAM operation can be freely performed. MITSUBISHI ELECTRIC ** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998 50 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM DRAM Write Transfer 1 (WB1->WB2->DRAM) Buffer Write (DIN->WB1) 1 2 4 3 6 5 8 7 10 9 11 12 13 14 K tRC CMd# CS# tRP tRAS RAS# tRCD tRWL CAS# DTD# Row Ad0-2 Ad0-Ad2=Low Row Ad3-11 WB2 **Col New Data[WB1(0-7)] Old Data WB1 C0 C1 C2 C3 C4 C5 DRAM DPD DPD PCG DPD DPD DPD ACT SRAM DES BW DQ0-15 D0 D1 BW BW D2 BW D4 D3 BW D5 BW D6 C6 DNOP BW D7 C7 C0 C1 C2 C3 C4 DWT1 DNOP PCG DPD DPD DPD BW BW D0 D1 BW D2 BW D3 BW D4 BW D5 Please refer to next page in detail. SRAM operation can be freely performed. MITSUBISHI ELECTRIC ** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998 51 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM DRAM Write Transfer 1 (WB1->WB2->DRAM) Buffer Write (DIN->WB1) 1 2 4 3 detail 6 5 8 7 10 9 12 11 14 13 K tRC CMd# CS# tRP tRAS RAS# tRCD tRWL CAS# DTD# Ad0-2 Row Ad0-Ad2=Low Row Ad3-11 WB2 [0-7] **Col New Data[from WB1(0-7)] Old Data WB1[0] WB1 mask[0] 0 0 1 WB1[1] WB1 mask[1] 1 WB1[2] WB1 mask[2] 2 2 WB1[3] WB1 masl[3] 3 3 WB1[4] WB1 mask[4] 4 WB1[5] WB1 mask[5] 4 5 WB1[6] WB1 mask[6] 6 7 WB1[7] WB1 mask[7] DRAM SRAM DQ0-15 DPD DPD PCG DPD DPD DPD ACT DNOP DWT1 DNOP PCG DPD DPD DPD DES BW BW BW BW BW BW BW BW BW BW BW BW BW D0 D1 D2 MITSUBISHI ELECTRIC D3 D4 D5 D6 D7 D0 D1 D2 D3 (REV 1.0) Jul. 1998 D4 D5 52 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM DRAM Write Transfer 1 (WB1->WB2->DRAM) Buffer Write Transfer (SRAM->WB1) 2 1 4 3 6 5 8 7 9 10 12 11 14 13 K tRC CMd# CS# tRP tRAS RAS# tRCD tRWL CAS# DTD# Row Ad0-2 Ad0-Ad2=Low Row Ad3-11 WB2 Old Data WB1 Old Data **Col New Data[WB1(0-7)] New Data Next New Data DRAM DPD DPD PCG DPD DPD DPD ACT DNOP DWT1 DNOP PCG DPD DPD DPD SRAM SW SW BWT BWT SW DQ0-15 D0 D1 SW D2 SW SW D3 SW D4 D5 SW D6 SW D7 D0 D1 SW SW D2 SW D3 Please refer to next page in detail. SRAM operation can be freely performed. MITSUBISHI ELECTRIC ** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998 53 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM DRAM Write Transfer 1 (WB1->WB2->DRAM) Buffer Write Transfer (SRAM->WB1) 1 2 3 4 5 detail 6 7 8 10 9 11 12 14 13 K tRC CMd# CS# tRP tRAS RAS# tRCD tRWL CAS# DTD# Row Ad0-2 Ad0-Ad2=Low Ad3-11 Row WB2 [0-7] **Col New Data[from WB1(0-7)] Old Data WB1[0] WB1 mask[0] 0 0 WB1[1] WB1 mask[1] 1 1 WB1[2] WB1 mask[2] 2 2 WB1[3] WB1 masl[3] 3 3 WB1[4] WB1 mask[4] 4 4 WB1[5] WB1 mask[5] 5 5 WB1[6] WB1 mask[6] 6 6 WB1[7] WB1 mask[7] 7 7 DPD DPD PCG DPD DPD DPD ACT DNOP DWT1 DNOP PCG DPD DPD DPD SW SW SW SW SW SW SW SW BWT BWT SW SW SW SW DRAM SRAM DQ0-15 D0 D1 D2 D3 MITSUBISHI ELECTRIC D4 D5 D6 D7 D0 D1 D2 (REV 1.0) Jul. 1998 D3 54 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM Page-Mode DRAM Write Transfer 1 (WB1->WB2->DRAM) Buffer Write (DIN->WB1) 1 2 4 3 6 5 8 7 10 9 12 11 14 13 K CMd# CS# tRP tRASP RAS# tPC tRCD tRWL CAS# DTD# Row Ad0-2 Ad0-Ad2=Low Ad0-Ad2=Low **Col Row Ad3-11 WB2 New Data[WB1(0-7)] Old Data C0 WB1 C1 C2 C3 C4 C5 DRAM DPD DPD PCG DPD DPD DPD ACT SRAM DES BW DQ0-15 D0 BW D1 BW D2 BW D3 BW D4 D5 **Col BW C6 C7 Next Data[WB1(0-1)] C0 C1 DNOP DWT1 DNOP DWT1 BW BW D6 D7 BW D0 BW D1 C2 C3 C4 DPD DNOP PCG BW D2 D3 BW BW D4 D5 Please refer to next page in detail. SRAM operation can be freely performed. MITSUBISHI ELECTRIC ** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998 55 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM Page-Mode DRAM Write Transfer 1 (WB1->WB2->DRAM) Buffer Write (DIN->WB1) 1 2 4 3 6 5 detail 8 7 10 9 12 11 14 13 K CMd# CS# tRP tRASP RAS# tPC tRCD tRWL CAS# DTD# Row Ad0-2 Ad0-Ad2=Low Ad0-Ad2=Low Ad3-11 Row WB2 [0-7] **Col New Data [from WB1(0-7)] Old Data WB1[0] WB1 mask[0] 1 1 WB1[2] WB1 mask[2] 2 2 WB1[3] WB1 masl[3] 3 3 WB1[4] WB1 mask[4] 4 4 WB1[5] WB1 mask[5] 5 WB1[6] WB1 mask[6] 6 7 WB1[7] WB1 mask[7] DQ0-15 Next Data[WB1(0-1)] 0 0 WB1[1] WB1 mask[1] DRAM SRAM **Col DPD DPD PCG DPD DPD DPD ACT DES BW BW BW BW BW BW 0 1 2 MITSUBISHI ELECTRIC 3 4 5 6 DWT1 DNOP DWT1 DNOP PCG DPD BW BW BW BW BW BW BW DNOP 7 0 1 2 3 (REV 1.0) Jul. 1998 4 5 56 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM DRAM Write Transfer 1&Read (WB1->WB2->DRAM->RB) Latency set=1 Buffer Write (DIN->WB1) 2 1 4 3 6 5 8 7 10 9 11 12 13 14 K tRC CMd# CS# tRP tRAS RAS# tRCD tRWL CAS# DTD# Ad0=High Row Ad0-2 Ad1-Ad2=Low Row Ad3-11 WB2 **Col Old Data WB1 0 2 1 4 3 New Data[WB1(0-7)] 5 6 7 DRAM SRAM DQ0-15 Latency x tK New Data[WB1(0-7)] Old Data DPD DPD PCG DPD DPD DPD ACT DES BW BW BW BW BW BW 0 1 4 3 New Data[WB1(0-7)] Old Data tCBF RB2 2 1 tCBF tCBF RB1 0 2 3 4 5 6 DNOP DWT1R DNOP BW 7 BW BW 0 1 PCG DPD DPD DPD BW BW BW BW 2 3 4 5 New Data on RB appears as to latency set count. See DRT timing chart. SRAM operation can be freely performed. MITSUBISHI ELECTRIC ** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998 57 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM DRAM Write Transfer 2 (WB2->DRAM) 1 3 2 5 4 7 6 9 8 11 10 13 12 14 K CMd# CS# tRP tRASP RAS# tPC tRCD tRWL CAS# DTD# Ad1=High Row Ad0-2 Ad0-Ad2=Low Ad0,Ad2=Low Row Ad3-11 **Col **Col NoChange WB2 New Data[WB1(0-7)] Old Data 0 WB1 1 2 3 4 5 DRAM DPD DPD PCG DPD DPD DPD ACT SRAM DES BW DQ0-15 0 BW 1 BW BW 2 SRAM operation can be freely performed. MITSUBISHI ELECTRIC 3 BW BW 4 5 6 0 1 2 3 DNOP DWT1 DNOP DWT2 DNOP PCG BW BW 6 7 7 BW BW 0 1 BW BW 2 3 4 DPD BW 4 5 ** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998 58 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM DRAM Write Transfer2 & Read (WB2->DRAM->RB1-> RB2) Latency set=1 1 3 2 5 4 7 6 9 8 11 10 13 12 14 K CMd# CS# tRP tRASP RAS# tPC tRCD tRWL CAS# DTD# Ad0,Ad1=High Row Ad0-2 Ad0-Ad2=Low Ad2=Low **Col Row Ad3-11 **Col NoChange WB2 New Data[WB1(0-7)] Old Data WB1 0 2 1 4 3 5 6 7 0 2 1 3 4 tCBF RB1 New Data[WB1(0-7)] Old Data Latency x tK RB1 New Data[WB1(0-7)] Old Data DRAM DPD DPD PCG DPD DPD DPD ACT SRAM DES BW DQ0-15 0 BW 1 BW BW 2 3 BW BW 4 5 DNOP DWT1 DNOP DWT2 DNOP BW BW 6 7 BW BW 0 1 BW BW 2 PCG DPD 3 BW 4 5 New Data on RB appears as to latency set count. See DRT timing chart. SRAM operation can be freely performed. MITSUBISHI ELECTRIC ** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998 59 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM This page is left blank, so that the Set Command Register Timing Diagram on the next spread can be seen conveniently. MITSUBISHI ELECTRIC (REV 1.0) Jul. 1998 60 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM Set Command Register (1) 1 2 3 4 5 6 8 7 9 10 11 12 13 14 K CMd# CS# RAS# CAS# DTD# CMD Ad0-11 DPD DPD DPD DPD DPD DPD Row SCR DPD DPD DPD ACT DNOP DNOP DNOP *Set Command Reg. Inhibit new command except for DNOP,DPD DES,SPD and NOP. MITSUBISHI ELECTRIC (REV 1.0) Jul. 1998 61 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM Set Command Register(2) Address Input Ad11 Ad10 Ad9 Ad8 Ad7 Ad6 Ad5 Ad4 Command Ad3 Ad2 Ad1 Ad0 L L L L L L L L L L L H L L L L L L L L L L H L L L L L L H L L L L L L L L L L L L H L L L L H L L L L H H L L L L L L L L L L L L L L H L L L L H L L L L L H H L L L L L L L H L L L L L L L L L L L L L No operation Set All WB1 Xfer Masks Default Output ModeTransparent Output Mode Latched Output Mode Registered Latency 1 Latency 2 Latency 3 Latency 4 Default BL=1 BL=2 BL=4 BL=8 Sequential Interleave Default Default K CMd# * Latency is the number of clock cycles required to transfer new data from the DRAM to the Read Buffer . Therefore, it can be adjusted to the clock frequency of the system. (Latency) x (tK) should meet tCBF min. timing requirement. CS# RAS# CAS# DTD# Ad0~11 Command SCR Inhibit new read or write function during these 4 clocks. MITSUBISHI ELECTRIC (REV 1.0) Jul. 1998 62 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM Burst Mode Address Initial Address Interleaved Sequential BL As2 As1 As0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 8 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 0 0 0 0 1 2 3 0 1 2 3 - 0 1 1 2 3 0 1 0 3 2 4 - 1 0 2 3 0 1 2 3 0 1 - 1 1 3 0 1 2 3 2 1 0 - - 0 0 1 0 1 - - 1 0 1 0 1 2 Note: When SRAM command is executed more than burst length, the Address repeats with the same sequence. MITSUBISHI ELECTRIC (REV 1.0) Jul. 1998 63 MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM 70P3S Package Dimension 70 A 36 70P3S-L 1 35 1 35 0.125 +0.05 -0.02 +0.02 (0.005 -0.0008 ) 70P3S-M 0.5+-0.1 (0.02+-0.004) Detail A 70 *3 0.65+-0.1 0.3 (0.026+-0.004) +0.004 -0.05 mm (INCH) 36 +0.1 -0.05 (0.012 UNIT : ) *2 23.49+-0.1 (0.925+-0.004) 0.1 (0.004) Note) MITSUBISHI ELECTRIC Dimension *1, *2 do not include mold flash. Dimension *3 does not include tie - bar cut remain. (REV 1.0) Jul. 1998 64