MITSUBISHI<Dig.Ana.INTERFACE> M62367GP 3V TYPE 8-BIT 8CH D-A CONVERTER WITH BUFFER AMPLIFIERS PIN CONFIGURATION (TOP VIEW) DESCRIPTION VSS (VrefL) Ao2 The M62367GP is a CMOS semiconductor IC has 8 channels of 8bit D-A converter. It is operable with a low supply voltage between 2.7~3.6V,and is easy to use due to serial data input,and 3pin(DI,CLK,LD)connection with microcomputer. The IC also contains Do pin terminal,enabling cascade connection,and therefore is suitable for automatic control in combination with a microcomputer. 1 16 GND 2 15 Ao1 Ao3 3 14 DI Ao4 4 13 CLK Ao5 5 12 LD Ao6 6 11 Do Ao7 7 10 Ao8 VDD (VrefU) 8 9 Vcc FEATURES •Operable with a low voltage between 2.7~3.6V •12-bit serial data input(connected via 3 pins:DI,CLK,LD) •8 channels of R-2R and segment type high-performance 8-bit D-A converters •8 buffer operational amplifiers with full swing of output voltage between Vcc and GND. •High oscillation stability against the capacitive load of buffer operational amplifiers. Outline 16P2E-A APPLICATION Digtal-analog conversion in industrial or home-use electronic equipment. Automatic control in combination with EEPROM and microcomputer(Substitute for conventional semi-fixed resistor) BLOCK DIAGRAM GND Ao1 DI CLK LD Do Ao8 16 15 14 13 12 11 10 Vcc 9 - 12-BIT SHIFT REGISTER 8-BIT R-2R + SEGMENT D-A CONVERTER D-A D0 1 2 3 4 5 D7 D8 9 10 D11 8-BIT LATCH L ADDRESS DECODER (8) (8) 8-BIT LATCH 8-BIT R-2R + SEGMENT D-A CONVERTER - 1 Vss (VrefL) L L L L L D-A D-A D-A D-A D-A - - - - - 2 3 4 5 6 7 8 Ao2 Ao3 Ao4 Ao5 Ao6 Ao7 VDD (VrefU) MITSUBISHI ELECTRIC ( 1 / 5 ) MITSUBISHI<Dig.Ana.INTERFACE> M62367GP 3V TYPE 8-BIT 8CH D-A CONVERTER WITH BUFFER AMPLIFIERS EXPLANATION OF TERMINALS Pin No. 14 11 13 Function Serial data input terminal to input 12-bit long serial data Terminal to output MSB data of 12-bit shift register Symbol DI Do CLK 12 Shift clock input terminal.Input signal at DI pin is input to 12-bit shift register at rise of shift clock pulse When H-level signal is input to this terminal.The value stored in 12-bit shift register is loaded in decoder and D-A converter output register LD Ao1 15 2 Ao2 Ao3 3 4 5 9 16 Ao4 Ao5 Ao6 Ao7 Ao8 VCC GND GND terminal 8 1 VDD VSS D-A converter lower reference voltage input terminal 6 7 10 8-bit D-A converter output terminal Power supply terminal D-A converter upper reference voltage input terminal BLOCK DIAGRAM FOR EXPLANATION OF TERMINALS DI Vcc GND 9 16 14 12-BIT SHIFT REGISTER CLK 13 D0 D1 D2 D3 D4 D5 D6 11 Do D7 D8 D9 D10 D11 ADDRESS DECODER 8 8 D0 ............ 8-BIT LATCH 1 8-BIT R-2R + SEGMENT D-A CONVERTER 1 2 3 4 5 6 7 8 D7 D0 .............................................8 .............................................. ................................................................................................... - 12 LD ............ 8-BIT LATCH 8-BIT R-2R + SEGMENT D-A CONVERTER - 8 15 10 VDD (VrefU) Ao1 Ao8 MITSUBISHI ELECTRIC D7 1 Vss (VrefL) ( 2 / 5 ) MITSUBISHI<Dig.Ana.INTERFACE> M62367GP 3V TYPE 8-BIT 8CH D-A CONVERTER WITH BUFFER AMPLIFIERS DIGITAL DATA FORMAT FIRST MSB LAST LSB DAC DATA DAC SELECT DATA D0 0 D1 D2 D3 D4 D5 D6 D7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 (VrefU-VrefL) / 256 X 3 +VrefL 1 1 0 0 0 0 0 0 (VrefU-VrefL) / 256 X 4 +VrefL 0 1 1 1 1 1 1 1 (VrefU-VrefL) / 256 X 255 +VrefL 1 1 1 1 1 1 1 1 D8 D9 D10 D11 0 0 0 0 DAC selection Don‘t care 0 0 0 1 Ao1 selection 0 0 1 0 Ao2 0 1 0 1 Ao3 0 0 1 0 Ao4 Ao5 0 0 1 1 0 1 1 1 0 1 0 1 Ao6 Ao7 0 Ao8 0 0 1 Don't care 1 1 0 1 0 Don't care 0 1 1 Don't care 1 1 1 0 0 Don't care 1 0 1 Don't care 1 1 1 0 Don't care 1 1 1 1 Don't care 0 0 1 1 D-A output (VrefU-VrefL) / 256 X 1 +VrefL (VrefU-VrefL) / 256 X 2 +VrefL VrefU * VrefU=VDD VrefL=Vss TIMING CHART (MODEL) MSB DI D11 LSB D10 D9 D8 D2 D1 D0 CLK LD D-A OUTPUT MITSUBISHI ELECTRIC ( 3 / 5 ) MITSUBISHI<Dig.Ana.INTERFACE> M62367GP 3V TYPE 8-BIT 8CH D-A CONVERTER WITH BUFFER AMPLIFIERS ABSOLUTE MAXIMUM RATINGS Symbol Vcc VDD VIN Vo Pd Topr Tstg Conditions Parameter Supply voltage Upper reference voltage of D-A converter Input voltage Ratings Unit -0.3~+7.0 -0.3~+7.0 V V V V mW °C -0.3~VCC+0.3 -0.3~VCC+0.3 150 -20~+85 -40~+125 Output voltage Power dissipation Operating temperature Storage tempareture °C ELECTRICAL CHARACTERISTICS Digital part(VCC,VrefU=+3V±10%, VCC≥VrefU,GND,VrefL=0V,Ta=-20 ~ +85°C,unless otherwise noted) Symbol VCC Supply voltage Icc Circuit current Input leak current IILK VIL Test conditions Parameter Min. 2.7 CLK=1MHz operation,Vcc=3V,IAO=0µA VIN=0~VCC VIH Input low voltage Input high voltage VOL Output low voltage IOL=2.5mA VOH Output high voltage IOH=-400µA Limits Typ. 3.0 -10 Max. Unit 3.6 V 3.5 10 mA 0.2VCC V µA 0.8VCC V 0.4 V V VCC-0.4 Analog part(VCC,VrefU=+3V±10%, VCC≥VrefU,GND,VrefL=0V,Ta=-20 ~ +85°C,unless otherwise noted) Symbol IrefU VrefU VrefL VAO IAO SDL SL SZERO SFULL Co Ro Parameter Test conditions Current dissipation VrefU=3V,VrefL=0V Data condition:maximum current D-A converter upper reference voltage range D-A converter lower reference voltage range Reference voltage can not always be set to any value in this range,because it is restricted to the buffer amplifier output voltage range IAO=±100µA Buffer amplifier output driver voltage IAO=+500µA range -200µA Upper saturation voltage=0.4V Buffer amplifier output voltage Lower saturation voltage=0.4V range Differential nonlinearity error Vcc=2.760V Nonlinearity error VrefU=2.610V Zero code error VrefL=0.050V(10mV/LSB) Without load(IAO=±0) Full scale error Limits Typ. Max. 1.4 2.5 mA 0.7Vcc Vcc V GND 0.3Vcc V 0.1 Vcc-0.1 V 0.2 Vcc-0.2 V -0.3 1 mA -1.0 -1.5 -2 -2 1.0 1.5 2 2 LSB LSB LSB LSB 0.1 µF Ω Min. Output capacitative load Buffer amplifier output impedance 5 MITSUBISHI ELECTRIC Unit ( 4 / 5 ) MITSUBISHI<Dig.Ana.INTERFACE> M62367GP 3V TYPE 8-BIT 8CH D-A CONVERTER WITH BUFFER AMPLIFIERS AC CHARACTERISTICS(VCC,VrefU=+3V±10%, VCC≥VrefU,GND,VrefL=0V,Ta=-20 ~ +85°C,unless otherwise noted) Parameter Symbol tCKL tCKH tCR tCF tDCH tCHD tCHL tLDC tLDH tDo tLDD Test conditions Min 200 200 Clock "L"pulse width Clock "H"pulse width Clock rise time Clock fall time Data set up time Data hold time Limits Typ Max Unit 200 ns ns ns ns ns ns ns 100 100 ns ns 200 200 30 60 LD set up time LD hold time LD "H" pulse duration Data output delay time CL=100pF 70 CL≥100pF,VAO:0.1 2.6V The time until the output becomes the final value of 1/2 LSB D-A output setting time 350 ns 300 µs TIMING CHART tCKH tCR tCF CLK tCKL DI tDCH tLDC tCHD tLDH tCHL LD tLDD D-A OUTPUT tDo Do OUTPUT MITSUBISHI ELECTRIC ( 5 / 5 )