MITSUBISHI SEMICONDUCTORS <HVIC> M63994P/FP HIGH VOLTAGE HALF BRIDGE DRIVER DESCRIPTION M63994P/FP is high voltage Power MOSFET and IGBT module driver for half bridge applications. PIN CONFIGURATION (TOP VIEW) M63994P/FP VCC 1 FEATURES IN 2 ¡FLOATING SUPPLY VOLTAGE ................................. 600V ¡OUTPUT CURRENT ............................................. ±500mA ¡SINGLE INPUT TYPE ¡INTERNALLY SET DEADTIME ¡HALF BRIDGE DRIVER ¡UNDERVOLTAGE LOCKOUT ¡8 LEAD DIP/8 LEAD SOP GND 3 LO 4 8 VB 7 HO 6 VS 5 NC NC:NO CONNECTION PACKAGE TYPE (8 Lead DIP/8 Lead SOP) APPLICATIONS MOSFET and IGBT inverter module driver for refrigerator, air-conditioner, washing machine, AC-servomotor and general purpose. 8P4 8P2S BLOCK DIAGRAM VB VBS UV HV LEVEL SHIFT INTER LOCK R Q R HO S PULSE GEN VS IN VCC DEAD TIME VCC UV R Q LO DELAY S GND Sep. 2000 MITSUBISHI SEMICONDUCTORS <HVIC> M63994P/FP HIGH VOLTAGE HALF BRIDGE DRIVER ABSOLUTE MAXIMUM RATINGS Symbol Parameter High Side Floating Supply Voltage VB VS Conditions High Side Floating Supply Offset Voltage High Side Output Voltage Low Side Fixed Supply Voltage VHO VCC VLO Low Side Output Voltage Logic Input Voltage VIN dVS/dt Ratings –0.5~624 VB–24 ~ VB+0.5 Unit VS–0.5 ~ VB+0.5 –0.5 ~ 24 V V VS ~ VCC+0.5 –0.5 ~ VCC+0.5 V ±50 V V/ns 0.85(P)/0.6(FP) 8.5(P)/6.0(FP) W mW/°C 40(P)/50(FP) –20 ~ +125 °C/W °C –20 ~ +100 –40 ~ +125 °C °C Allowable Offset Supply Voltage Transient Pt On Board, Ta = 25°C On Board, Ta > 25°C Package Power Dissipation Linear Derating Factor Junction-Case Thermal Resistance Junction Temperature Operation Temperature Kq Rth(j-c) Tj Topr Tstg V V Storage Temperature RECOMMENDED OPERATING CONDITIONS Symbol Parameter Test Conditions VB VS High Side Floating Supply Voltage High Side Floating Supply Offset Voltage VCC VIN Low Side Fixed Supply Voltage Logic Input Voltage Min. VS+13.5 –5 Limits Typ. — — Max. VS+20 500 13.5 0 — — 20 VCC Unit V V V V THERMAL DERATING FACTOR CHARACTERISTICS (ABSOLUTE MAXIMUM RATINGS) 1.0 Power Dissipation Pt (W) On Board 0.8 0.6 8 Lead DIP 0.4 8 Lead SOP 0.2 0 0 25 50 75 100 125 Ambient Temperature Ta (°C) Sep. 2000 MITSUBISHI SEMICONDUCTORS <HVIC> M63994P/FP HIGH VOLTAGE HALF BRIDGE DRIVER ELECTRICAL CHARACTERISTICS (Ta=25°C, VCC=VBS(=VB–VS)=15V, unless otherwise specified) Symbol Parameter Test conditions Min. Limits Typ. Max. — — — 500 1.0 750 µA µA Unit IFS IBS Floating Supply Leakage Current VBS standby Current ICC VCC standby Current — 500 750 µA VINH High Level Input Threshold Voltage — 11 — V VINL VINHYS Low Level Input Threshold Voltage Input Hysteresis Voltage — — 6 5.0 — — V V IINH High Level Input Bias Current VIN=15V — 75 200 µA IINL Low Level Input Bias Current VIN=0V — — 1.0 µA VBSUVR VBSUVT VBS Supply UV Reset Voltage VBS Supply UV Trip Voltage 7.5 7.0 8.5 8.0 9.5 9.0 V V tVBSUV VBS Supply Filter Time — 7.5 — µs VCCUVR VCC Supply UV Reset Voltage 7.5 8.5 9.5 V VCCUVT tVCCUV VCC Supply UV Trip Voltage VCC Supply Filter Time 7.0 — 8.0 7.5 9.0 — V µs VOH High Level Output Voltage IO=0A 13.8 14.4 — V VOL Low Level Output voltage IO=0A — — 0.1 V IOH IOL Output High Level Short Circuit Pulsed Current Output Low Level Short Circuit Pulsed Current VO=0V, PW<10µs VO=15V, PW<10µs — — –0.5 0.5 — — A A ROH Output High Level On Resistance IO=200mA, ROH=(VOH-VO)/IO — 40 — Ω ROL Output Low Level On Resistance IO=200mA, ROL=VO/IO — 20 — Ω tDEAD Deadtime LO Turn-off to HO Turn-on & HO Turn-off to LO Turn-on CL=1000pF between LO(HO) – GND(VS) 0.50 0.75 1.00 µs tdLH Output Turn-On Propagation Delay CL=1000pF between LO(HO) – GND(VS) 0.7 1.0 1.3 µs tdHL Output Turn-Off Propagation Delay CL=1000pF between LO(HO) – GND(VS) 0.2 0.3 0.4 µs tr tf Output Turn-On Rise Time Output Turn-On Fall Time CL=1000pF between LO(HO) – GND(VS) CL=1000pF between LO(HO) – GND(VS) — — 75 75 180 180 ns ns VB=VS=600V INPUT/OUTPUT TIMING DIAGRAM IN 50% 50% tf tr tf 90% 10% HO 90% 10% tdHL(LO) tdLH(HO) tr 10% 90% LO 90% tDEAD(HO) tdHL(HO) tdLH(LO) 10% tDEAD(LO) Sep. 2000 MITSUBISHI SEMICONDUCTORS <HVIC> M63994P/FP HIGH VOLTAGE HALF BRIDGE DRIVER PERFORMANCE CURVES ICC-VCC, IBS-VBS VINH, VINL-VCC 0.9 18 0.8 16 VINH ICC 14 VINH, VINL (V) ICC, IBS (mA) 0.7 0.6 0.5 IBS 0.4 12 10 8 0.3 6 0.2 4 0.1 8 12 16 20 2 24 VINL 8 12 VCC, VBS (V) 16 20 24 20 24 VCC (V) tdHL, tdLH-VCC tdead-VCC 1.1 1.4 1.0 1.2 0.9 1.0 tdead (µS) tdHL, tdLH (µS) tdLH 0.8 0.6 0.7 0.6 0.4 0.5 tdHL 0.2 0.8 8 12 16 20 0.4 24 8 12 16 VCC (V) VCC (V) VOH-VCC VOL-VCC 4.0 25 3.5 ILO=0mA 3.0 15 VOL (V) VOH (V) 20 10 ILO=–20mA 5 0 ILO=–200mA 8 12 16 VCC (V) 20 24 ILO=200mA 2.5 2.0 1.5 1.0 ILO=20mA 0.5 ILO=0mA 0 8 12 16 20 24 VCC (V) Sep. 2000 MITSUBISHI SEMICONDUCTORS <HVIC> M63994P/FP HIGH VOLTAGE HALF BRIDGE DRIVER IFS-Ta ICC, IBS-Ta 0.8 50 0.7 40 ICC, IBS (mA) IFS (µA) 0.6 30 20 ICC 0.5 0.4 IBS 0.3 10 0.2 0 –50 –25 0 25 50 75 0.1 –50 –25 100 125 0 Ta (°C) 50 75 100 125 Ta (°C) VCCUVT, VCCUVR-Ta VINH, VINL-Ta 12 9.5 11 VCCUVR 9.0 VINH VINH, VINL (V) VCCUVT, VCCUVR (V) 25 8.5 8.0 VCCUVT 10 9 8 7 7.5 VINL 6 7.0 –50 –25 0 25 50 75 5 –50 –25 100 125 0 Ta (°C) 50 75 100 125 75 100 125 Ta (°C) tdHL, tdLH-Ta tdead-Ta 1.6 2.0 1.4 1.6 tdLH 1.2 tdead (µS) tdHL, tdLH (µS) 25 1.2 0.8 1.0 0.8 0.4 0.6 tdHL 0 –50 –25 0 25 50 Ta (°C) 75 100 125 0.4 –50 –25 0 25 50 Ta (°C) Sep. 2000 MITSUBISHI SEMICONDUCTORS <HVIC> M63994P/FP HIGH VOLTAGE HALF BRIDGE DRIVER VOH-Ta VOL-Ta 16 6 ILO=0mA 5 ILO=–20mA 12 VOL (V) VOH (V) 4 8 ILO=–200mA ILO=200mA 3 2 4 ILO=20mA 1 ILO=0mA 0 –50 –25 0 25 50 Ta (°C) 75 100 125 0 –50 –25 0 25 50 75 100 125 Ta (°C) Sep. 2000 MITSUBISHI SEMICONDUCTORS <HVIC> M63994P/FP HIGH VOLTAGE HALF BRIDGE DRIVER LOGIC SEQUENCE VCCUVTRIP VCCUVRESET VCC delay (tUV) delay (tUV) VBS VBSUVTRIP VBSUVRESET delay (tUV) IN HO LO 1. INPUT/OUTPUT LOGIC : HO has positive logic with reference to IN. LO has negative logic with reference to IN. 2. LOGIC DURING UV(VCC, VBS)ERROR Error Signal HO LO UV error (VCC) LO is locked at “L” level as long as UV error for VCC is HO outputs “L” level as long as UV error for VCC is detected. detected. After VCC exceeds VCCUVRESET level, the lock for LO is HO responds to IN if VCC exceeds VCCUVRESET level. removed following an “H” state of the IN signal, and then LO responds to the input. UV error (VBS) HO is locked at “L” level as long as UV error for VBS is detected. After VBS exceeds VBSUVRESET level, the lock for HO is removed following an “L” state of the IN signal, and then HO responds to the input. LO is independent of VBS to respond to IN. Sep. 2000 MITSUBISHI SEMICONDUCTORS <HVIC> M63994P/FP HIGH VOLTAGE HALF BRIDGE DRIVER PACKAGE OUTLINE 8P4 Plastic 8pin 300mil DIP Lead Material Cu Alloy 5 1 4 E 8 c Weight(g) 0.5 JEDEC Code – e1 EIAJ Package Code DIP8-P-300-2.54 D Dimension in Millimeters Min Nom Max 4.5 – – 0.51 – – 3.3 – – 0.4 0.5 0.6 1.4 1.5 1.8 0.9 1.0 1.3 0.22 0.27 0.34 8.9 9.1 8.7 6.15 6.3 6.45 – 2.45 – – 7.62 – – 3.0 – 0° 15° – Symbol A A2 A A1 A2 b b1 b2 c D E e e1 L L A1 SEATING PLANE b1 b2 b e 8P2S-A Plastic 8pin 225mil SOP EIAJ Package Code SOP8-P-225-1.27 JEDEC Code – Weight(g) 0.07 Lead Material Cu Alloy 8 b2 I2 e E Recommended Mount Pad F 4 1 Symbol A D A2 A1 b y L e L1 HE e1 5 c Detail F A A1 A2 b c D E e HE L L1 y b2 e1 I2 Dimension in Millimeters Min Nom Max – – 1.9 0.05 – – – 1.5 – 0.35 0.4 0.5 0.13 0.15 0.2 4.8 5.0 5.2 4.2 4.4 4.6 – 1.27 – 5.9 6.2 6.5 0.2 0.4 0.6 – 0.9 – – – 0.1 0° – 10° – 0.76 – – 5.72 – 1.27 – – Sep. 2000