STMICROELECTRONICS STA002

STA002
®
STARMAN CHANNEL DECODER
FRONT_END INTERFACE:
IF input carrier frequency: f = 1.84 MHz
Single internal 6 bit A/D converter
QPSK demodulation
Input symbol frequency: Fs = 1.84 Msymbols/s
Digital Nyquist root filter:
- roll-off value of 0.4
Digital carrier loop:
- on-chip quadrature demodulator and tracking
loop
- lock detector
- C/N indicator
Digital timing recovery:
- internal timing error evaluation, filter and
correction
Digital AGC:
- internal signal power estimation and filter
- output control signal for AGC (1 bit PWM)
FORWARD ERROR CORRECTION:
Inner decoder:
- Viterbi soft decoder for convolutional codes,
constraint length M=7, Rate 1/2
Deinterleaver block
Outer decoder:
- Reed-Solomon decoder for 32 parity bytes;
correction of up to 16 byte errors
- Block lengths: 255
- Energy dispersal descrambler
BACK_END INTERFACE:
Broadcast Channel selection
Audio Service Component selection to MPEG
decoder
Service Component selection
CONTROL:
I2C serial Bus control interface
January 2002
TQFP44
DECRYPTION:
WES scheme supported
DESCRIPTION
Designed for World Space satellites digital audio
receivers, the STA002 Digital Receiver Front-end
integrates all the blocks needed to demodulate
incoming digital satellite audio signals from the
tuner: analog to digital converter, QPSK demodulator, signal power estimator, automatic gain control, Viterbi decoder, deinterleaver, Reed-Solomon decoder and energy dispersal descrabler. Its
advanced error correction functions guarantees a
low error rate even with small low gain receiver
antennas.
Additional functions include the selection of
broadcast channel, service components and
audio components for source decoding:
- The MPEG Audio bitstream is provided at the
serial audio output port.
- The Broadcast Channel is provided to the serial
data output port.
- The Service Component is provided at the SC
output interface.
World Space encryption scheme is supported for
pay programs and paging.
1/43
STA002
Fig. 1: Channel Decoder Block Diagram
BCCK
BC
DATA
INTERFACE
LOCK
BCSYNC
AGC
RXI
RNXI
BCDIN
TDM_CLK
A/D
QPSK
SCEN
SC
DATA
INTERFACE
TDM FRAME
CONTROLLER
TDM
TSCC
MANAGEMENT
SCDO
SCCK
BC
M_CLK
BCDO
SCK
SOURCE
DECODER
INTERFACE
SC
MANGEMENT
PLL/CLOCK
DISTRIBUTION
SDO
SEN
FRAME
SYNC.
VITERBI
PRC
MANAGEMENT
REED
SOLOMON
BC_CLK
DE-INTERLEAVER
BC/TSCC
MICROPROCESSOR
INTERFACE
RESET
INTR
SCL
SDA
D96AU541C
MINTR
TEST 9
SCDO
GND
SCCK
VDD
SCEN
VDD
BCDO
BCCK
GND
TEST 8
Fig. 2: Pin Connection
44
43
42
41
40
39
38
37
36
35
34
TEST 1
1
33
TEST 7
AGC
2
32
BCDIN
VDD
3
31
BCSYNC
A_VDD
4
30
GND
RXI
5
29
SDO
NRXI
6
28
SCK
A_GND
7
27
SEN
GND
8
26
VDD
M_CLK
9
25
TEST 6
CLK_TEST
10
24
MINTR
TEST 2
11
23
TEST 5
12
13
14
15
16
17
18
19
20
21
22
2/43
VDD
TEST 4
GND
RESET
GND
INTR
SCL
SDA
VDD
LOCK
TEST 3
D97AU671A
STA002
PIN DESCRIPTION
Type
1, 11, 12
22
2
3, 14, 21,
26, 38, 40
4
5
6
7
9
10
13
15
16
8, 17, 19,
30, 35, 42
18
20
24
27
28
29
31
32
36
37
39
41
43
Pin Name
Type
TEST (1:3)
I
23, 25, 33, 34, 44 TEST
(4:9)
AGC
O
VDD
A_VDD
RXI
NRXI
A_GND
M_CLK
CLK_TEST
LOCK
SDA
SCL
GND
INTR
RESET
MINTR
SEN
SCK
SDO
BCSYNC
BCDIN
BCCK
BCDO
SCEN
SCCK
SCDO
I
I
I
O
I/O
I
O
I
O
O
O
O
O
I
O
O
O
O
O
Function
Test Pin
I
AGC Output
Positive Supply Voltage
Analog Positive Supply Voltage
IF Signal Input
IF Signal Input
Analog Ground
Master Clock
Not Connected
Carrrier Lock Indicator
Data + ACK
Serial Clock
Negative Supply Voltage
Interrupt
Master Reset
MPEG Interrupt
MPEG Enable
MPEG Clock
MPEG Bit Output
Broadcast Channel Sync
Broadcast Channel Data Input
Broadcast Channel Clock
Broadcast Channel Data Output
Service Component Enable
Service Component Clock
Service Component Data Output
PAD Description
CMOS Input Pad Buffer with Pull-Down
Test Pin
CMOS 2mA Output Driver
Analog Pad Buffer
Analog Pad Buffer
Analog Pad Buffer with Comparator
CMOS Input Pad Buffer
CMOS 2mA Output Driver
CMOS Schmitt Trigger Bdir Pad Bufer
CMOS Input Pad Schmitt Triggered
CMOS 2mA Output Driver
CMOS Input Pad Buffer with Pull-Up
CMOS 2mA Output Driver
CMOS 2mA Output Driver
CMOS 2mA Output Driver
CMOS 2mA Output Driver
CMOS 2mA Output Driver
CMOS Input Pad Buffer
CMOS 2mA Output Driver
CMOS 2mA Output Driver
CMOS 2mA Output Driver
CMOS 2mA Output Driver
CMOS 2mA Output Driver
Note: pin 1, 11, 12 and 22 must be connected to ground in functional mode.
THERMAL DATA
Symbol
Rth j-amb
Parameter
Thermal resistance Junction to Ambient
Value
85
Unit
°C/W
Value
-0.3 to 4
-0.3 to VDD +0.3
-0.3 to VDD +0.3
-40 to +150
-20 to +85
Unit
V
V
V
°C
°C
ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
Vi
VO
Tstg
Toper
Parameter
Power Supply
Voltage on Input pins
Voltage on output pins
Storage Temperature
Operative ambient temp
3/43
STA002
ELECTRICAL CHARACTERISTICS: VDD = 3.3V ±0.3V; Tamb = 0 to 70°C; Rg = 50Ω unless otherwise
specified
DC OPERATING CONDITIONS
Symbol
VDD
Tj
Parameter
Power Supply Voltage
Operating Junction Temperature
Value
2.7 to 3.6V
-20 to 125°C
GENERAL INTERFACE ELECTRICAL CHARACTERISTICS
Symbol
IIL
Parameter
Low Level Input Current
Without pull-up device
Test Condition
Vi = 0V
Min.
-10
IIH
High Level Input Current
Without pull-up device
Vi = VDD
-10
Electrostatic Protection
Leakage < 1µA
Vesd
Typ.
Max.
10
Unit
µA
Note
1
10
µA
1
V
2
2000
Note 1: The leakage currents are generally very small, < 1nA. The value given here is a maximum that can occur after an electrostatic stress
on the pin.
Note 2: Human Body Model.
DC ELECTRICAL CHARACTERISTICS
Symbol
VIL
VIH
Vol
Voh
Parameter
Low Level Input Voltage
High Level Input Voltage
Low Level Output Voltage
High Level Output Voltage
Test Condition
Min.
Typ.
Max.
0.2*VDD
Unit
V
V
Note
0.4V
V
V
1, 2
1, 2
0.8*VDD
Iol = Xma
0.85*VDD
Note 1: Takes into account 200mV voltage drop in both supply lines.
Note 2: X is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability.
PULL_UP & PULL_DOWN CHARACTERISTICS
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Note
Ipu
Ipu
Rpu
Pull-up current
Vi = 0V
-25
-66
-125
µA
1
Pull-up current
Equivalent Pull-up
Resistance
Vi = VDD
Vi = 0V
25
66
50
125
µA
kΩ
1
Rpu
Equivalent Pull-down
Resistance
Vi = VDD
50
kΩ
Note 1: Min. condition: VDD = 2.7V, 125°C Min process
Max. condition: VDD = 3.6V, -20°C Max.
M_ CLK Electrical Characteristics (Pin number 9)
Symbol
Vil
Vih
Vref
Parameter
Low Level Input Voltage
High Level Input Voltage
Input Reference Voltage
Min.
Typ.
Max.
VDD -1.7
VDD -0.9
Unit
V
V
V
VDD -1.3
POWER DISSIPATION
Symbol
PD
4/43
Parameter
Power Dissipation
@ VDD = 3V
Test Condition
M_CLK = 39,0269MHz
Min.
Typ.
Max.
80
Unit
mW
Note
STA002
Fig. 3: Test Circuit
3
VDD
100nF
8
14
VDD
100nF
17
21
VDD
100nF
19
44
TEST9
34
TEST8
33
TEST7
32
BCDIN
25
TEST6
23
TEST5
22
TEST4
20
RESET
16
SCL
15
SDA
12
TEST3
26
VDD
200
43
100nF
41
SCCK
200
38
VDD
SCDI
200
30
39
100nF
SEN
200
37
35
BCDO
200
36
40
VDD
BCCK
200
100nF
BCSYNC
31
42
200
29
4
AVDD
SDI
200
28
7
SCK
200
27
TEST1
1
RXI
5
NRXI
6
M_CLK
9
TEST_CLK
10
TEST2
11
24
MINTR
200
18
INTR
200
AGC
2
200
13
VDD
4.7µF
SEN
200
LOCK
AVDD
100nF
4.7µF
VSS
100nF
100nF
100nF
VSS
100nF
4.7µF
100nF
4.7µF
AVSS
VSS
100nF
100nF
100nF
100nF
AVSS
D99AU1011
AVSS
Figure 4. Test Load Circuit
Test Load
VDD
Output
SDA
Other Outputs
IOL
OUTPUT
IOL
5mA
100µA
IOH
100µA
CL
100pF
100pF
VREF
3.6V
1.5V
VREF
CL
IOH
D98AU967
5/43
STA002
FUNCTIONAL DESCRIPTION
The STA002 integrates all the functions needed
to demodulate the signal coming from the RF FE;
with reference to the block diagram (Fig 1),
STA002 includes the following functions:
Microprocessor interface
Data transmission from microcontroller to the device takes place through the 2 wires (SDA and
SCL) I2C bus interface. STA002 acts always as a
slave in all its communications.
Interface to the Front-end
This block receives from the RF front-end the
QPSK modulated signal, centered at 1.84 MHz
(2nd IF frequency). This signal is over sampled
using the Master Clock and converted to digital
on 6 bits in 2’s complement format. The same frequency is also used to provide the clock signal for
the QPSK demodulator block.
QPSK
This block is composed by:
- AGC1
- quadrature demodulator
- carrier recovery
- timing recovery
- frequency sweep generator
- AGC2
- lock indicator
- carrier to noise estimator
To assure flexibility and to cover different working
conditions most of the parameters of each function can be programmed through the I2C interface.
TDM Demultiplexer
The TDM frame is divided into 3 fields.
The first is the Master Frame Preamble (MFP)
which contains the synchronisation word. The
second, the Time Slot Control Channel (TSCC),
contains information about the organization of the
Prime Rate Channel data which follows. The
third, is the data field; it contains 96 Prime Rate
Channels of 16 Kbit/s each; up to 8 Prime Rate
Channels are grouped into one Broadcast Channel.
The TDM demultiplexer executes the extraction
and decoding of one Broadcast Channel from the
TDM stream, according to the instructions coming from the microcontroller. The decoding flow is
the following:
- TDM synchronization
The master frame synchronization block receives
6/43
the demodulated symbol stream from the QPSK
demodulator and performs the alignment detecting the Master Frame Preamble.
The known syncronization word is also used to
correct the phase ambiguity intrinsic in QPSK demodulation.
- TSCC extraction
The information of the Prime Rate Channels to
Broadcast Channels allocation are contained in
the TSCC field which is synchronised with the
MFP.
In this stage all the information related to the
TSCC are extracted and made available for the
microcontroller via the I2C interface.
- PRC extraction and BC recovery
This block, after the Broadcast Channel (BC) selection, performs the extraction and synchronisation of the Prime Rate Channels (PRC) belonging
to the selected BC.
The extracted PRCs are aligned and grouped into
one BC data stream.
- FEC decoder
The extracted BC is decoded using a concatenated Forward Error Correction approach.
The FEC circuitry utilizes three error correction
stages: a rate 1/2 Viterbi decoder, a 255x4 bytes
convolutional deinterleaver and a 255/223 Reed
Solomon decoder.
The RS input blocks are 255 bytes long with 32
parity bytes.
Up to 16 errored bytes can be fixed in each RS
block.
BC demultiplexer
Every BC contains up to 8 Service Components;
the Service Control Header (SCH) field contains
all the information related to the organization of
the Service Components. This stage provides the
extraction of the SCH from the BC.
The SCH is available through I2C bus to the microcontroller for the selection of the desired Audio
Service Component, which is then supplied directly to the MPEG Source decoder via the audio
Service Component Interface.
DEVICE OPERATION
1. I2C BUS SPECIFICATION
The STA002 supports the I2C protocol. This protocol defines any device that sends data on to the
bus as a transmitter and any device that reads
the data as a receiver. The device that controls
the data transfer is known as the master and the
others as the slave. The master will always initiate the transfer and will provide the serial clock
STA002
for synchronisation. The STA002 is always a
slave device in all its communications.
1. 1 COMMUNICATION PROTOCOL
1.1.0 Data transition or change
Data changes on the SDA line must only occur
when the SCL clock is low. SDA transitions while
the clock is high are used to identify START or
STOP condition.
1.1.1 Start condition
START is identified by a high to low transition of
the data bus SDA signal while the clock signal
SCL is stable in the high state. A START condition must precede any command for data transfer.
1.1.2 Stop condition
STOP is identified by low to high transition of the
data bus SDA signal while the clock signal SCL is
stable in the high state. A STOP condition terminates communications between STA002 and the
bus master.
1.1.3 Acknowledge bit
An acknowledge bit is used to indicate a successful data transfer. The bus transmitter, either master or slave, will release the SDA bus after sending 8 bits of data.
During the 9th clock pulse the receiver pulls the
SDA bus low to acknowledge the receipt of 8 bits
of data.
Some registers do not give acknowledge when
the data is not available.
(RW; set to 1 in read mode and to 0 in write
mode). After a START condition the STA002
identifies on the bus the device address and if
matching it will acknowledges the identification on
SDA bus during the 9th bit time.
The following 2 bytes after the device identification byte are the internal space address.
1.3 WRITE OPERATION (see fig. 5)
Following a START condition the master sends a
device select code with the RW bit set to 0.
The STA002 gives the acknowledge and waits for
the 2 bytes of internal address. The least significant 10 bits of the 2 bytes address provides access to any of the internal registers. The most
significant bit means incremental mode (1 =
autoincremental, 0 = no) and the other bits are
set to zero.
After the receiption of each of the internal bytes
address the STA002 again responds with an acknowledge.
1.3.1 Byte write
In the byte write mode the master sends one data
byte and this is acknowledged by STA002. The
master then terminates the transfer by generating
a STOP condition.
1.3.2 Multibyte write
The multibyte write mode can start from any internal address. The master sends the data and each
one is acknowledged by the STA002. The transfer is terminated by the master generating a
STOP condition.
1.4 READ OPERATION (see Fig. 6)
1.1.4 Data input
During the data input the STA002 samples the
SDA signal on the rising edge of the clock SCL.
For correct device operation the SDA signal has
to be stable during the rising edge of the clock
and the data can change only when the SCL line
is low.
1.2 DEVICE ADDRESSING
To start communication between the master and
the STA002, the master must initiate with a start
condition. Following this the master sends onto
the SDA line 8 bits (MSB first) corresponding to
the device select address and read or write
mode.
The 7 most significant bits are the device address
identifier, corresponding to the I2C bus definition.
For the STA002 these are fixed as 1101010.
The 8th bit (LSB) is the read or write operation bit
1.4.1 Current byte address read
The STA002 has an internal byte address
counter. Each time a byte is written or read, this
counter, according to the autoincremental bit setting, is incremented or not.
For the current byte address read mode, following a START condition the master sends the device address with the RW bit set to 1. The
STA002 acknowledges this and outputs the byte
addressed by the internal byte address counter.
The counter is then incremented or not depending on the autoincremental bit. The master does
not acknowledge the received byte, but terminates the transfer with a STOP condition.
1.4.2 Random byte address read
A dummy write is performed to load the byte address into the internal address register.
7/43
STA002
Fig. 5: Write Mode Sequence
ACK
ACK
DEV
BYTE
WRITE
ACK
BYTE
START
ACK
BYTE
DATA IN
RW
STOP
ACK
ACK
DEV
MULTIBYT
WRITE
ACK
BYTE
ACK
BYTE
ACK
DATA IN
DATA IN
RW
START
STOP
D97AU669
Fig. 6: Read Mode Sequence
ACK
CURRENT
ADDRESS
READ
DEV
NO ACK
DATA
RW
START
STOP
ACK
RANDOM
ADDRESS
READ
DEV
ACK
BYTE
RW
START
DEV
ACK
NO ACK
DATA
DEV
START
RW= ACK
HIGH
SEQUENTIAL
CURRENT
READ
ACK
BYTE
STOP
RW
ACK
ACK
DATA
NO ACK
DATA
DATA
STOP
START
ACK
ACK
SEQUENTIAL
RANDOM
READ
DEV
START
BYTE
ACK
BYTE
RW
ACK
This is followed by another START condition from
the master and the device address repeated with
the RW bit set to 1. The STA002 acknowledges
this and outputs the byte addressed by the internal byte address counter.
The master does not acknowledge the received
byte, but terminates the transfer with a STOP
condition.
NO ACK
DATA
DATA
DEV
START
ACK
ACK
RW
DATA
STOP
D97AU670
1.4.3 Sequential address read
This mode can be initiated with either a current
address read or a random address read. However in this case the master does acknowledge
the data byte output and the STA002 continues to
output the next byte in sequence.
To terminate the stream of bytes the master does
not acknowledge the last received byte, but terminates the transfer with a STOP condition.
The output data stream is from consecutive byte
addresses, with the internal byte address counter
automatically incremented after each byte output.
1.5 REGISTER MAP (8 BIT REGISTER)
1.5.1 Register address List (by function)
FUNCTION
START ADDRESS
END ADDRESS
HEX_COD
000H
040H
080H
BIN
0000000000
0000111111
0010000000
HEX_COD
03FH
07FH
09FH
BIN
0000111111
0001111111
0010011111
RFU
SCH_MEM
0A0H
100H
0010100000
0100000000
0FFH
1EBH
0011111111
0111101011
RFU
TDM_MULTIPLEX
RFU
TSCC_MEM
1ECH
200H
240H
300H
0111101100
1000000000
1001000000
1100000000
1FFH
23FH
2FFH
3C1H
0111111111
1000111111
1011111111
1111000001
RFU
3C2H
1111000010
3FFH
1111111111
SCH
RFU
QPSK
8/43
STA002
1.5.2 SCH Registers
HEX_COD
DEC_COD
REGISTER NAME
TYPE
000H
001H
0
1
BRI_REG & NSC_REG (note 1)
EC_REG (note 1)
R
R
002H
003H
2
3
AFCI 1_REG (note 1)
AFCI 2_REG (note 1)
R
R
004H
005H
4
5
SOF_SF_REG (note 1)
ADF1_REG (7:0) (note 1)
R
R
006H
6
ADF1_REG (15:8) (note 1)
R
007H
7
ADF2_REG (7:0) (note 1)
R
008H
8
ADF2_REG (15:8) (note 1)
R
RESET
VALUE
009H
9
ADF2_REG (23:16) (note 1)
R
00AH
00BH
10
11
ADF2_REG (31:24) (note 1)
ADF2_REG (39:32) (note 1)
R
R
00CH
00DH
00EH
12
13
14
ADF2_REG (47:40) (note 1)
ADF2_REG (55:48) (note 1)
ADF2_REG (63:56) (note 1)
R
R
R
00FH
15
SEL_SC_REG
R/W
98H
010H
011H
012H
16
17
18
IW_REG (7:0) (note 2)
IW_REG (15:8) (note 2)
IW_REG (23:16) (note 2)
W
W
W
41H
42H
43H
013H
014H
19
20
IW_REG (31:24) (note 2)
IW_REG(39:32) (note 2)
W
W
44H
45H
015H
016H
017H
21
22
23
IW_REG (47:40) (note 2)
IW_REG (55:48) (note 2)
IW_REG (63:56) (note 2)
W
W
W
46H
47H
48H
018H
019H
01AH
24
25
26
EM_REG
PIWE_REG (7:0) (note 2)
PIWE_REG (15:8) (note 2)
R/W
R/W
R/W
00H
00H
00H
01BH
01CH
01DH
01EH
01FH
020H
27
28
29
30
31
32
BCIN_DELAY_REG
BC_ALARM_REG
TEST_PURPOSE
RFU
RFU
TEST PURPOSE
R/W
R/W
R/W
00H
20H
021H
022H
023H
024H
025H
026H
33
34
35
36
37
38
TEST PURPOSE
TEST PURPOSE
TEST PURPOSE
TEST PURPOSE
TEST PURPOSE
TEST PURPOSE
R/W
R/W
R/W
R/W
R/W
R/W
027H
028H
029H
39
40
41
TEST PURPOSE
TEST PURPOSE
TEST PURPOSE
R/W
R/W
R/W
R/W
Note 1: no acknowledge when data is not available
Note 2: when updated all bytes must be written
9/43
STA002
1.5.2 SCH Registers
REGISTER NAME
DEC_COD
02AH
02BH
42
43
TEST PURPOSE
TEST PURPOSE
R/W
R/W
02CH
44
TEST PURPOSE
R/W
02DH
45
TEST PURPOSE
R/W
02EH
02FH
46
47
TEST PURPOSE
TEST PURPOSE
R/W
R/W
030H
48
TEST PURPOSE
R/W
031H
49
TEST PURPOSE
R/W
032H
50
TEST PURPOSE
R/W
033H
51
TEST PURPOSE
R/W
034H
035H
52
53
TEST PURPOSE
TEST PURPOSE
R/W
R/W
036H
037H
038H
54
55
56
TEST PURPOSE
TEST PURPOSE
PIW_RAM (7:0) (note1)
R/W
R/W
W
00H
039H
57
PIW_RAM (15:8) (note1)
W
00H
03AH
03BH
03CH
58
59
60
PIW_RAM (23:16) (note1)
PIW_RAM (31:24) (note1)
PIW_RAM (39:32) (note1)
W
W
W
00H
00H
00H
03DH
03EH
61
62
PIW_RAM (47:40) (note1)
PIW_RAM (55:48) (note1)
W
W
00H
00H
03FH
63
PIW_RAM (63:56) (note1)
W
00H
Note 1: when updated all bytes must be written
10/43
TYPE
RESET
VALUE
HEX_COD
STA002
1.5.3 QPSK Registers
TYPE
RESET
VALUE
QPSK_CONTROL1
R/W
10H
QPSK_CONTROL2
R/W
90H
130
131
AGC1 _REF1 (note 1)
AGC1 _REF2 (note 1)
R/W
R/W
06H
01H
084H
085H
132
133
AGC1_BETA
AGC1_INTG
R/W
R/W
00H
7FH
086H
087H
134
135
AGC2 _REF
AGC2 _BETA
R/W
R/W
16H
00H
088H
136
AGC2_INTG
R/W
23H
089H
137
CN_CNT
R/W
FFH
08AH
08BH
138
139
SYMFREQ1 (note 1)
SYMFREQ2 (note 1)
R/W
R/W
D3H
11H
08CH
140
SYMFREQ3 (note 1)
R/W
0CH
08DH
08EH
08FH
141
142
143
TIMFLTPAR
TIMINTG
CARFLTPAR
R/W
R/W
R/W
48H
00H
57H
090H
091H
092H
144
145
146
IFFREQ1 (note 1)
IFFREQ2 (note 1)
IFFREQ3 (note 1)
R/W
R/W
R/W
37H
1DH
C1H
093H
147
IFFREQ4 (note 1)
R/W
00H
094H
095H
096H
148
149
150
CARINTG
RAMPCTRL
CARFREQ1
R/W
R/W
R
00H
01H
097H
098H
151
152
CARFREQ2
CARFREQ3
R
R
099H
09AH
153
154
FLAG
RFU
R
09BH
09CH
09DH
09EH
155
156
157
158
RFU
RFU
RFU
RFU
09FH
159
RFU
HEX_COD
DEC_COD
080H
128
081H
129
082H
083H
REGISTER NAME
Note 1: when updated all bytes must be written
11/43
STA002
1.5.4 SCH_MEM Registers
HEX_COD
DEC_COD
REGISTER NAME
100H
101H
102H
103H
104H
105H
106H
107H
108H
109H
10AH
10BH
10CH
10DH
10EH
10FH
110H
111H
112H
113H
114H
115H
116H
117H
118H
119H
11AH
11BH
11CH
11DH
11EH
11FH
120H
121H
122H
123H
124H
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
SC1_LENGHT & SC1_TYPE
SC1_EC & SC1_PT
SC1_PT
LANGUAGE 1
SC2_LENGHT & SC2_TYPE
SC2_EC & SC2_PT
SC2_PT
LANGUAGE 2
SC3_LENGHT & SC3_TYPE
SC3_EC & SC3_PT
SC3_PT
LANGUAGE 3
SC4_LENGHT & SC4_TYPE
SC4_EC & SC4_PT
SC4_PT
LANGUAGE 4
SC5_LENGHT & SC5_TYPE
SC5_EC & SC5_PT
SC5_PT
LANGUAGE 5
SC6_LENGHT & SC6_TYPE
SC6_EC & SC6_PT
SC6_PT
LANGUAGE 6
SC7_LENGHT & SC7_TYPE
SC7_EC & SC7_PT
SC7_PT
LANGUAGE 7
SC8_LENGHT & SC8_TYPE
SC8_EC & SC8_PT
SC8_PT
LANGUAGE8
DYNAMIC LABEL
DYNAMIC LABEL
DYNAMIC LABEL
DYNAMIC LABEL
DYNAMIC LABEL
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
1E7H
1E8H
1E9H
1EAH
1EBH
487
488
489
490
491
DYNAMIC LABEL
DYNAMIC LABEL
DYNAMIC LABEL
DYNAMIC LABEL
DYNAMIC LABEL
R
R
R
R
R
Note: no acknowledge when data is not available for all the SCH_MEM registers
12/43
TYPE
RESET
VALUE
STA002
1.5.5 TDM_MULTIPLEX Registers
HEX_COD
DEC_COD
200H
201H
202H
203H
204H
205H
206H
207H
208H
209H
20AH
20BH
20CH
20DH
20EH
20FH
210H
211H
212H
213H
214H
215H
216H
217H
218H
219H
21AH
21BH
21CH
21DH
21EH
21FH
220H
221H
222H
223H
224H
225H
226H
227H
228H
229H
22AH
22BH
22CH
22DH
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
548
550
551
552
553
554
555
556
557
REGISTER NAME
TDM_TRSH 1
TDM_TRSH 2
PRC_TRSH 1
PRC_TRSH 2
VITERBI_ERROR_CONTROL
SP_TRSH 2
PRC_MAXDELAY
TDM_ALARM
PRC_ALARM
BC_SEL 1 (note)
BC_SEL2 (note)
CONTROL
INT_MASK
ERROR_ REG
STATUS REG
PRC_ACTIVE_REG
PRC_ LOCK_REG
PRC_DELAY_REG
RS_ERROR_CONTROL
VIT_ERROR1
VIT_ERROR2
RS_BYTE_ERROR1
RS_BYTE_ERROR2
RS_BLOCK_ERROR
TEST_PURPOSE
TEST_PURPOSE
TEST_PURPOSE
TEST_PURPOSE
TEST_PURPOSE
TEST_PURPOSE
PLL_INT_REG
TEST_PURPOSE
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET
VALUE
4BH
43H
2AH
23H
00H
13H
06H
00H
00H
01H
00H
00H
00H
00H
00H
00H
07H
1CH
4AH
03H
18H
25H
2EH
3EH
18H
0DH
18H
12H
0AH
0CH
Note: when updated all bytes must be written
13/43
STA002
1.5.5 TDM_MULTIPLEX Registers (continued)
HEX_COD
DEC_COD
22EH
22FH
230H
231H
232H
233H
234H
235H
236H
237H
23CH
23DH
237EH
558
559
560
561
562
563
564
565
566
567
568
569
570
REGISTER NAME
TYPE
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
TEST_PURPOSE
TEST_PURPOSE
TEST_PURPOSE
R
R
R
R
R
R
R
R
R
R
R
R
R
RESET
VALUE
0EH
12H
32H
0CH
1CH
2FH
0AH
0BH
2AH
09H
09H
09H
09H
1.5.6 TSCC_MEM Registers
HEX_COD
DEC_COD
REGISTER NAME
300H
301H
302H
303H
304H
305H
306H
307H
768
769
770
771
772
773
774
775
TSCW 1 (7:0)
TSCW 1 (15:8)
TSCW 2 (7:0)
TSCW 2 (15:8)
TSCW 3 (7:0)
TSCW 3 (15:8)
TSCW 4 (7:0)
TSCW 4 (15:8)
R
R
R
R
R
R
R
R
3BCH
3BDH
3BEH
3BFH
3C0H
3C1H
956
957
958
959
960
961
TSCW 95 (7:0)
TSCW 95 (15:8)
TSCW 96 (7:0)
TSCW 96 (15:8)
TSCW ID (7:0)
TSCW ID (15:8)
R
R
R
R
R
R
2. IF INTERFACE
The Master Clock (M_CLK) is the source of all
the STA002 internal timings.
M_CLK is internally divided to drive the A/D converter and to provide the clock signal for the
QPSK block.
The IF input signal, centered at 1.84MHz, is oversampled at a frequency Fck of M_CLK/4 or
M_CLK/2 according to STA002 presettings.
TYPE
RESET
VALUE
the VCO.
The PLL output frequency Fck can be selected via
I2C interface according to the PLL_INT_REG.
Reg. name: PLL_INT_REG
Internal address: 21E H
Reset Value : 00H
Type: R/W
MSB
2.1 PLL
This fully integrated PLL includes the phase/frequency detector, the charge pump, the filter and
14/43
X
LSB
X
b5
b4
b3
b2
b1
b0
Description: PLL and INTR pin control register
STA002
b1
0
0
1
1
b0
0
1
0
1
PLL output clock (ADC input)
M_CLK (pin 9)
2XM_CLK (pin9)
Test purpose
Test purpose
b5
0
0
1
1
b4
0
1
0
1
INTR pin control
Normal function (from ERROR_REG)
BC_LOCK signal on INTR pin
MFP_LOCK signal on INTR pin
PRCP_ALL_LOCK on INTR pin
b3, b2: Test purpose
2.2 A/D CONVERTER
This block performs the analog to digital conversion of the incoming IF input signal.
The ADC has a resolution of 6 bit and is based
on the so called Half Flash architecture to reduce
both area and power consumption.
The sampling rate depends on the M_CLK (Master Clock) frequency and on the PLL presetting.
3. QPSK DEMODULATOR
3.1 QUADRATURE DEMODULATOR
The final base-band demodulation is performed in
this block.
The samples of the IF input signal are multiplied
by the sine and cosine functions to get the two inphase (I) and quadrature (Q) components of the
QPSK signal. The phase ambiguity inherent in
QPSK is solved in the frame synchronisation part.
A programmable bit allows to multiply by -1 the
quadrature component in order to accomodate
QPSK modulation with another convention of rotation sense (this is equivalent to a permutation of
I and Q components).
The sine and cosine functions are generated by
an NCO using a phase accumulator and a lookup table.
3.3. TIMING RECOVERY
The timing loop is completely implemented digitally and comprises the timing detector working at
symbol rate, a loop filter, the timing NCO and the
Nyquist/interpolator filters.
The loop is controlled by two parameters, alpha_tmg and beta_tmg contained in the
TIMFLTPAR register.
3.3.1 Timing loop registers
Timing
loop
filter
parameter
(TIMFLTPAR)
Internal address: 8D H
Reset Value: 48H
MSB
b7
LSB
b6
b5
b4
b3
alpha_tmg
b2
b1
b0
beta_tmg
Timing frequency registers (TIMINTG)
Internal address: 8E H
Reset Value: 0AH
MSB
b7
LSB
b6
b5
b4
b3
b2
b1
b0
signed number
The value of this register, when the system is
locked, is an image of the frequency offset.
Timing NCO frequency setting (SYMFREQ)
Internal address: 8C H 8B H 8A H
Reset Value : 0CH 11H D3H
MSB
b23
3.2. INTERPOLATOR NYQUIST FILTER
The I and Q components are filtered by a digital
Nyquist root filter with the following features:
Separate I and Q stream, Fck/Fsym samples per
symbols;
Raised root cosine shape with roll-off factor of
40%;
Separate I and Q output stream, 1 sample per
symbol.
This filter performs both the Nyquist filter function
(matched with the one in the transmission side)
and the interpolation function to compute the optimum output sample.
register
LSB
b22
b21
b20
b19
b18
b17
b16
SYMFREQ3
MSB
b15
LSB
b14
b13
b12
b11
b10
b9
b8
SYMFREQ2
MSB
b7
LSB
b6
b5
b4
b3
b2
b1
b0
SYMFREQ1
This register is divided into three bytes. The LSB
byte is named SYMFREQ1, the MSB is named
SYMFREQ3.
15/43
STA002
The 22 bits value to be written into this register is
given by:
Phase Detector Gain
 Fsym 22
2 
SYMFREQ = INT 
 Fck

D97AU724
(Kd)
for example if
0.3
M_CLK = 39,02687179MHz, Fck = M_CLK/4
0.2
SYMFREQ = 790995 = (C11D3)HEX
which is the Reset Value.
0.1
3.3.2 Loop equations
This timing loop is a second order one. The natural frequency and the damping factor may be calculated by the following formulas:
fn =
2π
Ko =
2π
222
Fck
The damping factor is:
α
2
K K ⋅m
o D

√
β
where α is programmed by the timing register alpha_tmg:
α = 2alpha_tmg
beta_tmg can only take value from 0 to 15; if
beta_tmg is 0 the loop reduces to a first order
one.
Alpha_tmg can take any value from 0 to 7. If both
alpha_tmg and beta_tmg are 0 then the timing
loop is open.
The timing phase detector gain KD depends on
the signal to noise ratio and is given in the following figure:
(see par. 3.8 for the C/N definition)
KD = 0.356 for a noise free input signal.
The natural frequency and the damping factor
can be rewritten as:
16/43
0
5
10
C/N(dB)
Ko KD β ⋅ m

√
where β is programmed by the timing register
beta_tmg:
b = 2beta_tmg-14 ⋅ Fsym (Fsym = 1.84MHz)
where m is the reference value of the AGC2 loop
(see AGC2_REF register), KD is the timing detector gain and Ko is the constant of the timing NCO:
ξ=
0
fn = 2.064 √


m ⋅ KD ⋅ 2beta_tmg
FCK √
FCK
ξ = 0.0577 √

⋅ D
alpha_tmg

√
beta_tmg ⋅ 2
2
m K
Table 1 gives the natural frequency and the
damping factor for the nominal amplitude m = 22,
KD = 0.356 and M_CLK = 39.02687179MHz.
In high noise conditions the value of KD may be
reduced up to 25% of its nominal (noise free)
value; it is recommended to start with a damping
factor, calculated without noise, greater than the
usual value of 0.7.
3.4. CARRIER RECOVERY
Also the carrier recovery is completely implemented digitally and comprises a phase and frequency detector, a loop filter, a NCO and a
sine/cosine look-up table.
The carrier NCO is the local oscillator for the input quadrature demodulator.
3.4.1 Carrier loop registers
Carrier
loop
filter
parameter
(CARFLTPAR)
Internal address: 8F H
Reset Value: 57H
register
MSB
b7
LSB
b6
b5
alpha_car
b4
b3
b2
b1
beta_car
b0
STA002
TABLE 1. Timing loop parameters (m= 22; KD = 0.356; M_CLK = 39.02687179MHz)
beta_tmg
fn(Hz)
0
NA
1
25
2
36
3
51
NA
NA
NA
NA
NA
NA
NA
NA
NA
0.71
1.42
2.85
5.70
11.4
22.8
45.6
NA
0.50
1.01
2.01
4.03
8.06
16.1
32.2
NA
0.36
0.71
1.42
2.85
5.70
11.4
22.8
alpha_tmg
0
1
2
3
4
5
6
7
MSB
LSB
b6
b5
b4
b3
b2
5
102
6
144
7
204
8
288
9
408
10
577
Damping factor
NA
NA
NA
0.13
0.18
0.25
0.25
0.36
0.50
0.50
0.71
1.01
1.01
1.42
2.01
2.01
2.85
4.03
4.03
5.70
8.06
8.06
11.4
16.1
NA
0.09
0.18
0.36
0.71
1.42
2.85
5.70
NA
0.06
0.13
0.25
0.50
1.01
2.01
4.02
NA
0.04
0.09
0.18
0.36
0.71
1.42
2.85
NA
0.03
0.06
0.13
0.25
0.50
1.01
2.01
The 26 bits value to be written into this register is
given by:
 IF 26
IFFREQ = INT 
2 
 Fck

Carrier frequency registers (CARINTG)
Internal address: 94 H
Reset Value: 00H
b7
4
72
b1
b0
For example if M_CLK = 39.02687179MHz,
Fck = M_CLK/4
signed number
IFFREQ = 12655927 = (C11D37)HEX
This register is formed by the 8 integrator MSBs
of the carrier loop filter.
The value of this register, when the system is
locked, is an image of the frequency offset.
It may be read or written at any time by the micro.
When written the integrator LSBs are reset.
which is the Reset Value.
Actual Carrier Frequency Register (CARFREQ)
Internal address: 96 H, 97 H, 98 H
MSB
Carrier NCO frequency setting register (IFFREQ)
Internal address: 93 H 92 H 91 H 90 H
Reset Value : 00H C1H 1DH 37H
MSB
b31
LSB
b30
b29
b28
b27
b26
b25
b24
MSB
LSB
b22
b21
b20
b19
b18
b17
b16
MSB
LSB
b14
b13
b12
b11
b10
b9
b8
IFFREQ2
MSB
b7
LSB
b6
b21
b20
b19
b18
b17
b16
CAR FREQ 3
MSB
b15
LSB
b14
b13
b12
b11
b10
b9
b8
MSB
b7
LSB
b6
b5
b4
b3
b2
b1
b0
CAR FREQ 1
IFFREQ3
b15
b22
CAR FREQ 2
IFFREQ4
b23
b23
LSB
b5
b4
b3
b2
b1
b0
IFFREQ1
This register is divided into four bytes.
The LSB byte is named IFFREQ1, the MSB is
named IFFREQ4.
This register contains the actual carrier frequency
value when the system is locked.
It is divided into 3 registers: CARFREQ3, down to
1 (CARFREQ3 is the MSB).
This register may be read at any time and it is
useful to store the value of the recovered carrier.
If the system unlocks (due, to a lack of signal
etc.) the carrier NCO could be initialized with this
value to speed-up the tracking process.
3.4.2 Loop parameters
Like the timing loop the carrier loop is a second
17/43
STA002
TABLE 2. Carrier loop parameters (m = 22; KD = 1.26; M_CLK = 39.02687179MHz)
beta_car
0
NA
fn(KHz)
alpha_car
1
0.38
2
0.54
3
0.77
4
1.09
5
1.54
6
2.17
7
3.07
8
4.35
9
6.15
10
8.69
NA
0.08
0.17
0.34
0.67
1.34
NA
0.06
0.12
0.24
0.47
0.95
NA
0.04
0.08
0.17
0.34
0.67
NA
0.03
0.06
0.12
0.24
0.47
Damping factor
NA
NA
NA
NA
NA
NA
0
1
2
3
4
5
NA
0.67
1.34
2.69
5.37
10.7
NA
0.47
0.95
1.90
3.80
7.60
NA
0.34
0.67
1.34
2.69
5.37
order system controlled by two parameters, alpha-car and beta-car, contained in the
CARFLTPAR register.
The natural frequency and the damping factor are
given in the following formulas:
fn =
m Ko K
Dβ

√
2π
where β is programmed by the carrier register
beta_car:
beta_car-4
β=2
NA
0.24
0.47
0.95
1.90
3.80
NA
0.17
0.34
0.67
1.34
2.69
NA
0.12
0.24
0.47
0.95
1.90
Phase Detector Gain
D97AU725
(Kd)
1.2
1
0.8
⋅Fsym (Fsym = 1.84MHz)
0.6
m is the reference value of the AGC2 loop (see
AGC2_REF register), KD is the phase detector
gain and Ko is the constant of the carrier NCO:
Ko =
2π
226
α
2
5
10
alpha_car
ξ = 0.0289 √

FCK 2
mKo KD
√

β
where α is programmed by the carrier register alpha_car:
α = 2alpha_car+6
beta_car can only take value from 0 to 15; if
beta_car is 0 the loop becames a first order one.
alpha_car can take any value from 0 to 9. If both
alpha_car and beta_car are 0 then the loop is
open.
KD depends on the signal to noise ratio and is
given in the figure in next column.
(see par. 3.8 for C/N definition)
KD = 1.26 for a noise free input signal.
The natural frequency and the damping factor
can be rewritten as:
fn = 16.515 √


m ⋅ KD ⋅ 2 beta_car
FCK √
18/43
0
C/N(dB)
FCK
The damping factor is
ξ=
0
m⋅K
D

√
beta_car
2
Table 2 gives the natural frequency and the
damping factor for the nominal amplitude m = 22,
KD = 1.26 and M_CLK = 39.02687179MHz.
In presence of noise the value of KD may be reduced of up to 60%; it is recommended to start
with a damping factor, without noise, greater than
the usual value of 0.7.
3.4.3 Phase and frequency detector parameter
The carrier phase error is calculated by the following formula : ε = I sgn(Q) - Q sgn(I).
This value is computed (at symbol rate) if the actual I and Q components are greater than a programmed threshold otherwise the previous value
is mantained. In this way the detector outputs a
DC value proportional to the frequency offset between the incoming signal and the local oscillator.
The threshold value may be programmed by the
PFDTHR parameter inside the QPSK_CONTROL2 register:
STA002
QPSK_CONTROL2 Register
Internal address: 81 H
Reset Value: 90H
MSB
b7
LSB
b6
b5
b4
PFDTHR
b3
b2
b1
CNTHR
b0
SN
The threshold value depends on the signal level
at the Nyquist filter output. A good value for this
parameter is given by: PFDTHR = 0.4 AGC2REF
where AGC2REF is the reference value for the
AGC2 loop.
3.4.4 Internal ramp parameter
In presence of a frequency offset greater than the
pull-in range of the carrier loop or in presence of
low signal to noise ratio the tracking performance
of the loop itself may became rather slow. To
help the loop in tracking this frequency offset an
internal ramp can be activated by I2C bus.
This ramp can be switched on or off by setting
the SWON parameter 1 or 0 respectively. When
SWON=0 the output value of the ramp is null.
The sweep rate can be calculated by the following formula:
F2ck
2swstep
dF
=
dt stepper + 1 226
LSB
b5
b4
b3
b2
MSB
X
LSB
X
X
X
X
X
b9
b1
b0
b5 : SWON; 1 = 2 ramp on; 0 = 2 ramp off
b4 : SWSTEP
b3 - b0 : STEPPER
Ramp control register (RAMPCTRL)
Internal address: 95 H
Reset Value: 01H
LSB
b6
b5
b4
b3
b2
b1
b0
AGC1_REF1
This register is divided into two bytes. The LSB
byte is named AGC1_REF1, the MSB is named
AGC1_REF2.
The reset value of this register (262) maintains
the peak signal input level equal to the half range
of the ADC.
AGC1 integrator gain register (AGC1_BETA)
Internal address: 84 H
Reset Value: 00H
MSB
X
3.5. AGC1
3.5.1 AGC1 control
To avoid a degradation of the signal to noise ratio
a constant IF level is necessary at the channel
decoder input.
The AGC1 outputs a signal to control the Variable
Gain Amplifier in the RF Front-End in order to
mantain a fixed level at the ADC input.
The input signal power (computed after the A/D
conversion) is compared to a programmable
b8
AGC1_REF2
b7
MSB
X
3.5.2 Registers
AGC1 reference level register (AGC1_REF)
Internal address: 83 H 82H
Reset Value : 01H 06H
MSB
where swstep can only take 0 and 1 values and
stepper can be programmed in a range from 0 to 15.
X
threshold; the difference is scaled by the
AGC1BETA coefficient then integrated.
The result is converted into a pulse width modulation signal to drive the AGC output pin; it may be
filtered by a simple RC filter to control the gain
command of a variable gain amplifier before the
A to D conversion.
The 8 integrator MSB’s (AGC1_ INTG register)
may be read or written at any time by the micro;
when written, the LSB’s are reset.
The integrator value is the level of the AGC output, after low pass filtering; it gives an image of
the input signal power. The sign of the loop can
be controlled by the AGC1CHS control bit in the
QPSK_CONTROL1 register in order to adapt the
loop to a positive or negative slope of the variable
gain amplifier.
LSB
X
X
X
X
b2
b1
b0
AGC1_BETA
The AGC1 loop gain βAGC1 is given by:
bAGC1 = 2AGC1_BETA
The parameter AGC1_BETA can only take values
from 0 to 5. When AGC1_BETA is set to "111"
the loop gain is null. This condition is useful to
open the AGC1 loop.
19/43
STA002
AGC1 integrator value register (AGC1_INTG)
Internal address: 85 H
Reset Value: 00H
MSB
b7
b6
b5
b4
b3
b2
AGC2 integrator value register (AGC2_INTG)
Internal address: 88 H
Reset Value: 00H
LSB
MSB
b0
b7
b1
signed number
LSB
b6
b5
b4
b3
b2
signed number
b1
b0
To open the AGC1 loop this register must be reset and the AGC1_BETA parameter must be
"111".
To open the AGC2 loop this register must be reset and the AGC2_BETA parameter must be
"111".
3.6. AGC2
3.6.1 AGC2 control
The AGC2 loop is used at the output of the
Nyquist / interpolator filter for power optimization
in the signal bandwith.
The modulus of the complex signal at the output
of the Nyquist filter is compared to a programmable threshold and then scaled by the
AGC2_BETA coefficient and integrated.
The integrated error drives two multiplier at the
output of both the Nyquist filters in order to mantain constant the level signal at the demodulator
output.
The AGC2 reference level value impacts the
value of the following functions:
- Carrier to Noise indicator;
- The carrier loop;
- The timing loop
3.6.2 Register
AGC2 reference level register (AGC2_REF)
Internal address: 86 H
Reset Value : 16 H
MSB
X
LSB
X
b5
b4
b3
b2
b1
b0
AGC2_REF
The value written in this register corresponds to
the modulud of the output complex signal (I,Q).
3.7. LOCK INDICATOR
This 1 bit carrier lock flag may be read at any
time.
This flag is available at the chip output and can
be also read by the micro in the FLAG register
A low logic level at the Lock Indicator means that
a QPSK signal is found.The lock indicator flag
controls , internally, the ramp block. The sweep
function is disable whenever a lock condition is
detected.
3.8. CARRIER TO NOISE INDICATOR
A register is used to estimate the carrier to noise
level C/N in a range from 4 to 17dB.
Remark: in the WorldStar system the correspondence between C/N, Eb/No (Energy per net-bit to
noise ratio) and Eb/No|QPSK (Energy per channelbit to noise ratio) are the following:
C/N = Eb/No|QPSK + 3dB = Eb/No - 0.6dB
AGC2 integrator gain register (AGC2_BETA)
Internal address: 87 H
Reset Value: 00H
MSB
X
LSB
X
X
X
X
b2
b1
b0
AGC2_BETA
The AGC2 loop gain βAGC2 can be controlled by
this register:
βAGC2 = 2AGC2_BETA
The parameter AGC2_BETA can take values
from 0 to 6. When AGC2_BETA is set to "111"
the loop gain is null and the AGC2 amplifier gain
keeps the last value.
20/43
The C/N indicator may be used to optimize the
antenna pointing or to give an idea of the RF sigal quality. This is based on the measure of the
scattering of the QPSK constellation: a 10 bit
counter is incremented when the scattering is exceeding a certain value. After a programmable
time interval the 8MSB of the counter are loaded
in the corresponding I2C-bus register.
The register value strongly depends on the
AGC2_REF parameter.
3.8.1 C/N Register (CNCNT)
This register contains a value proportional to the
signal to noise ratio at the Nyquist filter output
(Eb/No|QPSK).
STA002
TABLE 3. Correspondence between C/N and the CNCNT register contents.
C/N(dB) Eb/No|QPSK
m = AGC2_ REF
0
3
1
4
2
5
3
6
4
7
5
8
6
9
7
10
8
11
9
12
10
13
11
14
12
15
13
16
14
17
15
18
16
19
17
20
16
161
155
148
140
132
122
113
105
92
84
71
65
58
49
42
34
32
30
CNTHR = 8
22
26
101
121
93
112
84
102
73
91
61
79
50
68
38
55
28
46
20
33
13
26
8
20
6
14
3.2
9
1.6
5
0.9
3.4
0.5
2.4
0.25
1.5
0.07
0.9
16
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
CNTHR = 12
22
177
173
168
161
155
148
141
134
125
118
112
103
93
84
77
70
66
61
26
151
145
138
130
120
110
100
89
79
67
57
51
40
32
27
23
19
13
16
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
CNTHR = 16
22
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
26
193
192
190
186
184
180
177
174
170
165
161
158
154
149
144
141
137
131
The value are the average of 1000 readings of the CNCNT register.
The relation between C/N and the required value
(CNCNT) is given in the table 3 for three AGC2
reference levels. A value of 255 means overflow.
time internal.
A flag bit (CNFLAG) is set to 1 to indicate that a
value is available in the CNCNT register.
3.8.2 Control Register
There are two parameters to control the C/N estimator circuit CNTHR and SN located in the
QPSK _CONTROL 2 register.
The CNTHR parameter (2 bits) sets the threshold
value under which the circuit is activated.
The SN parameter (2bits) sets the measure time
internal.
Both there two parameters are given in the following tables:
3.9 CONTROL REGISTERS
QPSK_CONTROL1 register
Internal address: 80 H
Reset Value: 10H
CNTHR
THRESHOLD
00
01
10
11
8
12
16
NA
SN
00
01
10
11
TIME INTERVAL IN SYMBOLS
1024
4096
16384
65536
A suitable value of the threshold and time interval must be chosen to have a good level of confidence of the C/N estimate.
To increase the measure accuracy is advisable to
average several values.
Before starting the measure the CNCNT register
must be reset and can be read after the selected
MSB
X
LSB
b6
b5
b4
b3
X
X
X
b6 : AGC1CHS
b5 : CAR CHS
b4 :TIMCHS
b3 : QCHP
AGC1CHS changes the polarity of the AGC signal at output pin.
CARCHS and TIMCHS change the sign of the
carrier tracking loop and symbol tracking loop respectively.
QCHS inverts the sign of the Q component.
QPSK_CONTROL2 register
Internal address: 81 H
Reset Value: 90H
MSB
b7
LSB
b6
b5
PFDTHR
b4
b3
b2
CNTHR
b1
b0
SN
21/43
STA002
This register controls the Phase and frequency
detector threshold (see par. 3.4.3) and the C/N
indicator (see 3.8.2)
LOCK CNFLAG
reserved
This is a read only register when the LOCK bit is
0 then the carrier is locked. When the CNFLAG
bit is 1 then the C/N estimation is available.
4. TDM DEMULTIPLEXING
4.1 TDM_MULTIPLEX REGISTERS.
b4
b3
b2
b1
b0
LSB
b6
b5
b4
b3
b2
b1
b0
Description: TDM finite state machine control register (see Table 4).
LSB
b4
b5
Reg name: TDM_ALARM
Internal address: 207 H
Type: R/W
Reset Value: 00H
b7
MSB
b5
LSB
b6
MSB
Reg name: TDM_TRSH1
Internal address: 200 H
Type: R/W
Reset Value: 4BH
b6
X
Description: Master frame preamble recognition Warning flag threshold level.
Definition of the minimum number of TDM preamble bits to be recognized before setting an
alarm condition.
FLAG REGISTER
internal address: 99 H
X
MSB
b3
b2
b1
b0
Description: Master frame preamble recognition Synchronization threshold level.
Definition of the minimum number of TDM preamble bits to be recognized before enabling the
frame synchronization.
Reg name: PRC_TRSH1
Internal address: 202 H
Type: R/W
Reset Value: 2AH
MSB
X
LSB
X
b5
b4
b3
b2
b1
b0
Description: Prime rate channel preamble recognition - Synchronization threshold level.
Definition of the minimum number of PRC preamble bits to be recognized before enabling PRC
synchronization.
Reg name: TDM_TRSH2
Internal address: 201 H
Type: R/W
Reset Value: 43H
Table 4: TDM FSM active states
b7
X
b6
X
b5
X
b4
X
b3
X
b2
0
b1
0
b0
0
TDM FSM active states
mfp_detection, mfp_presync, mfp_sync,alarm 1 (1 cycle)
X
X
X
0
X
X
X
0
X
X
X
0
X
X
X
0
X
X
X
0
0
0
0
1
0
0
0
X
1
0
1
X
mfp_detection, mfp_presync, mfp_sync,alarm 1 (2 cycle)
mfp_detection, mfp_presync, mfp_sync,alarm 1 (3 cycle)
mfp_detection, mfp_presync, mfp_sync,alarm 1 (4 cycle)
mfp_detection, mfp_presync, mfp_sync, alarm 1, alarm 2 (1 cycles)
0
-
0
-
0
-
0
-
1
-
1
1
X
X
X
X
mfp_detection, mfp_presync, mfp_sync, alarm 1, alarm 2 (2 cycles)
mfp_detection, mfp_presync, mfp_sync, alarm 1, alarm 2 (n cycles)
1
1
1
1
1
1
X
X
mfp_detection, mfp_presync, mfp_sync, alarm 1, alarm 2 (32 cycles)
22/43
STA002
Reg name: PRC_TRSH2
Internal address: 203 H
Type: R/W
Reset Value: 23H
MSB
b7
MSB
X
LSB
X
b5
b4
b3
b2
b1
b0
Description: Prime rate channel preamble recognition - Warning flag threshold level.
It defines the minimum number of PRC preamble
bits to be recognized before setting an alarm condition.
LSB
b6
b5
b4
b3
b2
b1
b0
Description: It gives the list of active PRC within
one selected BC.
b0 to b7 indicates PRC0 to PRC7 respectively.
Reg name: PRC_LOCK_REG
Internal address: 210 H
Type: R
MSB
b7
LSB
b6
b5
b4
b3
b2
b1
b0
Description: Lock status of each PRC
Reg name: PRC_ALARM
Internal address: 208 H
Type: R/W
Reset Value: 00H
b0 to b7 indicates the lock status of PRC0 to
PRC7 respectively.
MSB
b7
LSB
b6
b5
b4
X
X
b1
b0
Description: PRC finite state machine control register (see table 5).
Reg name: PRC_DELAY_REG
Internal address: 211 H
Type: R
MSB
X
LSB
X
X
X
b3
b2
b1
b0
Description: PRC maximum number of delay
symbols
It detects the maximum number of delay symbols
among the PRC within the same BC.
Reg name: PRC_ACTIVE_REG
Internal address: 20F H
Type: R
Table 5: PRC_ALARM
b7
X
b6
X
b5
X
b4
X
b1
0
b0
0
PRC FSM active states
prcp_detection, prcp_presync, prcp_sync
X
0
0
0
X
0
0
0
X
0
0
1
X
0
1
0
0
1
1
1
1
0
0
0
prcp_detection, prcp_presync, prcp_sync, alarm 1
sp_detection, sp_presync, sp_sync, alarm2
sp_detection, sp_presync, sp_sync, alarm2 (1 cycle)
sp_detection, sp_presync, sp_sync, alarm2 (2 cycles)
0
1
0
1
1
1
1
1
1
1
1
0
0
0
sp_detection, sp_presync, sp_sync, alarm2 (3 cycles)
sp_detection, sp_presync, sp_sync, alarm2 (n cycles)
sp_detection, sp_presync, sp_sync, alarm2 (16 cycles)
0
0
0
0
0
0
0
0
1
0
1
0
1
1
1
1
1
1
sp_detection, sp_presync, sp_sync, alarm1, alarm2
sp_detection, sp_presync, sp_sync, alarm1, alarm2 (1 cycle)
sp_detection, sp_presync, sp_sync, alarm1, alarm2 (2 cycles)
0
1
0
1
1
1
1
1
1
1
1
1
1
1
sp_detection, sp_presync, sp_sync, alarm1, alarm2 (3 cycles)
sp_detection, sp_presync, sp_sync, alarm1, alarm2 (n cycles)
sp_detection, sp_presync, sp_sync, alarm1, alarm2 (16 cycles)
23/43
STA002
Reg name: PRC_MAXDELAY
Internal address: 206 H
Type: R/W
Reset Value:06H
4.2 INTERRUPT/STATUS REGISTERS
MSB
X
LSB
X
X
X
X
b2
b1
Reg name: CONTROL
Internal address: 20BH
Type: R/W
Reset Value: 00H
b0
MSB
Description: Maximum accepted number of delay symbols among the prime rate channels belonging to the same broadcast channel.
Reg name: SP_TRSH2
Internal address: 205 H
Type: R/W
Reset Value: 13H
MSB
X
LSB
X
X
b4
b3
b2
b1
b0
Description: Service control header preamble recognition - Warning flag threshold level.
Definition of the minimum number of SCH preamble bits to be recognized before enabling SCH
synchronization
b7
LSB
b6
b5
b4
b3
b2
b1
Description: Control register
b0 : Software reset on
b1 : Software reset enable
b2 : Set TDM out of frame
b3 : ERROR_REG reset on read enable
b4 : Set PRC out of frame
b5 : Set BC out of frame
b6, b7: Test purpose
Reg name: INT_MASK
Internal address: 20CH
Type: R/W
Reset Value: 00H
MSB
Reg name: BC_SEL1, BC_SEL2
Internal address: 209 H , 20AH
Type: R/W
Reset Value: 01H, 00H
X
BC_SEL1 (LSB)
MSB
b7
LSB
b6
b5
b4
b3
b2
b1
b0
BC_SEL2 (MSB)
MSB
b15
LSB
b14
b13
b12
b11
b10
b9
b8
Description: Broadcast channel selection
b10 ....b0: BC number selection
b11: Test purpose
b15 ... b12 : Test purpose (must be set at 0 in
functional mode)
LSB
b6
b5
b4
b3
b2
b1
b0
Description: Enable/Disable interrupt on INTR pin
b0 : SCCF interrupt mask
b1 : Max Delay Alarm mask
b2 : Illegal Address mask
b3 : TDM out of frame mask
b4 : RS block error mask
b5 : SCH interrupt mask
b6 : Test purpose
Reg name: ERROR_REG
Internal address: 20DH
Type: R/W
Reset Value: 00H
MSB
X
LSB
b6
b5
b4
b3
Description: Interrupt register
b0 : SCCF interrupt on
b1 : Max Delay Alarm on
24/43
b0
b2
b1
b0
STA002
tency.
The number of wrong bits is accumulated into a
register according to a given time base expressed in number of bits and, assuming that the
BER at the output of the Viterbi decoder is negligible with respect to the input BER, this count can
be read by the system micro controller to evaluate the signal quality after QPSK demodulation.
The error rate measurement is programmable
throught the VITERBI_ERROR_CONTROL register and the error rate is available in the registers:
- VIT_ERROR 1
- VIT_ERROR 2
b2 : Illegal Address on
b3 : TDM out of frame on
b4 : RS block error on
b5 : SCH interrupt on
b6 : Test purpose
Reg name: STATUS REG
Internal address: 20EH
Type: R
Reset Value: 00H
MSB
X
LSB
X
b5
b4
b3
b2
b1
b0
Description: Status register:
b0 : TSCC available
b1 : BC lock
b2 : SCH available
b3 : PRC lock
b4 : MFP lock
b5 : SCCF available
5. VITERBI DECODER AND SYNCHRONIZATION
A Viterbi decoder has been implemented in the
STA002 in order to extract the most probable
transmitted sequence using a trace back procedure.
This Viterbi decoder has been realized using 64bit trace back depth and the soft decision approach on the six-bit I and Q components coming
from the QPSK demodulator.
The convolutive codes are generated by the polynomials Gx = 171oct and Gy = 133oct.
The Viterbi decoder computes for each symbol
the metrics of the four possible paths, proportional to the square of the Euclidian distance between the recived I and Q and the theoretical
symbol value.
Four logical RAM banks (implemented with eight
RAM blocks of 32x64 bits) have been used for
the path memory.
The decoding latency is 256 bits.
A bit error (BER) estimator has been integrated in
the Viterbi block.
Corrected data bits at Viterbi output are encoded
according to the transmission convolutional code
so that a "good" stream is obtained. These data
are compared with the data stream coming from
the QPSK demodulator after having stored it into
a memory buffer to compensate the Viterbi la-
Reg name: VITERBI_ERROR_CONTROL
Internal address: 204 H
Type: R/W
Reset Value: 00H
MSB
LSB
X
X
X
X
b3
b2
b1
b0
Description: Viterbi input errors measurement
windows length and error mode presetting.
b1b0 =
00
01
10
11
Monitor windows length (bits)
1024
4096
16384
65536
b2
=
0
Error Measurement Mode
Single acquisition mode
b2
b3
=
=
1
0
b3
=
1
Continuous acquisition mode
End measurement (single /continuous
acquisition )
Single acquisition start
Reg name: VIT_ERR0R1, VIT_ERROR2
Internal address: 213 H , 214H
Type: R/W
VIT_ERROR 1 (ERROR COUNTER LOW)
MSB
A7
LSB
A6
A5
A4
A3
A2
A1
A0
VIT_ERROR 2 (ERROR COUNTER HIGH)
MSB
A15
LSB
A14
A13
A12
A11
A10
A9
A8
Description: Viterbi error counter register
25/43
STA002
6. REED SOLOMON DECODER
The STA 002 performs a real time block decoding
operation both on the Time Slot Control Channel
(TSCC) field and on the Broadcast Channel (BC)
stream by means of a programmable Reed-Solomon (RS) decoder.
This decoder works on blocks of 255 words of 8
bit symbols where the first 223 words represent
the information and the last 32 the code redundancy.
The synchrobyte is the first byte of the block.
All the correction capability of the code is used so
it is possible the correction of blocks containing
up to 16 errors while blocks with greater number
of errors are flagged as corrupted.
The RS decoder is programmable to support two
different Galois field generator polynomials as required by WorldSpace specifications and includes
an integrated BER estimator.
Monitoring the number of wrong words in each
block and correlating this number with the block
length, it is possible, provided that no corrupted
blocks are present, to get an estimation of the
signal quality at the Viterbi decoder output.
6.1 TSCC REED SOLOMON DECODER
The code generator polynomial is:
MSB
LSB
X
X
X
X
b3
b2
b1
Description: Reed Solomon input errors measurement windows length and error mode presettings
Monitor windows length (blocks)
3
64
256
1024
b1b0 =
00
01
10
11
b2
=
0
Single acquisition mode
b2
=
1
Continuous acquisition mode
b3
=
0
End measurement (single /continuous
acquisition
b3
=
1
Single acquisition start
Error Measurement Mode
Reg name: RS_BYTE_ERROR1,
RS_BYTE_ERROR2
Internal address: 215 H , 216H
Type: R/W
RS_BYTE_ERR0R1 (ERROR COUNTER LOW)
MSB
143
g(X) = ∏ (x − α
11J
) over the Galois Field
b0
b7
LSB
b6
b5
b4
b3
b2
b1
b0
J = 112
generated by X8+X7+X2+X+1.
6.2 BROADCAST CHANNEL RS DECODER
AND DESCRAMBLER.
The code generator polynomial is:
g(x) = (x-ω°) (x-ω1) (...) (x-ω31)
over the Galois Field generated by:
X8+X4+X3+X2+1=0
6.3 ENERGY DISPERSAL DESCRAMBLER
The descrambler generator polynomial is:
X9+X5+1
Reg name: RS_ERROR_CONTROL
Internal address: 212H
Type: R/W
Reset Value: 00H
26/43
RS_BYTE_ERROR
HIGH)
2
(ERROR
COUNTER
MSB
X
LSB
X
b13
b12
b11
b10
b9
b8
Description: RS byte error counter register
Reg name: RS_BLOCK_ERROR
Internal address: 217H
Type: R/W
MSB
b7
LSB
b6
b5
b4
b3
b2
b1
Description: RS block error counter register
b0
STA002
7. BROADCAST CHANNEL DEMULTIPLEXER
7.1 SCH REGISTER
Reg name: BRI_REG & NSC_REG
Internal address: 000H
Type: R
MSB
b7
MSB
b7
LSB
b6
b5
b4
b3
b2
b1
b0
Description:
b7 to b4 indicate the bit rate of the BC
(BRI field in the SCH)
0000: no valid data
0001: 16Kbps
..............................
1000 : 128Kbps
1001 - 1111: RFU
b3 = 0
b2 to b0 indicate the number of service components (NSC field in the SCH)
000: one Service Component
001: two Service Component
...............................................
111: eight Service Component
Reg name: EC_REG
Internal address: 001H
Type: R
MSB
b7
LSB
b6
b5
b4
b3
b2
Reg name: AFCI1_REG
Internal address: 002H
Type: R
b1
b0
Description:
b7 to b4 = 0000
b3 to b0 indicate the encryption strategy (Encryption Control field in the SCH)
0000: no encryption
0001: static Key
0010: ESI, common key, subscription period A
0100: ESI, broadcast channel specific key for
subscription period A
0101: ESI, broadcast channel specific key for
subscription period B
else: RFU
LSB
b6
b5
b4
b3
b2
b1
b0
Description :
b7 to b5 = 000
b4 to b0 indicate the Auxiliary field content indicator 1 (ACI1l field in the SCH)
00000: not used
00001: 16 bit encryption key selector
00010: RDS PI code
00011: Associated Broadcast Channel reference
(PS flag and ASP)
else: RFU
Reg name: AFCI2_REG
Internal address: 003H
Type: R
MSB
b7
LSB
b6
b5
b4
b3
b2
b1
b0
Description:
b7 : 0
b6 to b0 indicate the Auxiliary field content indicator 2 (ACI2 field in the SCH)
00000: not used
00001:64 bit encryption key selector
00010: Service Label
else: RFU
Reg name: SOF_SF_REG
Internal address: 0041H
Type: R
MSB
b7
LSB
b6
b5
b4
b3
b2
b1
b0
Description:
b7 to b5 = 000
b4 indicate the ADF2 multiframe start flag (SF
field in the SCH)
1: first segment of multiframe or no multiframe
0: intermediate segment of multiframe
b3 to b0 indicate the segment offset and lenght
field (SFT field in the SCH) if SF = 1 SOLF contains the total number of multiframe segments minus 1.
27/43
STA002
0000: one segment multiframe
0001: two segment multiframe
.................................................
1111: 16 segment multiframe
if SF = 0 SOLF contains the segment offset.
ADF2(31:24) (addr 00AH)
MSB
b31
LSB
b30
b29
b28
b27
b26
b25
b24
ADF2(23:16) (addr 009H)
Reg name: ADF1_REG
Internal address: 006H, 005H
Type: R
MSB
b23
LSB
b22
b21
b20
b19
b18
b17
b11
b10
b9
b16
ADF2(15:8) (addr 008H)
ADF1 (15:8) ( addr 006H)
MSB
MSB
b15
LSB
b14
b13
b12
b11
b10
b9
b15
LSB
b14
b13
b12
b8
b8
ADF2(7:0) (addr 007H)
ADF1 (7:0) ( addr 005H)
MSB
MSB
b7
LSB
b6
b5
b4
b3
b2
b1
b0
Description:
b15 to A0 contain the Auxiliary data field1 (ADF1
field in the SCH) with content defined by
AFCI1_REG)
b63
b61
b60
b59
b58
b57
b55
b56
LSB
b54
b53
b52
b51
b50
b49
b48
ADF2(47:40) (addr 00CH)
MSB
b47
LSB
b46
b45
b44
b43
b42
b41
b40
ADF2(39:32) (addr 00BH)
MSB
b39
28/43
LSB
b38
b37
b36
b35
b34
b33
A4
A3
A3
A1
A0
Description:
b64 to b0 contain the Auxiliary data field2 (ADF2
field in the SCH) with content defined by
AFCI2_REG)
b7
ADF2(55:48) (addr 00DH)
MSB
A5
MSB
LSB
b62
A6
Reg name: SEL_SC_REG
Internal address: 00FH
Type: R/W
Reg name: ADF2_REG
Internal address: 00EH,00DH, 00CH, 00BH,
00AH, 009H, 008H, 007H,
Type: R
ADF2(63:56) (addr 00EH)
MSB
A7
LSB
b32
LSB
b6
b5
b4
b3
b2
b1
b0
Description :
b7: =1 Enable service component selection A
= 0 Disable
b6 to b4 contain the Service Component selection A
000: SC1
001: SC2
...............
111: SC8
b3: =1 Enable service component selection B
= 0 Disable
b2 to b0 contain the Service Component selection B
000: SC1
001: SC2
...............
111: SC8
STA002
Reg name: PIW_ RAM
Internal address: 03F,03E, 03D, 03C,
03B, 03A, 039, 038,
Type: W
PIW_RAM (63:56) (addr 03F)
Reg name: EM_REG
Internal address: 018H
Type: R/W
MSB
b7
MSB
b63
b62
b61
b60
b59
b58
b57
MSB
b56
LSB
b54
b53
b52
b51
b50
b49
b48
PIW_RAM (47:40) (addr 03D)
MSB
b47
LSB
b46
b45
b44
b43
b42
b41
b5
b4
b3
b2
b1
MSB
LSB
b38
b37
b36
b35
b34
b33
b32
Description :
Encryption mode register
b7 to b1 = not used RFU
b0 indicate the encryption mode (1)
1: normal encryption mode
0: enable blocking
(1) for more information refer to document
number WST-WSG-DDS-003-500000
Chipset Encryption Implementation Specification
for World space receiver
Reg name: PIWE_REG
Internal address: 01AH, 019H
Type: R/W
PIWE (15:8) (addr 01AH)
MSB
PIW_RAM (31:24) (addr 03B)
b15
MSB
b31
b30
b29
b28
b27
b26
b25
b24
b13
b12
b11
b10
b9
b3
b2
b1
MSB
MSB
b8
LSB
b6
b5
b4
b0
LSB
b22
b21
b20
b19
b18
b17
b16
PIW_RAM (15:8) (addr 039)
MSB
LSB
b14
b13
b12
b11
b10
b9
b8
PIW_RAM (7:0) (addr 038)
MSB
b7
b14
PIWE (7:0) (addr 019H)
b7
b15
LSB
LSB
PIW_RAM (23:16) (addr 03A)
b23
b0
b40
PIW_RAM (39:32) (addr 03C)
b39
b6
LSB
PIW_RAM (55:48) (addr 03E)
b55
LSB
LSB
b6
b5
b4
b3
b2
b1
b0
Description:
b63 tob0 contain the prestored initialization word
0 which is the only one downloadable by the
processor.
Description :
b15 to b0 contain the 16 BIT static key selector
word. Each bit PIWE enables a certain static key.
If bit A0 of PIWE is set, the static key 0 will be enabled for read out and so forth.
Reg name: BCIN_DELAY_REG
Internal address: 01BH
Type: R/W
Default 00H
MSB
b7
LSB
b6
b5
b4
b3
b2
b1
b0
Description : BC input delay and BC input enable
register
b0: enables external BC input
29/43
STA002
b2b1 =
00
01
10
11
BC input delay (bytes)
1
2
3
4
IW_REG (47:40) (addr 015)
MSB
b47
b3: Test purpose (must be set at 0 in functional
mode)
b7 to b4: test purpose
b5
b4
b3
b2
b1
b0
Description: BC finite state machine control register (see table 6)
b5 indicates the BC synchronization mode
1: SP preamble detection
0: Synch from PRC
Reg name: IW_REG
Internal address: 017, 016, 015, 014,
013, 012, 011, 010,
Type: W
IW_REG (63:56) (addr 017)
MSB
b63
LSB
b62
b61
b60
b59
b58
b57
b43
b42
MSB
b38
b37
b36
b35
b34
b33
b31
b26
b25
b52
b51
b29
b28
b27
b50
b49
b24
IW_REG (23:16) (addr 012)
MSB
b23
LSB
b22
b21
b20
b19
b18
b17
b16
IW_REG (15:8) (addr 011H)
MSB
b15
LSB
b14
b13
b12
b11
b10
b9
b8
IW_REG (7:0) (addr 010H)
MSB
b7
LSB
b6
b5
b4
b3
b2
b48
Table 6: BC_ALARM_REG
b4
0
1
b3
0
0
b2
0
0
b1
0
0
b0
0
0
BC FSM active states
sp_detection, sp_presync, sp_sync
sp_detection, sp_presync, sp_sync, alarm_state (1 cycle)
1
1
1
0
0
0
0
0
0
0
1
1
1
0
1
sp_detection, sp_presync, sp_sync, alarm_state (2 cycles)
sp_detection, sp_presync, sp_sync, alarm_state (3 cycles)
sp_detection, sp_presync, sp_sync, alarm_state (4 cycles)
1
1
1
1
1
1
1
1
1
0
1
sp_detection, sp_presync, sp_sync, alarm_state (n cycles)
sp_detection, sp_presync, sp_sync, alarm_state (15 cycles)
sp_detection, sp_presync, sp_sync, alarm_state (16 cycles)
30/43
b32
LSB
b30
LSB
b53
b40
LSB
b1
Description:
b63 to b0 contain the initialization word IW.
MSB
b54
b41
b56
IW_REG (55:48) (addr 016)
b55
b44
MSB
LSB
X
b45
IW_REG (31:24) (addr 013)
MSB
X
b46
IW_REG (39:32) (addr 014)
b39
Reg name: BC_ALARM_REG
Internal address: 01CH
Type: R/W
Default:20H
LSB
b0
STA002
SCH_MEM REGISTERS
Service Component Control Field (SCCF)
Reg name: SERVICE COMPONENT 1
Internal address: 100H, 101H, 102H, 103H
Type: R
Description :
Contains information about the service component of the broadcast channel
b7 to b0 = SC language
SC1_LENGHT & SC1_TYPE (addr 100H)
SC2 _LENGHT & SC2_TYPE(addr 104H)
MSB
b31
b30
b29
b28
b27
b26
b25
LSB
MSB
b24
b31
SC1_EC & SC1_PT (addr 101H)
b22
b21
b20
b19
b18
b17
LSB
MSB
b16
b23
SC1_PT (addr 102H)
b14
b13
b12
b11
b10
b9
LSB
MSB
b8
b15
LANGUAGE 1 (addr 103H)
b6
b5
b4
b29
b28
b27
b26
b25
b24
LSB
b22
b21
b20
b19
b18
b17
b11
b10
b9
b16
b3
LSB
b14
b13
b12
b8
LANGUAGE 2 (addr 107H)
MSB
b7
b30
SC2_PT (addr 106H)
MSB
b15
LSB
SC2 _EC & SC2_PT (addr 105H)
MSB
b23
Reg name: SERVICE COMPONENT 2
Internal address: 104H, 105H, 106H, 107H
Type: R
Description :
Contains information about the service component of the broadcast channel
b2
b1
LSB
MSB
b0
b7
b31 to b28 = SC length Bit rate of the service
component divided by 8 kbps:
0000: 8 kbps
0001: 16 kbps
...............
1111: 128 kbps
b27 to b24 = SC type
Type of service component:
0000: MPEG
0001: general data
0100:JPEG
0101: MPEG
0101: Low bit rate video
1111: invalid data
else: RFU
b23 = Encryption flag
0: not encrypted SC
1: encrypted SC
b22 to b8 = Program type
LSB
b6
b5
b4
b3
b2
b1
b0
b31 to b28 = SC length Bit rate of the service
component divided by 8 kbps:
0000: 8 kbps
0001: 16 kbps
...............
1111: 128 kbps
b27 to b24 = SC type
Type of service component:
0000: MPEG
0001: general data
0100:JPEG
0101: Low bit rate video
1111: invalid data
else: RFU
b23 = Encryption flag
0: not encrypted SC
1: encrypted SC
b22 to b8 = Program type
b7 to b0 = SC language
31/43
STA002
Reg name: SERVICE COMPONENT 3
Internal address: 108H, 109H, 10AH, 10BH
Type: R
Description :
Contains information about the service component of the broadcast channel
Reg name: SERVICE COMPONENT 4
Internal address: 10CH, 10DH, 10EH, 10FH
Type: R
Description :
Contains information about the service component of the broadcast channel
SC3_LENGHT & SC3_TYPE (addr 108H)
SC4_LENGHT & SC3_TYPE (addr 10CH)
MSB
b31
b30
b29
b28
b27
b26
b25
LSB
MSB
b24
b31
SC3 _EC & SC3_PT(addr 109H)
b22
b21
b20
b19
b18
b17
LSB
MSB
b16
b23
SC3_PT (addr 10AH)
b14
b13
b12
b11
b10
b9
LSB
MSB
b8
b15
LANGUAGE 3 (addr 10BH)
b6
b5
b4
b3
b2
b1
LSB
MSB
b0
b7
b31 to b28 = SC length Bit rate of the service
component divided by 8 kbps:
0000: 8 kbps
0001: 16 kbps
...............
1111: 128 kbps
b27 to b24 = SC type
Type of service component:
0000: MPEG
0001: general data
0100:JPEG
0101: Low bit rate video
1111: invalid data
else: RFU
b23 = Encryption flag
0: not encrypted SC
1: encrypted SC
b22 to b8 = Program type
b7 to b0 = SC language
32/43
b28
b27
b26
b25
b24
LSB
b22
b21
b20
b19
b18
b17
b16
LSB
b14
b13
b12
b11
b10
b9
b8
LANGUAGE 4 (addr 10FH)
MSB
b7
b29
SC4 _PT(addr 10EH)
MSB
b15
b30
SC4_EC & SC3_PT (addr 10DH)
MSB
b23
LSB
LSB
b6
b5
b4
b3
b2
b1
b0
b31 to b28 = SC length Bit rate of the service
component divided by 8 kbps:
0000: 8 kbps
0001: 16 kbps
...............
1111: 128 kbps
b27 to b24 = SC type
Type of service component:
0000: MPEG
0001: general data
0100: JPEG
0101: Low bit rate video
1111: invalid data
else: RFU
b23 = Encryption flag
0: not encrypted SC
1: encrypted SC
b22 to b8 = Program type
b7 to b0 = SC language
STA002
Reg name: SERVICE COMPONENT 5
Internal address: 110H, 111H, 112H, 113H
Type: R
Description :
Contains information about the service component of the broadcast channel
Reg name: SERVICE COMPONENT 6
Internal address: 114H, 115H, 116H, 117H
Type: R
Description :
Contains information about the service component of the broadcast channel
SC5 _LENGHT & SC5_TYPE(addr 110H)
SC6 _LENGHT & SC6_TYPE(addr 114H)
MSB
b31
b30
b29
b28
b27
b26
b25
LSB
MSB
b24
b31
SC5_EC & SC5_PT(addr 111H)
b22
b21
b20
b19
b18
b17
LSB
MSB
b16
b23
SC5_PT (addr 112H)
b14
b13
b12
b11
b10
b9
LSB
MSB
b8
b15
LANGUAGE 5(addr 113H)
b6
b5
b4
b28
b27
b26
b25
b24
LSB
b22
b21
b20
b19
b18
b17
b16
LSB
b14
b13
b12
b11
b10
b9
b8
LANGUAGE6 (addr 117H)
MSB
b7
b29
SC6_PT (addr 116H)
MSB
b15
b30
SC6 _EC & SC6_PT(addr 115H)
MSB
b23
LSB
b3
b2
b1
LSB
MSB
b0
b7
b31 to b28 = SC length Bit rate of the service
component divided by 8 kbps:
000: 8 kbps
001: 16 kbps
...............
1111: 128 kbps
b27 to b24 = SC type
Type of service component:
0000: MPEG
0001: general data
0100: JPEG
0101: Low bit rate video
1111: invalid data
else: RFU
b23 = Encryption flag
0: not encrypted SC
1: encrypted SC
b22 to b8 = Program type
b7 to b0 = SC language
LSB
b6
b5
b4
b3
b2
b1
b0
b31 to b28 = SC length Bit rate of the service
component divided by 8 kbps:
0000: 8 kbps
0001: 16 kbps
...............
1111: 128 kbps
b27 to b24 = SC type
Type of service component:
0000: MPEG
0001: general data
0100: JPEG
0101: Low bit rate video
1111: invalid data
else: RFU
b23 = Encryption flag
0: not encrypted SC
1: encrypted SC
b22 to b8 = Program type
7 to b0 = SC language
33/43
STA002
Reg name: SERVICE COMPONENT 7
Internal address: 118H, 119H, 11AH, 11BH
Type: R
Description :
Contains information about the service component of the broadcast channel
Reg name: SERVICE COMPONENT 8
Internal address: 11CH, 11DH, 11EH, 11FH
Type: R
Description :
Contains information about the service component of the broadcast channel
SC7_LENGHT & SC7_TYPE (addr 118H)
SC8 _LENGHT & SC38_TYPE(addr 11CH)
MSB
b31
b30
b29
b28
b27
b26
b25
LSB
MSB
b24
b31
SC7 _EC & SC7_PT(addr 119H)
b22
b21
b20
b19
b18
b17
LSB
MSB
b16
b23
SC7_PT (addr 11AH)
b14
b13
b12
b11
b10
b9
LSB
MSB
b8
b15
LANGUAGE7 (addr 11BH)
b6
b5
b4
b3
b2
b1
LSB
MSB
b0
b7
b31 to b28 = SC length Bit rate of the service
component divided by 8 kbps:
0000: 8 kbps
0001: 16 kbps
...............
1111: 128 kbps
b27 to b24 = SC type
Type of service component:
0000: MPEG
0001: general data
0100: JPEG
0101: Low bit rate video
1111: invalid data
else: RFU
b23 = Encryption flag
0: not encrypted SC
1: encrypted SC
b22 to b8 = Program type
b7 to b0 = SC language
34/43
b28
b27
b26
b25
b24
LSB
b22
b21
b20
b19
b18
b17
b16
LSB
b14
b13
b12
b11
b10
b9
b8
LANGUAGE8 (addr 11FH)
MSB
b7
b29
SC8 _PT (addr 11EH)
MSB
b15
b30
SC8 _EC & SC8_PT(addr 11DH)
MSB
b23
LSB
LSB
b6
b5
b4
b3
b2
b1
b0
b31 to b28 = SC length Bit rate of the service
component divided by 8 kbps:
0000: 8 kbps
0001: 16 kbps
...............
1111: 128 kbps
b27 to b24 = SC type
Type of service component:
0000: MPEG
0001: general data
0100: JPEG
0101: Low bit rate video
1111: invalid data
else: RFU
b23 = Encryption flag
0: not encrypted SC
1: encrypted SC
b22 to b8 = Program type
b7 to b0 = SC language
STA002
Fig.7 shows the broadcast channel serial data out
(BCDO) burst of 8 bit (MSB first). The data bits
are valid at the negative slope of the clock line
(BCCK).
The BCSYNC signal indicates the first byte of the
broadcast channel Service preamble (04H) allowing an easy syncronization to external modules
using the BC data.
The input BC line (BCDI) must have the same
format of the BC output (BCDO). The data bit
must be valid on the negative edge of the output
clock line (BCCK).
The maximum delay allowed from the output data
and the input data is 4 bytes (4 bursts of 8 bits).
The input delay is programmable via I2C bus with
the BCIN_DELAY_REG register (01BH).
8. GENERAL INFORMATION
8.1 DECRIPTION
The STA002 supports a crypto-scheme named
WES (World Space Encrypton Scheme)
It is composed of two functional blocks:
- CSG (Crypto Sequence Generator)
implemented in the STA002 decoder
- IWG (Initialization Word Generator) processed
by external hardware such as a microcontroller
or a smart card.
The CSG module produces the pseudo-casual
sequence by an algorithm based on the galois arrithmetic.
This algorithm is derived in 2 phases:
1) Key expansion
2) Pseudo casual sequence generation
In the expansion phase activated every frame the
IWG 8 bytes key is used to initialize a 16 bytes
array.
The scrambling procedure, invoked every byte,
implements a pseudo random algorithm.
The XOR operation between the output of the
module the encrypted bytes completes the decryption procedure.
The 8 bytes keyword is loaded before the start of
the new frame to the I2C bus interface.
8.3 SERVICE COMPONENT INTERFACES
The STA002 provides two service component interfaces which support the same protocol:
- SC DATA INTERFACE (SCEN, SCDO, SCCK)
- SOURCE DECODER INTERFACE (SEN, SDO, SCK)
The service component interfaces consists of 3
wires each. Output clock (SCCK/SCK), SC data
(SCDO/SDO) and SC byte sync (SCEN/SEN).
The data transmitted via the service component
interface are 8 bit bursts.
The most significant bit is transmitted first.
As shown in fig.8 the service component serial
data out (SCDO/SDO) combines burst of 8 bit
length (MSB first). The data bit are valid at the
negative edge of the clock line (SCCK/ SCK).
The slope change of the SCEN/SEN indicates the
most significative bit of the 8 bit service component burst.
The SCEN/SEN signal is used if required for the
data bits alignement only.
8.2. BROADCAST CHANNEL INTERFACE
The Broadcast Channel interface consists of 4
wires: output clock (BCCK), output BC data
(BCDO), output BC frame sync. (BCSYNC) and
input BC data (BCDIN).
The data trasmitted and recived via the broadcast
channel interface are 8 bit bursts.
The most significant bit is transmitted first.
Fig. 7: Format Of The Broadcast Channel Interface (BC)
tclk
tclk-off
BCCK
BCDO
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
A
B
C
D
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
X
Y
A
B
BCSYNC
BCDI
PROGRAMMABLE DELAY FROM BC-OUT DATA
TO BC-IN DATA MAX 4 BYTE
tclk-off < 1.2ms
tclk ~ 6.5µs
D97AU744A
35/43
STA002
Fig. 8: Format Of The Service Component Interface
tclk
tclk-off
SCCK/SCK
SCDO/SDO
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
A
B
C
D
SCEN/SEN
tclk-off < 15ms
tclk ~ 6.5µs
D97AU745
CHANNEL DECODER INTERFACES BLOCK DIAGRAM
µP
IIC
SCL
SDA
INTR
RESET
RXI
RF
FRONT
END
RNXI
M_CLK
AGC
LOCK
CHANNEL
DECODER
SOURCE
DECODER
INTERFACE
RF
INTERFACE
SC DATA
INTERFACE
SCCK SCDO SCEN
36/43
MICRO
INTERFACE
BC DATA
INTERFACE
SCK
SDI
MPEG
DECODER
SEN
MINTR
D96AU547C
BCCK
BCDO BCSYNC BCDIN
STA002
8.4 FRAME SYNCRONIZATION TIMES
FRAME SYNCRONIZATION
TDM FRAME 138 ms
MFP 96 SY
MFP TSCC DATA MULTIPLEX
MFP
TSCC 2112 SYMBOLS
TSCC DATA MULTIPLEX
MFP TSCC DATA MULTIPLEX
251712 SYMBOLS
MFP
Tx
TSCC
DATA MULTIPLEX
MFP
TSCC DATA MULTIPLEX
MFP
TSCC
DATA MULTIPLEX
MFP
TSCC
TDM SYNCHRONISATION STATE MACHINE
MFP DETECTION
SYNC
PRE SYNC
TDM STATE MACHINE
MFP DETECTION
TSCC
READ
DATA READ
MFP TSCC
VER FIELD
DATA READ
MFP TSCC
VER FIELD
DATA READ
MFP
VER
TSCC
FIELD
MFP TSCC
VER FIELD
DATA READ
DATA READ
MFP TSCC
VER FIELD
DATA READ
MFP TSCC
VER FIELD
DATA READ
START INTERNAL TIMING
SYNC FOR MFP VERIFICATION
Ta
TSCC AVAILABLE
Ty
MFP LOCK
TSCC
VITERBI & RS
DECODED
DATA FIELD
TSCC
AVAILABLE
ALL PRC EXTRACTED LOCK
I2C INTERFACE
BC FRAME SYNC
PRC FRAME 432 ms
PRC
EXTRACTION
from 1 to8 PRC
CHANNELS
DATA FIELD
PRCP
PRCP DETECTION
BC
SELECTION
PRC
CHANNELS
MULTIPEXING
DATA FIELD
DATA FIELD
PRCP
PRC SYNCHRONISATION STATE MACHINE
PRE SYNC
SYNC
PROTECTED BC FRAME 432 ms
SP
SP
DATA FIELD
VITERBI & RS & DEINTELEAVER
DECODED BC FRAME 432 ms
Tdec
DATA FIELD
DATA FIELD
SP
SCH
SP
DATA FIELD
TDM SYNCHRONISATION STATE MACHINE
CASE 1
NORMAL
SYNC
CASE 2
HW
SYNC
PRE SYNC
SP DETECTION
SYNC
SP LOCK
SP DETECTION
DATA MULTIPLEX
SYNC
SP LOCK
Tx = MFP detection time: 0 to 138ms
Ta = TSCC decodification time:= < 2ms
Ty = PRCP detection time: 0 to 432ms
Tdec = VITERBI decoding +
REED SOLOMON error correction +
deinterleaving: ~55ms x PRC number
TDM SYNCRONIZATION TIME
TDM lock = QPSK lock + Tx + 138ms
PRC SYNCRONIZATION TIME
PRC lock = QPSK lock +TDM lock + Ty + 432 ms
BC SYNCRONIZATION TIME
CASE 1 ( SW sync):
the BC synchronization FSM asserts the lock sig-
nal when the SP is detected two consecutive
times.
BC lock = QPSK lock + TDM lock + Ty + Tdec +
432 ms
CASE 2 ( HW sync):
the BC synchronization FSM asserts the lock signal when the BC FRAME SYNC signal is asserted by the PRC alignment FSM and the SP is
valid.
BC lock = QPSK lock + TDM lock + Ty + Tdec
Note :
About the BC synchronisation, the selection between SW sync and HW syn is achievable
through the register BC_ALARM add 01CH bit
b5.
Bit b5 = 1 indicates the SW sync Bit b5 = 0 indicates HW sync.
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STA002
SCH & SCCF INTERRUPT
BC FRAME 432 ms
20 bit
SP
SCH
DATA MULTIPLEX
SP
SCH
DATA MULTIPLEX
SP
SCH
DATA MULTIPLEX
Tx
SP
SCH
DATA MULTIPLEX
SP
SCH
TDM SYNCHRONISATION STATE MACHINE
SP
DETECTION
DATA MULTIPLEX
SP
SCH
DATA MULTIPLEX
SP
SCH
( CASE 1)
SYNC
PRE SYNC
TDM SYNCHRONISATION STATE MACHINE
(CASE 2)
SYNC
SP
DETECTION
DATA FIELD
SCH
DATA FIELD
Service Component
Control Field
Service Control Data
Service Component multiplex
SP
BRI EC ACI1 ACI2
Nsc ADF1 SF SOLF ADF2 SCCF-1
SCCF-8
Dynamic Labels
Service Component multiplex
Tsccf
SCCF interrupt
Tsch
SCH interrupt
SCCF available
Tm
SCH available
reset by SW
Tm = SCCF/ SCH not available setup ~ 32 ms
Tsch = SCH interrupt time ~ 1 3.5 ms
Tsccf = SCCF interrupt time ~
BRI = Bit Rate Index ( from 1 to 8)
Nsc = number of Service Component ( from1 to
8)
432
⋅ 128 + Nsc ⋅ 32ms
7136 ⋅ BRI
8.5 LOSS OF SYNC TABLE
MPF
PRC
BC
TDM Out of Frame unlocked unlocked unlocked
PRC Out of Frame locked unlocked unlocked
locked
locked unlocked
BC Out of Frame
CONTROL REGISTER
TDM OOF PRC OOF
BC OOF
b2
b4
b5
0
1
0
0
0
X
1
0
0
X
X
1
MFP
lock
b4
1
0
1
1
TSCC available
SCH available
SCCF available
not available
available
available
*
*
*
*
*
*
PRC
lock
b3
1
0
0
1
STATUS REGISTER
BC
TSCC
lock
available
b1
b0
1
1
0
0
0
1
0
1
SCH
available
b2
1
*
*
*
* Meaningful only if all the sync levels (MFP, PRC, BC) are locked otherwise not significant
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SCCF
available
b5
1
*
*
*
STA002
8.6 I/O CELL DESCRIPTION
1) CMOS Output Pad Buffer, 2mA, with Slew Rate Control / Pins number 2, 13, 18, 24, 27, 28, 29, 31,
36, 37, 39, 41, 43
OUTPUT PIN
MAX LOAD
Z
50pF
Z
A
D98AU920
2) CMOS Schmitt Trigger Bidir Pad Buffer, 4mA, with Slew Rate Control / Pin number 10
EN
IO
INPUT PIN CAPACITANCE
A
IO
ZI
5pF
OUTPUT
PIN
MAX
LOAD
IO
100pF
D98AU921
3) CMOS Schmitt Trigger Input Pad Buffer / Pin number 16
A
INPUT PIN
A
Z
CAPACITANCE
3.5pF
D98AU923
4) CMOS Input Pad Buffer with Active Pull-Down / Pins number 11, 11, 12
A
Z
INPUT PIN
CAPACITANCE
A
3.5pF
D98AU923
5) CMOS Input Pad Buffer / Pins number 10, 22, 23, 25, 32, 33, 34, 44
A
Z
OUTPUT PIN
CAPACITANCE
A
3.5pF
OUTPUT PIN
CAPACITANCE
A
3.5pF
D98AU906
6) CMOS Input Pad Buffer with Active Pull-Up / Pin number 20
A
Z
D98AU907
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STA002
I/O CELL DESCRIPTION (Continued)
7) Analog Pad Buffer / Pins number 5, 6
Z
A
OUTPUT PIN
CAPACITANCE
A
4pF
OUTPUT PIN
A
TOTAL CAPACITANCE
4pF
D98AU924
8) M_CKL Input Stage / Pin number 9
VREF
A
Z
D98AU925
9) RXI/NRXI Input Stage / Pins number 5, 6
RXI
COMPARATOR 1
NRXI
A
Z
RXI
COMPARATOR 2
NRXI
B
Z
RXI
COMPARATOR 7
NRXI
D98AU926
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STA002
INPUT PIN
A/AI
CAPACITANCE
4pF
NRXI Electrical Characteristics
Symbol
Cm
Cmr
DiV
Parameter
Common Mode Voltage
Common Mode Voltage Range
Min.
Typ.
VDD -0.5
Max.
Unit
V
Note
1
VDD -0.3
V
2
1V Peak to Peak
V
VDD -2
Differential Input Voltage
Note 1: VA = VB Open circuit voltage
Note 2; VA = VB
8.7 APPLICATION NOTE (Registers preset)
According to the choosen M_CLK frequency
some registers values must be changed.
Table 7 shows two different presets for M_CLK =
39.0268MHz and M_CLK = 14.72MHz
Table 7:
HEX_COD DEC_COD
REGISTER NAME
M_CLK = 39.0268MHz
PRESET
38H
50H
M_CLK = 14.72MHz
PRESET
38H
50H
80H
81H
128
129
QPSK_CONTROL1
QPSK_CONTROL2
82H
83H
84H
130
131
132
AGC1_REF1
AGC1_REF2
AGC1_BETA
C8H
00H
05H
C8H
00H
05H
8AH
8BH
8CH
138
139
140
SYM_FREQ1
SYM_FREQ2
SYM_FREQ_
D3H
11H
0CH
00H
00H
10H
8DH
8FH
90H
91H
92H
93H
141
143
144
145
146
147
TIM_FLT_PAR
CAR_FLT_PAR
IF_FREQ1
IF_FREQ2
IF_FREQ3
IF_FREQ4
44H
22H
37H
1DH
C1H
00H
44H
22H
00H
00H
00H
01H
95H
200H
201H
202H
203H
21EH
149
512
513
514
515
542
RAMP_CTRL
TDM_TRSH1
TDM_TRSH2
PRC_TRSH1
PRC_TRSH2
PLL_INT_REG
20H
3CH
3CH
20H
20H
00H
20H
3CH
3CH
20H
20H
01H
220H
223H
544
547
RESERVED1
RESERVED4
06H
02H
06H
02H
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STA002
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STA002
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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© 2002 STMicroelectronics – Printed in Italy – All Rights Reserved
Purchase of I2C Components of STMicrolectronics, conveys a license under the Philips I2C Patent Rights to use these components in an I2C
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