MITSUBISHI MITSUBISHI 〈DIGITAL 〈DIGITAL ASSP〉 ASSP〉 M66305AP/AFP M66305AP/AFP TOGGLE LINE BUFFER TOGGLE LINE BUFFER DESCRIPTION M66305A Toggle Line Buffer has two 5,120-bit line buffer memories. It takes in serial data that arrives synchronously with clock pulses and outputs it in serial at a rate of up to 10 Mbits per second synchronously with external clock pulses. This buffer employs the double buffer system: While data is being output, data on the next line can be written on the other line buffer memory. PIN CONFIGURATION (TOP VIEW) GND INPUT CLOCK SICLK INPUT DATA SIDATA FEATURES • 5,120 × 1bit serial input-serial output line buffer memories • Data transmission at 10 megabits/second maximum • Two line buffer memories can be alternated by external toggle signal. • Memory capacity can be doubled by cascade connection. • Because of cascade input pin (CAS1), output potential after completion of output can be set to either H or L. • Low noise and high fan-out output (IO = ±24mA guaranteed) • Every input pin has built-in Schmidt trigger circuit. • Read counter and write counter can be reset independently. • RESET, T, CNTRST1 and CNTRST2 are equipped with negative noise reduction circuit. M66305AP ICE CASCADE INPUT 1 CAS1 GND T TOGGLE SIGNAL INPUT CS CHIP SELECT INPUT RESET INPUT RESET GND INPUT CLOCK ENABLE 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC SODATA SOCLK OCE CAS2 CNTRST2 CNTRST1 VCC BF INT OUTPUT DATA OUTPUT CLOCK OUTPUT CLOCK ENABLE CASCADE INPUT 2 READ COUNTER RESET INPUT WRITE COUNTER RESET INPUT (5V) BUFFER FULL OUTPUT WRITE REQUEST OUTPUT Outline 20P4 GND INPUT CLOCK SICLK INPUT DATA SIDATA APPLICATION Data buffer between industrial or home-use image data processing system and peripheral equipment M66305AFP ICE CASCADE INPUT 1 CAS1 NC NC GND T TOGGLE SIGNAL INPUT CS CHIP SELECT INPUT RESET INPUT RESET GND INPUT CLOCK ENABLE 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC SODATA SOCLK OCE CAS2 NC NC CNTRST2 CNTRST1 VCC BF INT OUTPUT DATA OUTPUT CLOCK OUTPUT CLOCK ENABLE CASCADE INPUT 2 READ COUNTER RESET INPUT WRITE COUNTER RESET INPUT (5V) BUFFER FULL OUTPUT WRITE REQUEST OUTPUT Outline 24P2W-A NC: No Connection BLOCK DIAGRAM CHIP SELECT INPUT Matching detection circuit INT CS OCE READ COUNTER CNTRST2 RESET INPUT Write register Write counter INPUT DATA SIDATA CASCADE INPUT 1 CAS1 AD S-RAM 5120 bits DI D0 WR AD S-RAM 5120 bits DI D0 WR SOCLK OUTPUT CLOCK Data selector Read counter WRITE COUNTER RESET INPUT CNTRST1 Address selector RESET INPUT RESET ICE TOGGLE SIGNAL INPUT T Data buffer SODATA OUTPUT DATA BF INPUT CLOCK SICLK INPUT CLOCK ENABLE Switch and P.G. WRITE REQUEST OUTPUT OUTPUT CLOCK ENABLE BUFFER FULL OUTPUT Toggle F/F 1 MITSUBISHI 〈DIGITAL ASSP〉 M66305AP/AFP TOGGLE LINE BUFFER FUNCTION When the status of input clock enable (ICE) is “L”, input data (SIDATA) is taken in (written) synchronously with input clock (SICLK) rise edge. When output clock enable (OCE) is “L”, output data (SODATA) is output (read) synchronously with output clock (SOCLK) fall edge. The double buffer system makes independent read and write operation possible. When one-line write and one-line read are completed, toggle signal (T) is required to be changed to “L”, With input of toggle signal, the line buffer memory which has completed write op- eration is switched to read mode, and the line buffer which has completed output is switched to write mode, enabling next write and read operations. To rewrite data during write operation, use write counter reset input (CNTRST1). To repeat output during output operation, use read counter reset (CNTRST2). These operations are possible only when the status of chip select (CS) is “L”. FUNCTION TABLE Input OCE SOC X X X X H X H X L L RES L H H H H H CS X H L L L L ICE X X H L H L SIC X X X H L L L X L H H H L H X X L H H H H H H L L L L L H X X L X X X X X L H X X L X Q0 x *1 *2 *3 *4 *5 *6 2 : : : : : : : : X T X X H H H H H H H H Output INT H Q0 Q0 Q0 *3 *3 BF H Q0 Q0 *1 Q0 *1 *4 H H *5 *5 H With CNTRST1 input, internal write counter is reset, enabling rewriting. *6 H *6 With CNTRST2 input, internal read counter is reset, enabling retrial of output. CR1 CR2 SOD X X L X X Q0 H H Q0 H H Q0 H H *2 H H *2 H H H H Remarks Initialization No internal change, no output change No internal change, no output change With rise of SICLK, data is written on line buffer memory. With fall of SOCLK, data is output. Write and read With rise of T: 1) Line buffer memory in read mode is switched to write mode and the other in write mode is switched to read mode. 2) BF and INT are canceled. No change “H” or “L” BF changes from “H” to “L” with rise of SICLK for write of 5120th bit. With fall of SOCLK, data written before toggle signal input is output in order. INT changes from “H” to “L” when the status of SOCLK rises after output of final bit of written before toggle signal inputs. Outputs the first bit of written data (D0). Output operation can be performed irrespective of CNTRST1. SODATA changes to the first bit of written data (D0). Write operation can be performed irrespective of CNTRST2. MITSUBISHI 〈DIGITAL ASSP〉 M66305AP/AFP TOGGLE LINE BUFFER PIN DESCRIPTION Pin RESET CS Name Reset input Chip select input ICE Input clock enable SICLK SIDATA OCE Input clock Input data Output clock enable SOCLK Output clock SODATA Output data T Toggle signal input BF Buffer full output INT Write request output CNTRST1 CNTRST2 CAS1 Write counter reset input Read counter reset input Cascade input 1 CAS2 Cascade input 2 NC No Connection Functions Initializes integrated circuit. (SODATA =“L”, BF =“H”, INT = “H”) “L”: Chip select “H”: Non-select (Inputs other than RESET have no effects on circuit inside.) “L”: Input clock (SICLK) enable “H”: Input clock (SICLK) disable With rise of SICLK, SIDATA is written on line buffer memory. “L”: Output clock (SOCLK) enable “H”: Output clock (SOCLK) disable With fall of SOCLK, SODATA is output. Because buffer is provided between memory and output, each piece of data is propagated at a constant rate, irrespective of internal memory read access time. The line buffer memory in write mode is switched to read mode, and the other in read mode is switched to write mode. Output when SICLK rises for input of 5,120th bit, indicating no more writing is possible. When BF is “L”, circuit inside is automatically set to “input disable”. BF is canceled with rise of toggle signal (T) status. Output when SOCLK rises after output of final bit of written data. When INT is “L”, circuit inside is automatically set to “output disable”. INT is canceled with rise of toggle signal (T) status. Used to rewrite data during write operation when CS is “L”. Used to undo data output halfway or to retry output when CS is “L”. Output when SOCLK falls after output of final bit of written data. When cascade connection is not used, be sure to connect this pin to VCC or GND. Up to 2 cascade connections are possible. Connect the CA2 pin of master IC to V CC, and the CA2 pin of slave IC to GND. Refer to APPLICATION EXAMPLE for details. Non-connected pin provided only for M66305AFP. This pin can be used for wiring. 3 MITSUBISHI 〈DIGITAL ASSP〉 M66305AP/AFP TOGGLE LINE BUFFER BASIC TIMING DIAGRAM ICE SICLK SIDATA D0(B) D1(B) D2(B) D5118(B) D5119(B) D0(C) BF T OCE SOCLK SODATA D0(A) D1(A) D5118(A) D5119(A) CAS1 D0(B) INT * Circuit operates as shown in this timing chart in case one line length 5,120. If the line length is shorter than this, BF stays “H” status. Start Reset OPERATION FLOWCHART During the first cycle of operation after reset, write operation is possible but read operation is impossible. Input toggle signal (T) after the one-line data is written. During the second and following cycles, the previous written data can be output or new data can be written in parallel. After one-line data is written and output is completed (INT output), input toggle signal (T). Write operation Completion? NO YES Toggle signal Write operation Output operation Write completion and INT detection? YES Completion? YES END 4 NO NO MITSUBISHI 〈DIGITAL ASSP〉 M66305AP/AFP TOGGLE LINE BUFFER ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO Pd Tstg Parameter Supply voltage Input voltage Output voltage Power dissipation Storage temperature Conditions Ratings –0.5 ~ +7.0 –0.5 ~ VCC + 0.5 –0.5 ~ VCC + 0.5 700 –65 ~ 150 mounted Unit V V V mW °C RECOMMENDED OPERATIONAL CONDITIONS (Ta = –10˚C ~ 70°C unless otherwise noted) Symbol VCC GND VI VO Topr Parameter Conditions Supply voltage Supply voltage Input voltage Output voltage Operating ambient temperature Min. 4.5 Limits Typ. 5.0 0.0 0.0 0.0 –10 Max. 5.5 VCC VCC 70 Unit V V V V °C ELECTRICAL CHARACTERISTICS (Ta = –10˚C ~ 70°C, VCC = 5V±10% and GND = 0V unless otherwise noted) Symbol Parameter Test conditions VT+ VT– VT+ - VT– Positive threshold voltage Negative threshold voltage Hysteresis width All input VOH “H” output voltage IOH=–24mA VOL “L” output voltage IOL=+24mA ICC Quiescent supply current VI=VCC or GND IIH IIL CI “H” input current “L” input current Input capacitance VI=5.5V VI=0V Min. Limits Typ. Max. 2.4 0.6 VCC – 0.8 0.4 VCC–0.35* VCC–0.4** 0.25* 0.30** 55* 45** Unit V V V V 0.53 130 110** +1.0 –1.0 10 V mA µA µA pF The current flowing into the IC is positive current. *Ta=25˚C **Ta=70˚C 5 MITSUBISHI 〈DIGITAL ASSP〉 M66305AP/AFP TOGGLE LINE BUFFER TIMING CONDITIONS (Ta = –10˚C ~ 70°C, VCC = 5V±10% and GND = 0V unless otherwise noted) Symbol Parameter tw±(SIC) Input clock pulse width (Note 2) tw±(SOC) Output clock pulse width (Note 2) tw(T) tw(RES) tw(CR1) tw(CR2) tsu(SID-SIC) th(SIC-SID) tsu(ICE-SIC) th(SIC-ICE) tsu(CS-SIC) th(SIC-CS) tsu(OCE-SOC) th(SOC-OCE) tsu(CS-SOC) th(SOC-CS) tsu(CS-T) th(T-CS) th(SIC-T) trec(T-SIC) th(SOC-T) trec(T-SOC) tsu(CS-CR1) th(CR1-CS) tsu(CS-CR2) th(CR2-CS) trec(R-SIC/SOC) trec(CR1-SIC) trec(CR2-SOC) Toggle signal input pulse width Reset input pulse width Write counter reset input pulse width Read counter reset input pulse width Input data setup time before input clock Input data hold time after input clock Input clock enable setup time before input clock Input clock enable hold time after input clock Chip select setup time before input clock Chip select hold time after input clock Output clock enable setup time before output clock Output clock enable hold time after output clock Chip select setup time before output clock Chip select hold time after output clock Chip select setup time before toggle signal input Chip select hold time after toggle signal input Toggle signal hold time after input clock Input clock recovery time after toggle signal input Toggle signal hold time after output clock Output clock recovery time after toggle signal input Chip select setup time before write counter reset Chip select hold time after write counter reset Chip select setup time before read counter reset Chip select hold time after read counter reset Input and output clock recovery time after reset Input clock recovery time after write counter reset Output clock recovery time after read counter reset Min. 30 43* 50 150 100 100 100 25 0 25 0 150 100 25 0 150 100 100 100 100 150 100 150 100 100 100 100 100 150 150 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 2 To satisfy switching characteristic fmax = 10 MHz (frequency: 100ns), the condition shown below should be met: 100 ns ≤ (tW+) + (tW–) *: Ta=25˚C SWITCHING CHARACTERISTICS (Ta = –10˚C ~ 70°C, VCC = 5V±10% and GND = 0V) Symbol tc(SIC) tc(SOC) Parameter Input clock cycle time Output clock cycle time tPLH(SOC-SOD) Propagation time between input clock and output data tPHL(SOC-SOD) tPHL(SIC-BF) Propagation time between input clock and BF tPHL(SOC-INT) Propagation time between output clock and INT tPLH(T-BF) tPLH(T-INT) tPLH(R-BF) tPLH(R-INT) tPHL(CR1-BF) tPLH(CR2-INT) Propagation time between toggle signal input and BF Propagation time between toggle signal input and INT Propagation time between reset input and BF Propagation time between reset input and INT Propagation time between write counter reset and BF Propagation time between read counter reset and INT Note 3 AC test waveform ; Input pulse level: 0V ~ 3V Input pulse rise time: 6ns 6 Test conditions Input pulse fall time: 6ns CL=50pF CL=150pF CL=50pF CL=150pF CL=50pF CL=150pF CL=50pF CL=150pF CL=150pF Test voltage ; Input voltage: 1.3V Output voltage: 1.3V Min. 100 100 Limits Typ. Max. Unit ns ns 36 40 36 40 75 85 75 85 100 100 100 100 100 100 ns ns ns ns ns ns ns ns ns ns MITSUBISHI 〈DIGITAL ASSP〉 M66305AP/AFP TOGGLE LINE BUFFER TIMING CHARTS CS ICE tsu(ICE-SIC) SICLK tc(SIC) tw+(SIC) tsu(CS-SIC) tsu(SID-SIC) th(SIC-ICE) th(SIC-CS) tw-(SIC) SIDATA th(SIC-SID) ICE (Note 4) tsu(ICE-SIC) th(SIC-ICE) SICLK Note 4. Timing to invalidate the clock. CS OCE tsu(OCE-SOC) SOCLK tc(SOC) tw+(SOC) tsu(CS-SOC) th(SOC-OCE) th(SOC-CS) tw-(SOC) SODATA tPLH(SOC-SOD) tPHL(SOC-SOD) 7 MITSUBISHI 〈DIGITAL ASSP〉 M66305AP/AFP TOGGLE LINE BUFFER OCE tsu(OCE-SOC) th(SOC-OCE) SOCLK SODATA CS T tsu(CS-T) tw(T) th(T-CS) CS CNTRST1 tsu(CS-CR1) tw(CR1) th(TR1-CS) tw(CR2) th(TR2-CS) CS CNTRST2 8 tsu(CS-CR2) MITSUBISHI 〈DIGITAL ASSP〉 M66305AP/AFP TOGGLE LINE BUFFER T SICLK /SOCLK th(SIC-T) th(SOC-T) trec(T-SIC) trec(T-SOC) BF tPHL(SIC-BF) tPLH(T-BF) INT tPHL(SOC-INT) tPLH(T-INT) RESET /CNTRST1 /CNTRST2 SICLK /SOCLK tw(RES) trec(RES-SIC)/(RES-SOC) trec(CR1-SIC) trec(CR2-SOC) BF tPLH(RES-BF)/(CR1-BF) INT tPLH(RES-INT)/(CR2-INT) 9 MITSUBISHI 〈DIGITAL ASSP〉 M66305AP/AFP TOGGLE LINE BUFFER APPLICATION EXAMPLE GND SICLK SIDATA ICE VCC SICLK SIDATA CS RESET CAS2 SODATA SOCLK OCE VCC GND CNTRST2 CNTRST2 T CNTRST1 CNTRST1 VCC CS RESET BF GND INT GND VCC SICLK SIDATA SODATA SOCLK OCE ICE CAS1 (VCC OR GND) SOCLK OCE ICE CAS1 T SODATA CAS2 CAS1 GND CNTRST2 T CNTRST1 VCC CS RESET GND GND BF BF INT INT Note 5. Output clock recovery time after toggle signal input [tre(T-SOC): 1) When one line length is 5,125 bits (5,120 +5) or less, trec(T-SOC) is required to be 500 ns or more. 2) When one line length is 5,126 bits (5,120 +6) or more, trec(T-SOC) is required to be 150 ns or more. Note 6. ICs used in this example connection: M66305A: 2pcs. M74HC32: 1pc. 10