MITSUBISHI
MITSUBISHI
〈DIGITAL
〈DIGITAL
ASSP〉
ASSP〉
M66252P/FP
M66252P/FP
1152 x 8-BIT LINE MEMORY (FIFO)
1152 x 8-BIT LINE MEMORY (FIFO)
FEATURES
• Memory construction ........................................................
............................. 1152words x 8bits (dynamic memory)
• High-speed cycle ............................................ 50ns (min.)
• High-speed access ........................................ 40ns (max.)
• Output hold ....................................................... 5ns (min.)
• Fully independent, asynchronous write and read operations
• Variable-length delay bit
• Output .................................................................... 3-state
PIN CONFIGURATION (TOP VIEW)
Q0
Q1
Data output
Q2
Q3
Read enable input
RE
Read reset input RRES
GND
Read clock input RCK
Q4
Q5
Data output
Q6
Q7
1
2
3
4
5
6
7
8
9
10
11
12
M66252P/FP
DESCRIPTION
The M66252P/FP is a high-speed line memory with a FIFO
(First In First Out) structure of 1152-word × 8-bit configuration
which uses high-performance silicon gate CMOS process
technology.
It has separate clock, enable and reset signals for write and
read and is most suitable as a buffer memory between
devices with different data processing throughput.
24
23
22
21
20
19
18
17
16
15
14
13
D0
D1
D2
D3
WE
WRES
VCC
WCK
D4
D5
D6
D7
Data input
Write enable input
Write reset input
Write clock input
Data input
Outline 24P4Y
24P2W-A
APPLICATION
Digital photocopiers, high-speed facsimiles, laser beam printers.
BLOCK DIAGRAM
Vcc 18
Output buffer
Memory array
(1152 x 8 bits)
Read control circuit
Write
clock input WCK 17
Input buffer
Read address counter
Write
reset input WRES 19
Data output
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
1 2 3 4 9 10 11 12
Write address counter
Write
enable input WE 20
Write control circuit
Data input
D0 D1 D2 D3 D4 D5 D6 D7
24 23 22 21 16 15 14 13
5 RE Read
enable input
6 RRES Read
reset input
8 RCK Read
clock input
7 GND
1
MITSUBISHI 〈DIGITAL ASSP〉
M66252P/FP
1152 x 8-BIT LINE MEMORY (FIFO)
When read enable input RE is “L,” data on memory are output to Q0 thru Q7 synchronously with read clock input RCK
rise edges. At this time, read address counter executes
counting.
The following read-related operations are also performed
synchronously with RCK rise edges.
When RE is “H,” reading from memory is inhibited, and read
address counter stops counting. The status of Q0 thru Q7 becomes high-impedance.
When read reset input RRES is “L,” read address counter is
initialized.
FUNCTION
When the status of write enable input WE is “L,” data on D0
thru D7 are written on the memory synchronously with write
clock input WCK rise edges. At this time, write address
counter executes counting.
The following write-related operations are also performed
synchronously with WCK rise edges.
When WE is “H,” writing on memory is inhibited, and write address counter stops counting.
When write reset input WRES is “L,” write address counter is
initialized.
ABSOLUTE MAXIMUM RATINGS (Ta = –20 ~ 70°C unless otherwise noted)
Symbol
VCC
VI
VO
Pd
Tstg
Parameter
Supply voltage
Input voltage
Output voltage
Power dissipation
Storage temperature
Conditions
Ratings
–0.5 ~ +7.0
–0.5 ~ VCC + 0.5
–0.5 ~ VCC + 0.5
550 (Note 1)
–65 ~ 150
Reference pin: GND
Ta = 25°C
Unit
V
V
V
mW
°C
Note 1: Ta ≥ 62°C are derated at –8.8mW/°C (24P4Y)
Ta ≥ 51°C are derated at –7.5mW/°C (24P2W)
RECOMMENDED OPERATIONAL CONDITIONS
Symbol
VCC
GND
Topr
Parameter
Min.
4.5
Supply voltage
Supply voltage
Ambient temperature
Limits
Typ.
5
0
–20
Max.
5.5
Unit
70
V
V
°C
ELECTRICAL CHARACTERISTICS (Ta = –20 ~ 70°C, VCC = 5V±10%, GND = 0V)
Symbol
VIH
VIL
VOH
VOL
2
Parameter
“H” input voltage
“L” input voltage
“H” output voltage
“L” output voltage
IIH
“H” input current
IIL
“L” input current
IOZH
IOZL
“H” output current under “off” condition
“L” output current under “off” condition
ICC
Average supply current during operation
CI
CO
Input capacitance
Output capacitance under “off” condition
Test conditions
Min.
2.0
Limits
Typ.
Max.
0.55
V
V
V
V
1.0
µA
–1.0
µA
5.0
–5.0
µA
µA
100
mA
10
15
pF
pF
0.8
IOH = –4mA
IOL = 4mA
WE, WRES, WCK, RE,
VI = VCC RRES, RCK
D0~D7
WE, WRES, WCK, RE,
VI = GND RRES, RCK
D0~D7
VO = VCC
VO = GND
VI = VIH, VIL, Outputs are open
tWCK, tRCK = 100ns
f = 1MHz
f = 1MHz
Unit
VCC – 0.8
MITSUBISHI 〈DIGITAL ASSP〉
M66252P/FP
1152 x 8-BIT LINE MEMORY (FIFO)
SWITCHING CHARACTERISTICS (Ta = –20 ~ 70°C, VCC = 5V±10%, GND = 0V)
Symbol
tAC
tOH
tOEN
tODIS
Parameter
Access time
Output hold time
Output enable time
Output disable time
Min.
Limits
Typ.
5
5
5
Max.
40
40
40
Unit
ns
ns
ns
ns
TIMING CHARACTERISTICS (Ta = –20 ~ 70°C, VCC = 5V±10%, GND = 0V)
Symbol
tWCK
tWCKH
tWCKL
tRCK
tRCKH
tRCKL
tDS
tDH
tRESS
tRESH
tNRESS
tNRESH
tWES
tWEH
tNWES
tNWEH
tRES
tREH
tNRES
tNREH
tr, tf
tH
Parameter
Write clock (WCK) cycle time
Write clock (WCK) “H” pulse width
Write clock (WCK) “L” pulse width
Read clock (RCK) cycle time
Read clock (RCK) “H” pulse width
Read clock (RCK) “L” pulse width
Input data setup time (in response to WCK)
Input data hold time (in response to WCK)
Reset setup time (in response to WCK and RCK)
Reset hold time (in response to WCK and RCK)
Reset non-select setup time (in response to WCK and RCK)
Reset non-select hold time (in response to WCK and RCK)
WE setup time (in response to WCK)
WE hold time (in response to WCK)
WE non-select setup time (in response to WCK)
WE non-select hold time (in response to WCK)
RE setup time (in response to RCK)
RE hold time (in response to RCK)
RE non-select setup time (in response to RCK)
RE non-select hold time (in response to RCK)
Input pulse rise time and fall time
Data hold time (Note 1)
Min.
50
25
25
50
25
Limits
Typ.
Max.
Unit
ns
ns
ns
ns
ns
25
15
5
15
5
15
5
15
5
15
5
15
5
15
5
35
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Note 1. The following conditions should be met for each line access:
WE “H” level period ≤ 20ms - 1152 · tWCK - WRES “L” level period
RE “H” level period ≥ 20ms - 1152 · tRCK - RRES “L” level period
2. Perform reset operation after turning on power supply.
3
MITSUBISHI 〈DIGITAL ASSP〉
M66252P/FP
1152 x 8-BIT LINE MEMORY (FIFO)
TEST CIRCUIT
Vcc
Qn
RL=1kΩ
CL= 30pF : tAC, tOH
SW1
Qn
SW2
CL=5pF : tOEN, tODIS
RL=1kΩ
Input pulse level:
0 ~ 3V
Input pulse rise time and fall time: 3ns
Measurement reference level, input: 1.3V
Measurement reference level, output: 1.3V (Note: tODIS (LZ) is tested at 10% output
amplitude, and tODIS (HZ) is tested at 90%
output amplitude.)
Load capacitance CL includes floating capacitance and probe input capacitance.
Parameter
tODIS(LZ)
tODIS(HZ)
tOEN(ZL)
tOEN(ZH)
SW1
Closed
Open
Closed
Open
SW2
Open
Closed
Open
Closed
TEST CONDITIONS FOR OUTPUT DISABLE TIME tODIS AND OUTPUT ENABLE TIME tOEN
3V
RCK
1.3V
1.3V
GND
3V
RE
GND
tOEN(ZH)
tODIS(HZ)
1.3V
tODIS(LZ)
Qn
4
VOH
90%
Qn
tOEN(ZL)
10%
1.3V
VOL
MITSUBISHI 〈DIGITAL ASSP〉
M66252P/FP
1152 x 8-BIT LINE MEMORY (FIFO)
TIMING CHARTS
• Write Cycles
Cycle n
Cycle(n+1)
Cycle(n+2)
Disable cycles
Cycle(n+3)
Cycle(n+4)
WCK
tWCK
tWCKH tWCKL tWEH tNSES
tNWEH tWES
WE
tDS tDH
tDS tDH
(n)
Dn
(n+1)
(n+2)
(n+3)
(n+4)
WRES=“H”
• Write Reset Cycles
Cycle(n–1)
Cycle n
tWCK
tNRESH tRESS
Reset cycles
Cycle 0
Cycle 1
Cycle 2
WCK
tRESH tNRESS
WRES
Dn
tDS tDH
tDS tDH
(n –1)
(n)
(0)
(1)
(2)
WE=“L”
5
MITSUBISHI 〈DIGITAL ASSP〉
M66252P/FP
1152 x 8-BIT LINE MEMORY (FIFO)
• Matters that needs attention when WCK stops
n cycle
n+1 cycle
n cycle
Disable cycle
WCK
tNWES
tWCK
WE
Dn
tDS tDH
tDS tDH
(n)
(n)
Period for writing data (n)
into memory
Period for writing data (n)
into memory
WRES = “H”
Input data of n cycle is read at the rising edge after WCK of n cycle and writing operation starts in the WCK low-level period of
n+1 cycle. The writing operation is complete at the falling edge after n+1 cycle.
To stop reading write data at n cycle, enter WCK before the rising edge after n+1 cycle.
When the cycle next to n cycle is a disable cycle, WCK for a cycle requires to be entered after the disable cycle as well.
6
MITSUBISHI 〈DIGITAL ASSP〉
M66252P/FP
1152 x 8-BIT LINE MEMORY (FIFO)
• Read Cycles
Cycle n
Cycle(n+1)
Cycle(n+2)
Disable cycles
Cycle(n+3)
Cycle(n+4)
RCK
tRCKH tRCKL tREH tNRES
tRCK
tNREH tRES
tAC
RE
tOEN
tODIS
Qn
(n)
(n+1)
HIGH-Z
(n+2)
(n+3)
(n+4)
tOH
RRES=“H”
• Read Reset Cycles
Cycle(n–1)
Cycle n
Reset cycles
tRCK
tNRESH tRESS
Cycle 0
Cycle 1
Cycle 2
RCK
tRESH tNRESS
RRES
tAC
Qn
(n–1)
(n)
(0)
(0)
(0)
(1)
(2)
tOH
RE=“L”
7
MITSUBISHI 〈DIGITAL ASSP〉
M66252P/FP
1152 x 8-BIT LINE MEMORY (FIFO)
VARIABLE-LENGTH DELAY BITS
• 1-line (1152-bit) delay
A write input data is written into memory at the second rise edge of WCK in the cycle, and a read output data is output from
memory at the first rise edge of RCK in the cycle, so that 1-line delay can be made easily.
Cycle 0
Cycle 1
Cycle
1150
Cycle 2
Cycle
1151
Cycle 1’
Cycle 0’
Cycle 2’
WCK
RCK
tRESS tRESH
WRES
RRES
tDS tDH
tDS tDH
Dn
(0)
(1)
(2)
(1149)
(1150)
(1151)
1152 cycles
(0’)
(1’)
(2’)
(1)
(2)
tOH
tAC
Qn
(0)
WE, RE=“L”
• n-bit delay 1
(Making a reset at a cycle corresponding to delay length)
Cycle 0
Cycle 1
Cycle
(n–2)
Cycle 2
Cycle
(n–1)
Cycle 1’
Cycle 0’
Cycle 3’
Cycle 2’
WCK
RCK
tRESS tRESH
tRESS tRESH
WRES
RRES
tDS tDH
tDS tDH
Dn
(0)
(1)
(2)
m cycles
Qn
(n–3)
(n–2)
(n–1)
tAC
(0’)
(1’)
(2’)
(3’)
(1)
(2)
(3)
tOH
(0)
WE, RE=“L”
m≥3
8
MITSUBISHI 〈DIGITAL ASSP〉
M66252P/FP
1152 x 8-BIT LINE MEMORY (FIFO)
• n-bit delay 2
(Sliding WRES and RRES at a cycle corresponding to delay length)
Cycle Cycle n(W) Cycle(n+1)(W) Cycle(n+2)(W) Cycle(n+3)(W)
(n–1)(W) Cycle 0(R) Cycle 1(R) Cycle 2(R) Cycle 3(R)
Cycle 0(W) Cycle 1(W) Cycle 2(W)
WCK
RCK
tRESS tRESH
WRES
tRESS tRESH
RRES
tDS tDH
Dn
(0)
tDS tDH
(1)
(2)
(n–2)
(n–1)
(n)
(n+2)
(n+3)
(1)
(2)
(3)
tDH
tAC
m cycles
(n+1)
Qn
(0)
WE, RE=“L”
m≥3
• n-bit delay 3
(Disabling RE at a cycle corresponding to delay length)
Cycle 0(W) Cycle 1(W) Cycle 2(W)
Cycle Cycle n(W) Cycle(n+1)(W) Cycle(n+2)(W) Cycle(n+3)(W)
(n–1)(W) Cycle 0(R) Cycle 1(R) Cycle 2(R) Cycle 3(R)
WCK
RCK
tRESS tRESH
WRES
RRES
tNREH tRES
RE
tDS tDH
tDS tDH
Dn
(0)
(1)
(2)
m cycles
Qn
HIGH-Z
(n–2)
(n–1)
tAC
(n)
(n+1)
(n+2)
(n+3)
(1)
(2)
(3)
tOH
(0)
WE, RE=“L”
m≥3
9
MITSUBISHI 〈DIGITAL ASSP〉
M66252P/FP
1152 x 8-BIT LINE MEMORY (FIFO)
• Shortest read of data “n” written in cycle n
Cycle n–1 on read side should be started after end of cycle n+1 on write side
When the start of cycle n–1 on read side is earlier than the end of cycle n+1 on write side, output Qn of cycle n becomes invalid.
In the figure shown below, the read of cycle n–1 is invalid.
Cycle n
Cycle n+1
Cycle n+2
Cycle n+3
WCK
(n)
Dn
(n + 1)
Cycle n – 2
(n + 2)
Cycle n – 1
(n + 3)
Cycle n
RCK
invalid
Qn
(n)
• Longest read of data “n” written in cycle n: 1-line delay
Cycle n <1>* on read side should be started when cycle n <2>* on write is started
Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1>* and the start of writing side n cycle <2>* overlap each other.
Cycle n 〈1〉∗
Cycle 0 〈2〉∗
Cycle n 〈2〉∗
WCK
Dn
(n – 1)〈1〉∗
(n)〈1〉∗
Cycle n 〈0〉∗
(0)〈2〉∗
(n – 1)〈2〉∗
Cycle 0 〈1〉∗
(n)〈2〉∗
Cycle n 〈1〉∗
RCK
Qn
(n – 1)〈0〉∗
(n)〈0〉∗
(0)〈1〉∗
(n – 1)〈1〉∗
〈0〉∗, 〈1〉∗ and 〈2〉∗
indicates a line value.
10
(n)〈1〉∗
MITSUBISHI 〈DIGITAL ASSP〉
M66252P/FP
1152 x 8-BIT LINE MEMORY (FIFO)
APPLICATION EXAMPLE
Laplacian Filter Circuit for Correction of Resolution in the Secondary Scanning Direction.
N
Line n image data
M66252
~
~
B
Line (n+1)
image data
Q0
D7
Q7
Adder
N+K {2N–(A+B)}
D0
×2
Subtractor
2N–(A+B)
1-line
delay
Corrected
image data
×K
M66252
Q0
~
~
D7
Q7
Secondary scanning
direction
1-line
delay
A
Line (n–1)
image data
Adder
A+B
D0
Primary scanning
direction
A
Line (n–1)
N
Line n
B
Line (n+1)
N' = N+K {(N–A)+(N–B)}
= N+K {2N–(A+B)}
K : Laplacean coefficient
11