MOTOROLA 33742S

Freescale Semiconductor, Inc.
MOTOROLA
Document order number: MC33742
Rev 2.0, 10/2004
SEMICONDUCTOR TECHNICAL DATA
Advance Information
33742
33742S
System Basis Chip (SBC) with
Enhanced High-Speed CAN
Transceiver
SYSTEM BASIS CHIP
WITH ENHANCED
HIGH-SPEED CAN
Freescale Semiconductor, Inc...
The 33742 and the 33742S are monolithic integrated circuits combining
many functions frequently used by automotive environmental control units
(ECUs).
The 33742 is an SBC having a fully protected fixed 5.0 V low-drop regulator
with current limit, overtemperature pre-warning, and reset. An output drive with
sense input is also provided to implement a second 5.0 V regulator, using an
external PNP bipolar junction transistor. The 33742 has normal, standby, stop,
and sleep modes, an internally switched high-side power supply output with
four wake-up inputs, programmable window watchdog, interrupt, reset, SPI
input control, and a high-speed CAN transceiver compatible with CAN 2.0 A
and B protocols for module-to-module communication.
DW SUFFIX
CASE 751F-05
28-TERMINAL SOICW
Features
• High-Speed 1.0 Mbps CAN Interface with Bus Diagnostic Capability
(Detection of CANH and CANL Short to Ground, to VDD, and to VSUP)
• Low-Drop Voltage 5.0 V, 200 mA VDD Regulator with Current-Limiting,
Overtemperature Pre-Warning, and Output Monitoring with Reset
• Additional 5.0 V Regulator with External Series Pass Transistor
• Normal, Standby, Stop, and Sleep Modes with Low Sleep and Stop
Mode Current
• 150 mA High-Side Switch Output for Control of External Circuitry
• Four External Wake-Up Inputs
• Software-Programmable Watchdog Window, Interrupt, and Reset
ORDERING INFORMATION
Device
MC33742DW/R2
MC33742SDW/R2
33742 Simplified Application Diagram
VPWR
33742
33742
VDD
5.0 V
MCU
RST
V2
VSUP
V2CTRL
V2
CS
SCLK
MOSI
MISO
SPI
L0
L1
L2
L3
CS
SCLK
MOSI
MISO
WDOG
INT
GND
VPWR
HS
Safe Circuitry
ECU Local
Supply
TXD
CANH
Twisted
RXD
CANL
Pair
CAN Bus
GND
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Motorola, Inc. 2004
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Temperature
Range (TA)
Package
-40°C to 125°C
28 SOICW
Freescale Semiconductor, Inc.
Table 1. Significance Device Differences
Reset Duration
Device Differences
See Page
33742
15 ms (typical)
The duration of the reset mode, in which the RST terminal is asserted low, is 15 ms
typical. Reset mode is entered after device power up, when a VDD undervoltage
condition occurred and if the watchdog register is not properly triggered.
15
33742S
3.5 ms (typical)
The duration of the reset mode, in which the RST terminal is asserted low, is 3.5 ms
typical. Reset mode is entered after device power up, when a VDD undervoltage
condition occurred and if the watchdog register is not properly triggered.
15
Freescale Semiconductor, Inc...
Motorola Part No.
V2CTRL
VSUP
VSUP Monitor
CAN
Dual Voltage Regulator
5.0 V/200 mA Supply
VDD Monitor
HS Control
L0
L2
L3
VDD
Mode Control
Oscillator
HS
L1
V2
Programmable
Wake-Up Input
INT
Interrupt
Watchdog
Reset
WDOG
RST
MOSI
SCLK
MISO
SPI
CS
V2
CANH
CANL
High-Speed 1.0 Mbps
CAN
Physical Interface
TXD
RXD
GND
Figure 1. 33742 Simplified Internal Block Diagram
33742
2
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Freescale Semiconductor, Inc.
RXD
TXD
VDD
1
28
2
27
3
26
RST
INT
4
25
5
24
GND
GND
GND
GND
V2
V2CTRL
VSUP
HS
L0
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
WDOG
CS
MOSI
MISO
SCLK
GND
GND
GND
GND
CANL
CANH
L3
L2
L1
TERMINAL DEFINITIONS
A functional description of each terminal can be found in the System/Application Information section beginning on page 18.
Terminal
Terminal
Name
Formal Name
1
RXD
Receive Data
CAN bus receive data output
2
TXD
Transmit Data
CAN bus transmit data input
3
VDD
Voltage Digital Drain
4
RST
Reset Output
(Active LOW)
This is the device reset output whose main function is to reset the MCU. This terminal
has an internal pull-up current source to VDD
5
INT
Interrupt Output
(Active LOW)
This output is asserted LOW when an enabled interrupt condition occurs. The output
is a push-pull structure.
6–9
20–23
GND
Ground
Ground of the IC. These terminals are connected to the package lead frame in order to
provide a thermal path.
10
V2
Voltage Source 2
Sense input for V2 regulator using external ballast. V2 is also the internal supply for the
CAN cell.
11
V2CTRL
Voltage Source 2 Control
12
VSUP
Voltage Supply
13
HS
High-Side Output
Output of internal high-side switch. Current capability is internally limited to 150 mA.
14–17
L0–L3
Level 0 –3 Inputs
Input interfaces to external circuitry (switched or ICs). Levels at these terminals can be
read by SPI and input can be used as programmable wake-up input in Sleep or Stop
mode.
18
CANH
CAN High
CAN high output.
19
CANL
CAN Low
CAN low output.
24
SCLK
Serial Data Clock
25
MISO
Master In/Slave Out
SPI data sent to MCU. When CS is HIGH, terminal is high impedance.
26
MOSI
Master Out/Slave In
SPI data received by the 33742.
27
CS
Chip Select
(Active LOW)
28
WDOG
Watchdog Output
(Active LOW)
Definition
5.0 V regulator output terminal.
Output driver for the external ballast transistor.
Supply input for the complete device.
Clock input for the Serial Peripheral Interface (SPI) of the device.
Chip select terminal for SPI. When CS is LOW, device is selected.
Output of watchdog circuitry. Terminal is asserted LOW if software watchdog is not
correctly triggered.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
ELECTRICAL RATINGS
V
VSUP
Power Supply Voltage at VSUP Terminal
Continuous (Steady-State)
-0.3 to 27
Transient Voltage (Load Dump)
-0.3 to 40
VLOG
-0.3 to VDD + 0.3
V
IDD
Internally Limited
A
Voltage
VHS
-0.3 to VSUP + 0.3
V
Output Current
IHS
Internally Limited
A
Logic Inputs (RXD, TXD, MOSI, MISO, CS, SCLK, RST, WDOG, and INT
Terminals)
Output Current at VDD Terminal
Freescale Semiconductor, Inc...
HS Terminal
VESD1
ESD Voltage, Human Body Model (Note 1)
V
HS, L0, L1, L2, L3, CANH, CANL Terminals
±4000
All Other Terminals
±2000
VESD2
±200
DC Input Voltage
VDCIN
-0.3 to 40
V
DC Input Current
IDCIN
±2.0
mA
VTRINEC
±100
V
PD
1.0
W
Continuous Voltage
VCANH/L
-27 to 40
V
Continuous Current
ICANH/L
200
mA
CANH and CANL Transient Voltage (Load Dump) (Note 5)
VLDH/L
40
V
CANH and CANL Transient Voltage (Note 6)
VTRH/L
±40
V
ESD Voltage, Machine Model (Note 2)
V
L0, L1, L2, L3 Terminals
Transient Input Voltage with External Component (Note 3)
Power Dissipation (Note 4)
CANL and CANH Terminals
Notes
1. ESD1 testing is performed in accordance with the Human Body Model (CZAP =100 pF, RZAP =1500 Ω).
2.
ESD2 testing is performed in accordance with the Machine Model (CZAP =200 pF, RZAP =0 Ω).
3.
4.
Testing in accordance with ISO 7637-1. See also Figure 2.
Maximum power dissipation at 85°C ambient temperature in free air with no heatsink, according to JEDEC JESD51-2 and JESD51-3
specifications.
Load dump test in accordance with ISO 7637-1.
Transient test in accordance with ISO 7637-1. See also Figure 3.
5.
6.
33742
33742
1.0 nF
1.0 nF
Lx
10 kΩ
GND
Transient Pulse
Generator
(Note)
GND
Note Waveform per ISO 7637-1. Test Pulses 1, 2, 3a, and 3b.
Figure 2. ISO 7637 Test Setup for L0:L3 Inputs
33742
4
CANH
Transient Pulse
Generator
(Note)
CANL
GND
1.0 nF
GND
Note Waveform per ISO 7637-1. Test Pulses 1, 2, 3a, and 3b.
Figure 3. ISO 7637 Test Setup for CANH/CANL
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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MAXIMUM RATINGS (continued)
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
Ambient
TA
-40 to 125
Junction
TJ
-40 to 150
Storage Temperature
TSTG
-55 to 165
°C
Thermal Resistance Junction to GND Terminals
RθJG
20
°C/W
T SOLDER
240
°C
THERMAL RATINGS
°C
Operating Temperature
Freescale Semiconductor, Inc...
Peak Package Reflow Temperature During Solder Mounting (Note 7)
Notes
7. Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits
may cause malfunction or permanent damage to the device.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.75 V ≤ V2 ≤ 5.25 V, 5.5 V ≤ VSUP ≤ 18 V, and -40°C ≤ TA ≤ 125°C. Typical values noted
reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
VSUP
5.5
–
18
V
Full Functionality (Note 8)
18
–
27
Reduced Functionality (Note 9)
4.5
–
5.5
VSUP TERMINAL
Nominal DC Supply Voltage
VSUP-EX
Freescale Semiconductor, Inc...
Extended DC Voltage
V
Input Voltage During Load Dump
VSUP-LD
–
–
40
V
Input Voltage During Jump Start
VSUP-JS
–
–
27
V
Supply Current in Standby Mode (Note 10) (IOUT at VDD = 10 mA,
CAN Recessive or Sleep Mode)
mA
ISUP(STDBY)
TA ≥ 25°C
–
12
15
TA = - 40°C to 25°C
–
14.5
19
Supply Current in Normal Mode (Note 10) (IOUT at VDD = 10 mA,
CAN Recessive or Sleep Mode)
mA
ISUP(NORM)
TA ≥ 25°C
–
12.4
15
TA = - 40°C to 25°C
–
15
19
Supply Current in Sleep Mode (Note 10) [VDD and V2 OFF, CAN in Sleep
Mode with CAN Wake-Up Disabled (Note 11)]
µA
ISUP(SLP-WD)
VSUP < 13.5 V, Oscillator Running (Note 12)
–
85
105
VSUP < 13.5 V, Oscillator Not Running (Note 13)
–
53
80
VSUP = 18 V, Oscillator Running (Note 12)
–
110
140
Supply Current in Sleep Mode (Note 10) [VDD and V2 OFF, VSUP < 13.5 V,
Oscillator Not Running (Note 13), CAN in Sleep Mode with Wake-Up Enabled]
µA
ISUP(SLP-WE)
TA = -40°C
–
80
–
TA = 25°C
–
65
–
TA = 125°C
–
55
–
Supply Current in Stop Mode (Note 10) [IOUT at VDD < 2.0 mA, VDD ON, CAN
in Sleep Mode with Wake-Up Disabled (Note 11)
VSUP < 13.5 V, Oscillator Running (Note 12)
µA
ISUP(STOP-WD)
–
–
160
VSUP < 13.5 V, Oscillator Not Running (Note 13)
–
80
160
VSUP = 18 V, Oscillator Running (Note 12)
–
100
210
Notes
8. All functions and modes available and operating. Watchdog, HS turn ON/turn OFF, CAN cell operating, L0:L3 inputs operating, SPI read/
write operation. Overtemperature may occur.
9. VDD > 4.0 V, RST HIGH if reset 2 selected by SPI, logic terminal high level reduced, device is functional.
10.
Current measured at VSUP terminal.
11.
If CAN cell is Sleep-Enabled for wake-up, an additional current (ICAN-SLEEP) must be added to specified value.
12.
13.
Oscillator running means one of the following function is active: Forced Wake-Up or Cyclic Sense or Software Watchdog in Stop mode.
Oscillator not running means none of the following functions are active: Forced Wake-Up and Cyclic Sense and Software Watchdog in Stop
mode.
33742
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.75 V ≤ V2 ≤ 5.25 V, 5.5 V ≤ VSUP ≤ 18 V, and -40°C ≤ TA ≤ 125°C. Typical values noted
reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
VSUP TERMINAL (continued)
Supply Current in Stop Mode (Note 14) [IOUT at VDD < 2.0 mA, VDD ON,
VSUP < 13.5 V, Oscillator Not Running (Note 15), CAN in Sleep Mode with
Wake-Up Enabled]
TA = -40°C
–
100
–
TA = 25°C
–
92
–
TA = 125°C
–
80
–
VBF
1.5
3.0
4.0
V
BATFAIL Flag Hysteresis (Note 16)
VBF(HYS)
–
1.0
–
V
Battery Fall Early Warning Threshold
VBF(EW)
BATFAIL Flag Internal Threshold
Freescale Semiconductor, Inc...
µA
ISUP(STOP-WE)
V
In Normal and Standby Modes
5.3
5.8
6.3
0.1
0.2
0.3
VBF(EW-HYST)
Battery Fall Early Warning Hysteresis
V
In Normal and Standby Modes (Note 16)
VDD TERMINAL (Note 17)
VDD Output Voltage (2.0 mA < IDD < 200 mA)
V
VDDOUT
5.5 V < VSUP < 27 V
4.9
5.0
5.1
4.5 V < VSUP < 5.5 V
4.0
–
–
–
0.2
0.5
–
0.1
0.25
200
285
350
160
–
200
125
–
160
20
–
40
VDDDRP1
Dropout Voltage
V
IDD = 200 mA
Dropout Voltage, Limited Output Current and Low VSUP
VDDDRP2
V
IDD = 50 mA, 4.5 V < VSUP
IDD
VDD Output Current
Internally Limited
mA
TSD
Thermal Shutdown (Junction)
Normal or Standby Mode
°C
TPW
Overtemperature Pre-Warning (Junction)
VDDTEMP Bit Set
°C
TSD - TPW
Temperature Threshold Difference
RST Threshold, Selectable by RSTTH Bit in SPI Register RCR
VRSTTH
V
Threshold 1, Default Value after Reset, RSTTH Bit set to 0
4.5
4.6
4.7
Threshold 2, RSTTH bit Set to 1
4.0
4.2
4.3
1.0
–
VRSTTH
VDD for Reset Active
VDDR
°C
V
Notes
14. Current measured at VSUP terminal.
15.
16.
17.
Oscillator not running means none of the following functions are active: Forced Wake-Up and Cyclic Sense and Software Watchdog in Stop
mode.
Guaranteed by design; however, it is not production tested.
IDD is the total regulator output current. VDD specification with external capacitor. Stability requirement: Capacitance > 47 µF, ESR < 1.3 Ω
(tantalum capacitor). In Reset, Normal Request, Normal and Standby modes. Measures with capacitance = 47 µF tantalum.
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.75 V ≤ V2 ≤ 5.25 V, 5.5 V ≤ VSUP ≤ 18 V, and -40°C ≤ TA ≤ 125°C. Typical values noted
reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
9.0 V < VSUP < 18 V
–
5.0
25
5.5 V < VSUP < 27 V
–
10
25
Unit
VDD TERMINAL (continued) (Note 18)
Line Regulation (IDD = 10 mA, Capacitance = 47 µF Tantalum at VDD)
Load Regulation (Capacitance = 47 µF Tantalum at VDD)
VLD
1.0 mA < IDD < 200 mA
mV
–
25
75
–
30
50
VTHERM-S
Thermal Stability
Freescale Semiconductor, Inc...
mV
VLR
VSUP = 13.5 V, IDD = 100 mA (Note 19)
mV
VDD TERMINAL IN STOP MODE (Note 18)
VDDSTOP
VDD Output Voltage
V
4.75
5.0
5.25
4.75
5.0
5.25
10
17
25
Selectable by SPI, Default Value after Reset, Bit Value 0
4.5
4.6
4.7
Selectable by SPI, Bit Value 1
4.1
4.2
4.3
IDD ≤ 2.0 mA
IDD ≤ 10 mA
IDDS-WU
IDD Output Current to Wake-Up
V
VRST-STOP
Reset Threshold
Line Regulation (Capacitance = 47 µF Tantalum at VDD)
VLR-STOP
5.5 V < VSUP < 27 V, IDD = 2.0 mA
Load Regulation (Capacitance = 47 µF Tantalum at VDD)
mV
–
5.0
25
–
15
75
VLD-STOP
1.0 mA < IDD < 10 mA
mA
mV
V2 TRACKING VOLTAGE REGULATOR (Note 20)
V2 Output Voltage (Capacitance = 10 µF Tantalum at V2)
V2
2.0 mA ≤ I2 ≤ 200 mA, 5.5 V < VSUP < 27 V
I2 Output Current (for Information Only)
1.0
1.01
200
–
–
0
–
10
3.75
4.0
4.25
mA
I2CTRL
Worst Case at TJ = 125°C
V2LOW Flag Threshold
0.99
I2
Depending on External Ballast Transistor
V2 Control Drive Current Capability (Note 21)
VDD
V2LTH
mA
V
Notes
18. IDD is the total regulator output current. VDD specification with external capacitor. Stability requirement: capacitance > 47 µF, ESR < 1.3 Ω
(tantalum capacitor). In Reset, Normal Request, Normal and Standby modes, measures with capacitance = 47 µF tantalum.
19. Guaranteed by characterization and design; however, it is not production tested.
20. V2 specification with external capacitor. Stability requirement: capacitance > 42 µF and ESR < 1.3 Ω (tantalum capacitor), external resistor
between base and emitter required. Measurement conditions: ballast transistor MJD32C, capacitance > 10 µF tantalum, 2.2 kΩ resistor
between base and emitter of ballast transistor.
21. Guaranteed current capability of the V2CTRL terminal is 10 mA. Current may be higher. No active limitation is provided.
33742
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.75 V ≤ V2 ≤ 5.25 V, 5.5 V ≤ VSUP ≤ 18 V, and -40°C ≤ TA ≤ 125°C. Typical values noted
reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
0
–
1.0
VDD - 0.9
–
VDD
-2.0
–
2.0
Unit
LOGIC OUTPUT TERMINAL (MISO) (Note 22)
VOL
Low-Level Output Voltage
V
IOUT = 1.5 mA
VOH
High-Level Output Voltage
IOUT = -250 µA
V
µA
IHZ
Tri-Stated MISO Leakage Current
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0 V < VMISO < VDD
LOGIC INPUT TERMINALS (MOSI, SCLK, CS)
High-Level Input Voltage
VIH
0.7 VDD
–
VDD + 0.3
V
Low-Level Input Voltage
VIL
-0.3
–
0.3 VDD
V
High-Level Input Current on CS
I IH
-100
–
-20
-100
–
-20
-10
–
10
-300
-250
-150
IO = 1.5 mA, 5.5 V < VSUP < 27 V
0
–
0.9
IO = 0 mA, 1.0 V <VSUP < 5.5 V
0
–
0.9
µA
VI = 4.0 V
µA
I IL
Low-Level Input Current on CS
VI = 1.0 V
µA
I IN
MOSI and SCLK Input Current
0 V < VIN < VDD
RST OUTPUT TERMINAL (Note 23)
µA
IOH
High-Level Output Current
0 V < VOUT < 0.7 VDD
V
VOL
Low-Level Output Voltage
IPDW
RST Pulldown Current
mA
V > 0.9 V
2.3
–
5.0
0
–
0.9
WDOG OUTPUT TERMINAL (Note 24)
V
VOL
Low-Level Output Voltage
IO = 1.5 mA, 1.0 V < VSUP < 27 V
V
VOH
High-Level Output Voltage
IO = -250 µA
VDD -0.9
–
VDD
0
–
0.9
VDD -0.9
–
VDD
INT OUTPUT TERMINAL (Note 24)
V
VOL
Low-Level Output Voltage
IO = 1.5 mA
V
VOH
High-Level Output Voltage
IO = -250 µA
Notes
22. Push-pull structure with tri-state condition (CS HIGH).
23. Output terminal only. Supply from VDD. Structure switch to ground with pullup current source.
24.
Push-pull structure.
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.75 V ≤ V2 ≤ 5.25 V, 5.5 V ≤ VSUP ≤ 18 V, and -40°C ≤ TA ≤ 125°C. Typical values noted
reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
HS OUTPUT TERMINAL
TJ = 25°C, IOUT - 150 mA, VSUP > 9.0 V
–
2.0
2.5
TA = 125°C, IOUT - 150 mA, VSUP > 9.0 V
–
–
4.5
TA = 125°C, IOUT - 120 mA, 5.5 V < VSUP < 9.0 V
–
3.5
5.5
ILIM
Output Current Limitation
mA
160
–
500
TSD
155
–
190
°C
ILEAK
–
–
10
µA
-1.5
–
-0.3
5.5 V < VSUP < 6.0 V
2.0
2.5
3.0
6.0 V < VSUP < 18 V
2.5
3.0
3.6
18 V < VSUP < 27 V
2.7
3.2
3.7
VSUP - VHS > 1.0 V
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Ω
RDS(ON)
Driver Output ON Resistance
HS Thermal Shutdown
HS Leakage Current
VCL
Output Clamp Voltage
IOUT = -10 mA, No Inductive Load Drive Capability
V
L0, L2, L2, AND L3 INPUT TERMINALS
VTHN
Negative Switching Threshold
V
VTHP
Positive Switching Threshold
V
5.5 V < VSUP < 6.0 V
2.7
3.3
3.8
6.0 V < VSUP < 18 V
3.0
4.0
4.6
18 V < VSUP < 27 V
3.5
4.2
4.7
–
1.3
-10
–
10
VHYST
Hysteresis
V
0.6
5.5 V < VSUP < 27 V
µA
I IN
Input Current
-0.2 V < VIN < 40 V
CAN SUPPLY
Supply Current of CAN Cell
CAN in Normal Mode, Bus Recessive State
IRES
–
1.3
3.0
mA
CAN in Normal Mode, Bus Dominant State without Bus Load
IDOM
–
1.5
3.5
mA
ICAN-SLEEP
–
12
24
µA
IDIS
–
–
1.0
µA
CAN in Sleep State, Wake-Up Enabled, V2 Regulator OFF
CAN in Sleep State, Wake-Up Disabled, V2 Regulator OFF (Note 25)
Notes
25. Guaranteed by design; however, it is not production tested.
33742
10
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.75 V ≤ V2 ≤ 5.25 V, 5.5 V ≤ VSUP ≤ 18 V, and -40°C ≤ TA ≤ 125°C. Typical values noted
reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
VCM
-27
–
40
V
Recessive State at RXD
–
–
500
Dominant State at RXD
900
–
–
VHYST
100
–
–
mV
RIN
5.0
–
100
kΩ
RIND
10
–
100
kΩ
TXD Dominant State
2.75
–
4.5
TXD Recessive State
–
–
3.0
CANH AND CANL TERMINALS
Bus Terminals Common Mode Voltage
Differential Input Voltage (Common Mode Between -3.0 V and 7.0 V)
Differential Input Hysteresis (RXD)
Freescale Semiconductor, Inc...
Input Resistance
Differential Input Resistance
VCANH - VCANL
mV
VCANH
CANH Output Voltage
V
VCANL
CANL Output Voltage
V
TXD Dominant State
0.5
–
2.25
TXD Recessive State
2.0
–
–
TXD Dominant State
1.5
–
3.0
V
TXD Recessive State
–
–
100
mV
CANH
ICANH
–
–
-35
CANL
ICANL
35
–
–
TSD
160
180
–
CANL
ICANL/OC
60
–
200
CANH
ICANH/OC
-200
–
-60
VoH -VoL
Differential Output Voltage
mA
Output Current Capability (Dominant State)
Overtemperature Shutdown
°C
mA
CANL Overcurrent Detection (Note 26)
CANH and CANL Input Current, Device Supplied (CAN Sleep Mode with
CAN Wake-Up Enabled or Disabled)
VCANH, VCANL from 0 V to 5.0 V
VCANH, VCANL = -2.0 V
VCANH, VCANL = 7.0 V
CANH and CANL Input Current, Device Unsupplied
µA
ICAN1
–
3.0
-60
-50
10
–
–
60
75
–
40
100
µA
ICAN2
VCANH, VCANL = 2.5 V
VCANH, VCANL = -2.0 V
-60
-50
–
VCANH, VCANL = 7.0 V
–
190
240
Notes
26. Reported in CAN register. For a description of the contents of the CAN register, refer to CAN Register (CAN) on page 40.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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11
Freescale Semiconductor, Inc.
STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.75 V ≤ V2 ≤ 5.25 V, 5.5 V ≤ VSUP ≤ 18 V, and -40°C ≤ TA ≤ 125°C. Typical values noted
reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
CANL to GND Threshold
VLG
–
1.75
–
V
CANH to GND Threshold
VHG
–
1.75
–
V
CANL to VSUP Threshold
VLVB
–
VSUP - 2.0
–
V
CANH to VSUP Threshold
VHVB
–
VSUP - 2.0
–
V
CANL to VDD Threshold
VL5
–
VDD - 0.43
–
V
CANH to VDD Threshold
VH5
–
VDD - 0.43
–
V
Freescale Semiconductor, Inc...
CANH AND CANL DIAGNOSTIC INFORMATION
RXD Weak Pulldown Current Source (Note 27)
µA
IRXDW
RXD Permanent Dominant Failure Condition
–
100
–
TXD AND RXD TERMINALS
TXD Input High Voltage
VIH
0.7 VDD
–
VDD + 0.4
V
TXD Input Low Voltage
VIL
-0.4
–
0.3 VDD
V
TXD High-Level Input Current
IIH
-10
–
10
-150
-100
-50
VDD - 1.0
–
–
–
–
0.5
VTXD = V2
µA
µA
IIL
TXD Low-Level Input Current
VTXD = 0 V
VOH
RXD Output High Voltage
IRXD = 250 µA
V
V
VOL
RXD Output Low Voltage
IRXD = 1.0 mA
Notes
27. Guaranteed by design; however, it is not production tested.
33742
12
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Freescale Semiconductor, Inc.
DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.75 V ≤ V2 ≤ 5.25 V, 5.5 V ≤ VSUP ≤ 18 V, and -40°C ≤ TA ≤ 125°C. Typical values noted
reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SPI Operation Frequency
f REQ
0.25
–
4.0
MHz
SCLK Clock Period
t PCLK
250
–
N/A
ns
SCLK Clock High Time
t WSCLKH
125
–
N/A
ns
SCLK Clock Low Time
t WSCLKL
125
–
N/A
ns
Falling Edge of CS to Rising Edge of SCLK
t LEAD
100
–
N/A
ns
Falling Edge of SCLK to Rising Edge of CS
t LAG
100
–
N/A
ns
MOSI to Falling Edge of SCLK
t SISU
40
–
N/A
ns
Falling Edge of SCLK to MOSI
t SIH
40
–
N/A
ns
MISO Rise Time (Note 29)
t RSO
–
25
50
–
25
50
Freescale Semiconductor, Inc...
DIGITAL INTERFACE TIMING (Note 28)
ns
CL = 220 pF
t FSO
MISO Fall Time (Note 29)
ns
CL = 220 pF
ns
Time from Falling or Rising Edges of CS
MISO Low Impedance
t SOEN
–
–
50
MISO High Impedance
t SODIS
–
–
50
–
–
50
18
–
34
Time from Rising Edge of SCLK to MISO Data Valid
t VALID
ns
0.2 VDD ≤ MISO ≥ 0.8 VDD, CL = 200 pF
STATE MACHINE TIMING
Delay Between CS LOW-to-HIGH Transition (at End of SPI Stop Command)
and Stop Mode Activation (Note 30)
µs
t CS-STOP
µs
t INT
Interrupt Low-Level Duration
Stop Mode
Internal Oscillator Frequency (Note 31)
f OSC
Watchdog Period Normal and Standby Modes
t WD
7.0
10
13
–
100
–
ms
Period 1
8.58
9.75
10.92
Period 2
39.6
45
50.4
Period 3
88
100
112
Period 4
308
350
392
Notes
28.
29.
30.
31.
kHz
See Figure 4, SPI Timing Diagram, page 17.
Not production tested. Guaranteed by design.
Not production tested. Guaranteed by design. Detected by V2 OFF.
f OSC is indirectly measured (1.0 ms reset) and trimmed.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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13
Freescale Semiconductor, Inc.
DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.75 V ≤ V2 ≤ 5.25 V, 5.5 V ≤ VSUP ≤ 18 V, and -40°C ≤ TA ≤ 125°C. Typical values noted
reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
308
350
392
Period 1
6.82
9.75
12.7
Period 2
31.5
45
58.5
Period 3
70
100
130
Period 4
245
350
455
Normal and Standby Modes
-12
–
12
Stop Mode
-30
–
30
Timing 1
3.22
4.6
5.98
Timing 2
6.47
9.25
12
Timing 3
12.9
18.5
24
Timing 4
25.9
37
48.1
Timing 5
51.8
74
96.2
Timing 6
66.8
95.5
124
Timing 7
134
191
248
Timing 8
271
388
504
200
350
500
-30
–
30
–
–
–
–
9.0
–
22
9.0
–
22
Unit
STATE MACHINE TIMING (continued)
t NRTOUT
Normal Request Mode Timeout
Normal Request Mode
t WD-STOP
Freescale Semiconductor, Inc...
Watchdog Period Stop Mode
ms
f ACC
Watchdog Period Accuracy
Cyclic Sense/FWU Timing Sleep and Stop Modes
%
t CSFWU
ms
µs
t ON
Cyclic Sense ON Time
Sleep and Stop Modes.
t ACC
Cyclic Sense/FWU Timing Accuracy
Sleep and Stop Modes
Delay Between SPI Command and HS Turn ON (Note 32)
t S-HSON
Normal or Standby Mode, VSUP > 9.0 V
Delay Between SPI Command and HS Turn OFF (Note 32)
t S-HSOFF
Normal or Standby Mode, VSUP > 9.0 V
Delay Between SPI and V2 Turn ON (Note 32)
Delay Between SPI and V2 Turn OFF (Note 32)
µs
22
µs
µs
µs
15
35
70
–
–
10
µs
t S-CAN_N
Normal Mode (Note 33)
Delay Between SPI and CAN Sleep Mode (Note 32)
22
t S-NR2N
Normal Request Mode
Delay Between SPI and CAN Normal Mode (Note 32)
µs
t S-V2OFF
Normal Mode
Delay Between Normal Request and Normal Mode After Watchdog Trigger
Command (Note 32)
%
t S-V2ON
Standby Mode
Normal Mode (Note 33)
ms
µs
t S-CAN_S
–
–
10
Notes
32. Delay starts at falling edge of clock cycle #8 of the SPI command and start of “Turn ON” or “Turn OFF” of HS or V2.
33. Guaranteed by design; however, it is not production tested.
33742
14
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.75 V ≤ V2 ≤ 5.25 V, 5.5 V ≤ VSUP ≤ 18 V, and -40°C ≤ TA ≤ 125°C. Typical values noted
reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
STATE MACHINE TIMING (continued)
Delay Between CS Wake-Up (CS LOW to HIGH) and Device in Normal
Request Mode (VDD ON and RST HIGH)
15
Stop Mode
Delay Between CS Wake-Up (CS LOW to HIGH) and First Accepted SPI
Command
40
90
µs
t W-SPI
90
–
N/A
20
–
N/A
25
–
–
4.0
–
30
tIDD-DGLT
40
55
75
33742
t RSTDUR
12
15
18
33742S
t RSTDURS
3.0
3.5
4.0
t WUF
8.0
20
38
Device in Stop Mode After Wake-Up
Delay Between INT Pulse and First SPI Command Accepted
Freescale Semiconductor, Inc...
µs
t W-CS
Device in Stop Mode After Wake-Up
Delay Between Two SPI Messages Addressing the Same Register
µs
t S-1STSPI
t 2SPI
µs
VDD TERMINAL
µs
tD
Reset Delay Time
Measured at 50% of Reset Signal
IDD Overcurrent to Wake-Up Deglitcher Time (Note 34)
µs
RST TERMINAL
ms
Reset Duration After VDD HIGH
L0, L2, L2, AND L3 INPUT TERMINALS
Wake-Up Filter Time
µs
Notes
34. Guaranteed by design; however, it is not production tested.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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15
Freescale Semiconductor, Inc.
DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.75 V ≤ V2 ≤ 5.25 V, 5.5 V ≤ VSUP ≤ 18 V, and -40°C ≤ TA ≤ 125°C. Typical values noted
reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
t DOUT
200
360
520
µs
Slew Rate 3
60
100
210
Slew Rate 2
70
110
225
Slew Rate 1
80
130
255
Slew Rate 0
110
200
310
Slew Rate 3
20
65
110
Slew Rate 2
25
80
150
Slew Rate 1
35
100
200
Slew Rate 0
50
160
300
10
50
140
Slew Rate 3
100
150
200
Slew Rate 2
120
165
220
Slew Rate 1
140
200
250
Slew Rate 0
250
340
410
Slew Rate 3
60
125
150
Slew Rate 2
65
150
190
Slew Rate 1
75
180
250
Slew Rate 0
200
310
460
t RDR
20
30
60
Slew Rate 3
t SL3
4.0
19
40
Slew Rate 2
t SL2
3.0
13.5
20
Slew Rate 1
t SL1
2.0
8.0
15
Slew Rate 0
t SL0
1.0
5.0
10
CAN MODULE TIMING
Dominant State Timeout
Propagation Loop Delay TXD to RXD (Recessive to Dominant) (Note 35)
Freescale Semiconductor, Inc...
Propagation Delay TXD to CAN (Recessive to Dominant) (Note 36)
t LRD
t TRD
Propagation Delay CAN to RXD (Recessive to Dominant) (Note 37)
t RRD
Propagation Loop Delay TXD to RXD (Dominant to Recessive) (Note 35)
t LDR
Propagation Delay TXD to CAN (Dominant to Recessive) (Note 36)
Propagation Delay CAN to RXD (Dominant to Recessive) (Note 37)
ns
ns
ns
ns
t TDR
ns
ns
V/µs
Non-Differential Slew Rate (CANL or CANH)
Notes
35. See Figure 5, page 17.
36. See Figure 6, page 17.
37. See Figure 7, page 17.
33742
16
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Timing Diagrams
t PCLK
CS
t WSCLKH
t LEAD
t LAG
SCLK
t WSCLKL
Freescale Semiconductor, Inc...
t SISU
MOSI
Undefined
t SIH
Di 8
Don’t Care
Di 0
t VALID
t SODIS
t SOEN
MISO
Don’t Care
Do 0
Do 8
Note Incoming data at MOSI terminal is sampled by the 33742 at SCLK falling edge. Outgoing data at MISO terminal
is set by the 33742 at SCLK rising edge (after t VALID delay time).
Figure 4. SPI Timing Diagram
tLRD
TX
tRDR
0.9 V
2.0 V
VDIFF
0.8 V
tRRD
tLDR
2.0 V
RX
2.0 V
RX
0.8 V
0.5 V
0.8 V
Figure 7. Propagation Delay CAN to RXD
Figure 5. Propagation Loop Delay TXD to RXD
tTRD
TX
0.8 V
VDIFF
2.0 V
tTDR
0.9 V
0.5 V
Figure 6. Propagation Delay TXD to CAN
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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17
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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
Freescale Semiconductor, Inc...
The 33742 and the 33742S are integrated circuits dedicated
to automotive applications. Their functions include the
following:
• One fully protected voltage regulator with 200 mA total
output current capability available at the VDD terminal.
• Driver for external pass transistor for V2 regulator
function.
• VDD regulator undervoltage reset function, programmable
window or timeout software watchdog function.
• Two running modes: Normal and Standby modes when
the microcontroller is running.
• Sleep and Stop modes for operation in low power mode to
reduce the application current consumption, while offering
wake-up capability from CAN interface, L3:L0 wake-up
input, and automatic timer wake-up.
• Programmable wake-up input and cyclic sense wake-up.
• CAN high-speed physical interface with bus failure
diagnostic and enhanced protection feature for TXD and
RXD failure.
• Interface with micro through SPI. Interrupt output to report
device status, diagnostic, and wake-up event.
FUNCTIONAL TERMINAL DESCRIPTION
RXD and TXD
V2
The RXD and TXD terminals (receive data terminal and
transmit data terminal, respectively) are connected to the
microcontroller CAN protocol handler. TXD is an input and
controls the CANH and CANL line state (dominant when TXD is
LOW, recessive when TXD is HIGH). RXD is an output and
reports the bus state (RXD LOW when CAN bus is dominant,
HIGH when CAN bus is recessive).
The V2 terminal is the input sense of the V2 regulator. It is
connected to the external ballast transistor. V2 is also the 5.0 V
supply of the internal CAN interface. It is possible to connect V2
to an external 5.0 V regulator or to the VDD output when no
external ballast transistor is used. In this case, the V2CTRL
terminal must be left open. Refer to Figure 28, 33742 Typical
Application Schematic, page 46.
VDD
V2CTRL
The VDD terminal is the output terminal of the 5.0 V internal
regulator. It can deliver up to 200 mA. This output is protected
against overcurrent and overtemperature. It includes an
overtemperature pre-warning flag, which is set when the
internal regulator temperature exceeds 130°C typical. When
the temperature exceeds the overtemperature shutdown
(170°C typical), the regulator is turned off.
The V2CTRL terminal is the output drive of the V2 regulator
connected to the external ballast transistor.
VDD includes an undervoltage reset circuitry, which sets the
RST terminal LOW when VDD is below the undervoltage reset
threshold.
VSUP
The VSUP terminal is the battery supply input of the device.
HS
The HS terminal is the internal high-side driver output. It is
internally protected against overcurrent and overtemperature.
RST
L0, L1, L2, and L3
The Reset terminal RST is an output that is set LOW when
the device is in reset mode. The RST terminal is set HIGH when
the device is not in reset mode. RST includes an internal pullup
current source. When RST is LOW, the sink current capability is
limited, allowing RST to be shorted to 5.0 V for software debug
or software download purposes.
The L0:L3 input terminals can be connected to external
switches or any IC’s output. The state of the inputs can be read
by SPI. Theses inputs can be used as wake-up events when the
device is set in Sleep or Stop mode.
INT
The CAN High and CAN Low terminals are the interfaces to
the CAN bus lines. They are controlled by TXD input level, and
the state of CANH and CANL is reported through RXD output.
A 60 Ω impedance termination is connected between CANH
and CANL.
The Interrupt terminal INT is an output that is set LOW when
an interrupt occurs. INT is enabled using the Interrupt Register
(INTR). When INT occurs, INT stays LOW until the INT source
is cleared.
CANH and CANL
INT output also reports a wake-up event by a 10 µs typical
pulse when the device is in stop mode.
33742
18
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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SCLK
MOSI
This is the Serial Data Clock terminal of the serial peripheral
interface.
This is the Master Out/Slave In terminal of the serial
peripheral interface. Control data from the microcontroller are
received through this terminal.
MISO
This is the Master In/Slave Out terminal of the serial
peripheral interface. Data are send from the device to the
microcontroller through MISO terminal.
CS
This is the device Chip Select terminal of the serial peripheral
interface. When this terminal is LOW, the internal serial
peripheral interface of the device is selected.
WDOG
Freescale Semiconductor, Inc...
The Watchdog terminal is used to signal that a software
watchdog has not been properly triggered.
DEVICE OPERATION
Power Supply
The 33742 is supplied from the battery line through the VSUP
terminal. An external diode is required to protect against
negative transients and reverse battery. The 33742 can operate
from 4.5 VDC and under jump-start conditions at 27 VDC.
The VSUP terminal sustains standard automotive voltage
conditions such as load dump at 40 V. When VSUP falls below
3.0 V typical, the 33742 detects it and stores the information in
the Mode Control Register (MCR) bit BATFAIL. Detection is
available in all operation modes.
Note For a detailed description of all the registers
mentioned in this section, refer to the section titled SPI
INTERFACE AND REGISTER DESCRIPTION beginning on
page 38.
The 33742 incorporates a battery early warning function,
which provides a maskable interrupt when the VSUP voltage is
below 6.0 V typical. A hysteresis is included. Operation is only
in Normal and Standby modes. VSUP LOW is reported in the
Input/Output Register (IOR).
VDD Regulator
The VDD regulator is a 5.0 V output with output current
capability up to 200 mA. It includes a voltage monitoring
circuitry associated with an undervoltage reset function. The
VDD regulator is fully protected against overcurrent and short
circuit. It has overtemperature detection warning flags (bit
VDDTEMP in the MCR and INTR registers) and
overtemperature shutdown with hysteresis.
V2 Regulator
V2 regulator circuitry is designed to drive an external pass
transistor increasing output current flexibility. Two terminals, V2
and V2CTRL, are used to achieve the flexibility. Output voltage
is 5.0 V and is realized by a tracking function of the VDD
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
regulator. The recommended ballast transistor is MJD32C.
Other transistors can be used, however. Depending on the PNP
transistor gain, an external resistor-capacitor network might be
connected. V2 is the supply input for the CAN cell. The state of
V2 is reported in the IOR register (bit V2LOW set to logic [1] if
V2 is below 4.0 V typical).
HS VSUP Switch Output
HS output is a 2.0 Ω typical switch from VSUP terminal. It
allows the supply of external switches and their associated
pullup or pulldown circuitry, in conjunction, for example, with the
wake-up input terminals L0:L3. Output current is limited to
200 mA and HS is protected against short circuit and has an
overtemperature shutdown (bit HSOT in the IOR register and bit
HSOT-V2LOW in the INTR register).
HS output is controlled by the bit HSON in the IOR register.
Thanks to an internal timer, HS can be activated at regular
intervals in Sleep and Stop modes. It can also be permanently
turned on in Normal or Standby modes to drive loads or supply
peripheral components. No internal clamping protection circuit
is implemented; thus dedicated external protection circuitry is
required in case of inductive load drive. HS negative voltage
should not go below -0.3 V.
Battery Fail Early Warning
Refer to the discussion under the heading Power Supply,
above.
Internal Clock
The 33742 has an internal clock used to generate all timings
(reset, watchdog, cyclic wake-up, filtering time, etc.). Two
oscillators are implemented. A high-accuracy (±12 percent)
oscillator used in Normal Request, Normal, and Standby
modes, and a low-accuracy (±30 percent) oscillator used in
Sleep and Stop modes.
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33742
19
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Freescale Semiconductor, Inc.
Functional Modes
Reset Mode
The 33742 has four modes of operation, all controlled by the
SPI. The modes are Standby, Normal, Stop, and Sleep. An
additional temporary mode called Normal Request mode is
automatically accessed by the device after reset or wake-up
from Stop mode. A Reset mode is also implemented. Special
modes and configuration are possible for debug and program
microcontroller flash memory.
In the Reset mode, the RST terminal is LOW and a timer runs
for t RSTDUR time. After t RSTDUR has elapsed, the 33742 enters
Normal Request mode. Reset mode is entered if a reset
condition occurs (VDD LOW, watchdog timeout, or watchdog
trigger in a closed window).
Table 2 below offers a summary of the functional modes.
Normal Request mode is a temporary mode automatically
accessed by the 33742 after the Reset mode or after the 33742
wakes up from Stop mode. After wake-up from the Sleep mode
or after device power-up, the 33742 enters the Reset mode
before entering the Normal Request mode. After a wake-up
from the Stop mode, the 33742 enters the Normal Request
mode directly.
Normal Request Mode
Table 2. Table of Operation
Mode
Voltage Regulator
HS Switch
Wake-Up
Capabilities
(if Enabled)
RST Terminal
INT Terminal
Watchdog
Software
CAN Cell
Normal
Request
VDD: ON,
V2: OFF,
HS: OFF
–
Low for t RSTDUR
time, then HIGH
–
–
–
Normal
VDD: ON,
V2: ON,
HS: Controllable
–
Running
TXD/RXD
Standby
VDD: ON,
V2: OFF,
HS: Controllable
–
Same as Normal
mode
Same as Normal
mode
Running
Low power
Stop
VDD: ON
(Limited Current
Capability),
V2: OFF,
HS:OFF or Cyclic
Sense
CAN, SPI, L0:L3,
Cyclic Sense,
Forced Wake-Up,
IDD Overcurrent
(Note 39)
Normally HIGH.
Active LOW if
WDOG (Note 40)
or VDD
undervoltage occurs
Signal 33742
wake-up and
IDD > IDDS-WU
(not maskable)
Running if enabled.
Not running if
disabled
Low power.
Wake-up capability
if enabled
Sleep
VDD: OFF,
V2: OFF,
HS: OFF or Cyclic
CAN, SPI,
L0:L3, Cyclic Sense
Forced Wake-Up
LOW
Not Active
Not running
Low power.
Wake-up capability
if enabled
Normal
Debug
(Note 38)
Same as Normal
–
Normally HIGH.
Active LOW if VDD
undervoltage occurs
Same as Normal
Not running
Same as Normal
Standby
Debug
(Note 38)
Same as Standby
–
Normally HIGH.
Active LOW if VDD
undervoltage occurs
Same as Standby
Not running
Same as Standby
Stop Debug
(Note 38)
Same as Stop
Same as Stop
Normally HIGH.
Active LOW if VDD
undervoltage occurs
Same as Stop
Not running
Same as Stop
Flash
Programming
Forced externally
–
Not operating
Not operating
Not operating
Not Operating
Normally HIGH.
If enabled, signal
Active LOW if
failure (VDD
WDOG or VDD
Pre-Warning Temp,
CAN, HS)
undervoltage occurs
Notes
38. Mode entered via special sequence described under the heading Debug Mode: Hardware and Software Debug with the 33742 beginning on
page 25.
39. IDD overcurrent always enabled.
40.
33742
20
WDOG if enabled.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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In Normal Request mode, the VDD regulator is ON, the V2
regulator is OFF, and the RST terminal is HIGH. As soon as the
33742 enters the Normal Request mode, an internal 350 ms
timer is started (parameter tNRTOUT). During these 350 ms, the
MCU of the application must address the 33742 via SPI and
configure the TIM1 subregister to select the watchdog period.
This is the condition for the 33742 to stop the 350 ms timer and
go into the Normal or Standby mode and set the watchdog timer
according to the configuration.
Freescale Semiconductor, Inc...
Normal Request Entered and No Watchdog Configuration
Occurs
If the Normal Request mode is entered after the 33742
powers up or after a wake-up from Stop mode, and if no
watchdog configuration occurs while the 33742 is in Normal
Request mode, the 33742 goes into Reset mode after the
350 ms time period has expired before again going into Normal
Request mode. If no watchdog configuration is achieved, the
33742 alternatively goes from Normal Request mode, to Reset
mode, to Normal Request mode, and so on.
If the Normal Request mode is entered after a wake-up from
Sleep mode, and if no watchdog configuration occurs while the
33742 is in Normal Request mode, the 33742 goes back to
Sleep mode.
Normal Mode
In Normal mode, both the VDD and V2 regulators are ON.
This corresponds to the normal application operation. All
functions are available in this mode (watchdog, wake-up input
reading through SPI, HS activation, and CAN communication).
Watchdog software is running and must be periodically cleared
through SPI.
Standby Mode
In Standby mode, only the VDDregulator is ON. The V2
regulator is turned OFF by disabling the V2CTRL terminal. The
CAN interface is not able to send messages. If a CAN message
is received, the CANWU bit is set. Other functions available are
L0:L3 input reading through SPI and HS activation. Watchdog
is running.
Sleep Mode
In Sleep mode, the VDD and V2 regulators are OFF. Current
from the VSUP terminal is reduced. In Sleep mode, the 33742
can be awakened by L0:L3 inputs, by cyclic sense of the L0:L3
inputs, by the automatic forced wake-up timer, and from the
CAN physical interface receiving an incoming CAN message.
When a wake-up occurs, the 33742 goes first into the Reset
mode before entering Normal Request mode.
Stop Mode
The V2 regulator is turned OFF by disabling the V2CTRL
terminal. The VDD regulator is activated in a special low power
mode, allowing the delivery of a few mA. The objective is to
maintain power on the MCU of the application while the MCU is
turned into power-saving condition (i.e, Stop or Wait modes). In
Stop mode, the device supply current from VPWR is very low.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
When the application is in Stop mode (both MCU and
33742), the application can wake up from either the 33742 side
(for example, cyclic sense, forced wake-up, CAN message,
wake-up inputs, and overcurrent on VDD) or the MCU side (key
wake-up, etc.).
Stop mode is always selected by SPI. In Stop mode, the
watchdog software may be either running or not running
depending upon selection by SPI (Reset Control Register
[RCR], bit WDSTOP). To clear the watchdog if it is running, the
33742 must be awakened by the CS terminal (SPI wake-up). In
Stop mode, the 33742 wake-up capability is identical to that in
Sleep mode, with the addition of CS and VDD overcurrent wakeup. Refer to Table 2, page 20.
Application Wake-Up from 33742 Side
When the application is in Stop mode, it can wake up from
the 33742 side. When a wake-up is detected by the 33742 (for
example, CAN, wake-up input), the 33742 turns itself into
Normal Request mode and generates an interrupt pulse at the
INT terminal.
Application Wake-Up from MCU Side
When the application is in Stop mode, the wake-up event
may come from the MCU side. In this case the MCU signals to
the 33742 by a LOW-to-HIGH transition on the CS terminal.
Then the 33742 goes into Normal Request mode and generates
an interrupt pulse at the INT terminal.
Stop Mode Current Monitor
If the VDD output current exceeds an internal threshold
(IDDS-WU), the 33742 goes automatically into Normal Request
mode and generates an interrupt at the INT terminal. The
interrupt is not maskable and the INTR register will have no flag
set.
Interrupt Generation When Wake-Up from Stop Mode
When the 33742 wakes up from Stop mode, it first enters the
Normal Request mode before generating a pulse (10 µs typical)
on the INT terminal. These interrupts are not maskable, and the
wake-up event can be read through the SPI registers, CANWU
bit in the CAN Register (CANR), and LCTRx bit in the Wake-Up
Register (WUR). In case of wake-up from Stop mode
overcurrent or from forced wake-up, no bit is set. After the INT
pulse, the 33742 accepts SPI command after a time delay
(t S-1STSPI).
Watchdog Software in Stop Mode
If watchdog is enabled, the MCU has to wake up
independently of the 33742 before the end of the 33742
watchdog time. In order to do this, the MCU must signal the
wake-up to the 33742 through the SPI wake-up (CS activation).
The 33742 then wakes up and jumps into the Normal Request
mode. The MCU has to configure the 33742 to go to either
Normal or Standby mode. The MCU can then decide to go back
to the Stop mode.
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21
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If no MCU wake-up occurs within the watchdog timing the
33742 activates the RST terminal and jumps into the Normal
Request mode. The MCU can then be initialized.
Stop Mode Enter Command
Stop mode is entered at the end of the SPI message at the
rising edge of the CS. (Refer to the t CS-STOP data in the
Dynamic Electrical Characteristics table on page 13.) Once
Stop mode is entered, the 33742 can wake up from the VDD
regulator overcurrent detection. In order to allow time for the
MCU to complete the last CPU instruction, allowing the MCU to
enter its low power mode, a deglitcher time of 40 µs typical is
implemented.
Figure 8, page 22, depicts the operation of entering the Stop
mode.
Freescale Semiconductor, Inc...
SPI Stop/Sleep
Command
SPI CS
t CS-STOP
33742 in Normal
or Standby mode
t IDD-DGLT
33742 in Stop mode.
No IDD over IDD-DGLT
33742 in Stop mode.
IDD over IDD-DGLT
Figure 8. Entering Stop Mode
RST and WDOG Terminals, Software Watchdog
Operations
Watchdog Software (Selectable Watchdog Window or
Watchdog Timeout)
Watchdog software is used in the 33742 Normal and
Standby modes for monitoring the MCU. Watchdog may be
either watchdog window or watchdog timeout, selectable by
SPI (TIM1 subregister, bit WDW). Default is watchdog window.
The watchdog period may be set from 10 ms to 350 ms
(TIM1 subregister, bits WDT0 and WDT1). When watchdog
window is selected, the closed window is the first part of the
selected period, and the open window is the second part of the
period. (Refer to Timing Register (TIM1/2) beginning on
page 43.)
RST Terminal Description
A reset output is available to reset the MCU. Causes of reset
are the following:
• VDD Falling Out of Range—If VDD falls below the reset
threshold (V RSTTH), the RST terminal is pulled LOW until
VDD returns to the normal voltage.
• Power-ON Reset—At 33742 power-on or wake-up from
Sleep mode, the RST terminal is maintained LOW until
VDD is within its operation range.
• Watchdog Timeout—If watchdog is not cleared, the
33742 will pull the RST terminal LOW for the duration of
the reset time (t RSTDUR).
Watchdog can only be cleared within the open window time.
Any attempt to clear watchdog in the closed window will
generate a reset. Watchdog is cleared through SPI by
addressing the TIM1 subregister.
33742
22
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Freescale Semiconductor, Inc.
Reset and Watchdog Operation
Table 3 describes watchdog and reset output modes of
operation. RST is activated in the event VDD fall or watchdog is
not triggered. WDOG output is active LOW as soon as RST goes
LOW and stays LOW as long as the watchdog is not properly
reactivated by SPI. The WDOG output terminal is a push-pull
structure that can drive external components of the application;
for instance, to signal MCU wrong operation.
Freescale Semiconductor, Inc...
Figure 9 illustrates the device behavior in the event the TIM1
register in not properly accessed. In this case a software reset
occurs, and the WDOG terminal is set LOW until the TIM1
register is properly accessed.
Table 3. Watchdog and Reset Output Operation
WDOG
Events
Output
RST Output
Device Power-Up
LOW to HIGH
LOW to HIGH
VDD Normal,
Watchdog Properly Triggered
HIGH
HIGH
VDD < RSTTH
HIGH
LOW
Watchdog Timeout Reached
LOW (Note 41)
LOW
Notes
41. WDOG stays LOW until the TIM1 register is properly
addressed through SPI.
Watchdog Timeout
VDD
RST
WDOG
Watchdog
Period
SPI
Watchdog Clear
TIM1 register addressed.
SPI CS
Figure 9. RST and WDOG Output Operation
Wake-Up Capabilities
Several wake-up capabilities are available to the 33742
when it is in Sleep or Stop mode. When a wake-up has
occurred, the wake-up event is stored in the Wake-Up Register
(WUR) or the CAN register. The MCU can then access the
wake-up source. The wake-up options are selectable through
SPI while the 33742 is in Normal or Standby mode and prior to
entering low power mode (Sleep or Stop mode). When a wakeup occurs from Sleep mode, the 33742 activates VDD. It
generates an interrupt if wake-up occurs from Stop mode.
Wake-Up from Wake-Up Inputs (L0:L3) Without Cyclic
Sense
The wake-up lines are dedicated to sense the state of
external switches and if changes occur to wake up the MCU (in
Sleep or Stop modes). Wake-up terminals L0:L3 are able to
handle 40 VDC. The internal threshold is 3.0 V typical and
these inputs can be used as an input port expander. The wakeup input states are read through SPI (WUR register).
In order to select and activate direct wake-up from the L0:L3
inputs, the WUR register must be configured with the
appropriate level sensitivity. Additionally, the Low Power
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Control (LPC) Register must be configured with 0xx0 data (bits
LX2HS and HSAUTO are set to 0).
Level sensitivity is selected by the WUR register. Level
sensitivity is configured by L0:L3 input pairs: L0 and L1 level
sensitivity are configured together, while L2 and L3 are
configured together.
Cyclic Sense Wake-Up (Cyclic Sense Timer and Wake-Up
Inputs L0:L3)
The 33742 can wake up upon state change of one of the four
wake-up input lines (L0:L3) while the external pullup or
pulldown resistor of the switches associated with the wake-up
input lines are biased with HS VSUP switch. The HS switch is
activated in Sleep or Stop modes from an internal timer. Cyclic
Sense and Forced Wake-Up are exclusive. If Cyclic Sense is
enabled, Forced Wake-Up cannot be enabled.
In order to select and activate the cyclic sense wake-up from
the L0:L3 inputs, the WUR register must be configured with the
appropriate level sensitivity, and the LPC register must be
configured with 1xx1 data (bit LX2HS set at 1 and bit HSAUTO
set at 1). The wake-up mode selection (direct or cyclic sense) is
valid for all four wake-up inputs.
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33742
23
Freescale Semiconductor, Inc.
Forced Wake-Up
SPI Wake-Up
The 33742 can wake up automatically after a predetermined
time spent in Sleep or Stop mode. Cyclic Sense and Forced
Wake-up are exclusive. If Forced Wake-Up is enabled (FWU bit
set to 1 in the LPC register), Cyclic Sense cannot be enabled.
The 33742 can be awakened by the CS terminal in Sleep or
Stop modes. Wake-up is detected by the CS terminal transition
from LOW to HIGH level. In Stop mode, this corresponds with
the condition where the MCU and the 33742 are in Stop mode
and when the application wake-up event comes through the
MCU.
CAN Interface Wake-Up
33742 Power-Up and 33742 Wake-Up from Sleep Mode
After device or system power-up, or after the 33742 wakes
up from Sleep mode, the 33742 enters into the Reset mode
prior to moving into Normal Request mode.
Figure 10 shows the device state diagram and Figure 11,
page 25, shows device behavior after power-up sequence.
The 33742 can wake up from a CAN message if the CAN
wake-up is enabled. Refer to the section titled CAN BUS
MODULE DESCRIPTION beginning on page 29 for details of
the wake-up detection.
Watchdog: Timeout OR VDD Low
Watchdog: Timeout & Nostop & !BATFAIL
Power
Down
VDD Low OR Watchdog:
Timeout 350 ms & Nostop
g:
Ti
m
eo
ut
O
R
V
DD
Lo
w
4
2
(N
o
te
1
43
Stop
)
Watchdog: Timeout OR VDD Low
SPI: Stop & CS
LOW to HIGH
Transition
Nostop and SPI: Sleep
& CS LOW to HIGH
Transition
ch
do
Wake-Up
33742 Power-Up
W
at
Standby
3
SP
I:
H Sto
ig p
h &
Tr C
an S
si Lo
ti o w
n to
Normal Request
1
1
Normal
1
Nostop and SPI:
Sleep & CS LOW
to HIGH
Reset
SPI: Standby and
Watchdog Trigger
(Note 42)
SPI: Normal
2
SPI: Standby
Reset Counter (3.4 ms)
Expired
g:
do
ch r
at e
W rigg
T
Freescale Semiconductor, Inc...
The 33742 incorporates a high-speed 1.0 Mbps CAN
physical interface. It is compatible with ISO 11898-2. The
control of the CAN physical interface operation is accomplished
through the SPI. CAN modes are independent of the 33742
operation modes.
Wake-Up
(VDD High Temperature OR [VDD Low > 100 ms & VSUP > BFew]) & Nostop & !BATFAIL
1
2
3
4
Sleep
Denotes priority
State Machine Description
Nostop = Nostop bit = 1
!Nostop = Nostop bit = 0
BATFAIL = Batfail bit = 1
!BATFAIL = Batfail bit = 0
VDD Overtemperature = VDD thermal shutdown occurs
VDD LOW = VDD below reset threshold
VDD LOW > 100 ms = VDD below reset threshold for more than 100 ms
Watchdog: Trigger = TIM1 subregister write operation
VSUP > BFew = VSUP > Battery Fail Early Warning (6.1 V typical)
Watchdog: Timeout = TIM1 register not written before watchdog timeout period
expired, or watchdog written in incorrect time window if watchdog window
selected (except Stop mode). In Normal Request mode, timeout is 355 ms
p2.2 (350 ms p3) ms.
SPI: Sleep = SPI write command to MCR register, data sleep
SPI: Stop = SPI write command to MCR register, data stop
SPI: Normal = SPI write command to MCR register, data normal
SPI: Standby = SPI write command to MCR register, data standby
Notes
42. These two SPI commands must be sent consecutively in this sequence.
43. If watchdog activated.
Figure 10. 33742 State Diagram (Not Valid in Debug Modes)
33742
24
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Power-Up
Behavior after power-up if no trigger appears
Behavior after reset of BATFAIL if no trigger appears
Reset
Normal
Request
Yes
No
Trigger
No
No
Batfail
No Stop
Yes
Sleep
Freescale Semiconductor, Inc...
Yes
Normal
Figure 11. Behavior at 33742 Power-Up
Debug Mode: Hardware and Software Debug with the
33742
Debug Modes with Software Watchdog Disabled Though
SPI (Normal Debug, Standby Debug, and Stop Debug)
When the 33742 is mounted on the same printed circuit
board as the MCU it supplies, both application software and
33742 dedicated routines must be debugged. The following
features permit software debugging by allowing the possibility
of disabling the 33742 internal software watchdog timer.
The watchdog software can be disabled through SPI. To
avoid unwanted watchdog disable while limiting the risk of
disabling the watchdog during 33742 normal operation,
watchdog disable must be done using the following sequence:
Device Power-Up, Reset Terminal Connected to VDD
At 33742 power-up, VDD voltage is provided; however, if no
SPI communication occurs to configure the device, a reset
occurs every 350 ms. In order to allow software debug and
avoid MCU reset, the RST terminal can be connected directly to
VDD by a jumper.
• Step 1–Power down the 33742.
• Step 2–Power up the 33742. This sets the BATFAIL bit,
allowing the 33742 to enter Normal Request mode.
• Step 3–Write to the TIM1 subregister to allow the 33742
to enter Normal mode.
• Step 4–Write to the MCR register with data 0000. This
enables the debug mode. Complete SPI byte is
0001 0000.
• Step 5–Write to the MCR register normal debug. SPI byte
is 0001 x101.
Important While in debug mode, the 33742 can be used
without having to clear the watchdog on a regular basis to
facilitate software and hardware debug.
• Step 6–To leave the debug mode, write 0000 to the MCR
register.
At Step 2, the 33742 is in Normal Request. Steps 3, 4, and 5
should be completed consecutively and within the 350 ms time
period of the Normal Request mode. If not, the 33742 will go
into Reset mode and enter Normal Request again.
Figure 12, page 26, illustrates debug mode selection.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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25
Freescale Semiconductor, Inc.
VSUP
VDD
BATFAIL
TIM1(Step 3)
MCR (Step 5)
MCR (Step 6)
SPI
MCR (Step 4)
Debug Mode
SPI: Read BATFAIL
33742/33742S in Debug mode.
No Watchdog
33742/33742S not in Debug mode.
Watchdog ON
When the 33742 is in debug mode and has been set into
Stop Debug or Sleep, a wake-up causes the 33742 to enter the
Normal Request mode for 350 ms. To avoid having the 33742
generate a reset (enter Reset mode), the desired next debug
mode (Normal Debug or Standby Debug) should be configured
within the 350 ms time period of the Normal Request mode.
To avoid entering debug mode after a power-up, first read
the BATFAIL bit (MCR read) and write 0000 into the MCR
register.
Figure 13 below and Figure 14, page 27, show the detailed
operation of the 33742 once the debug mode has been
selected.
Watchdog: Timeout 350 ms
Normal Request
Reset Counter
(3.4 ms) Expired
Power
Down
Reset
Watchdog:
Trigger
Freescale Semiconductor, Inc...
Figure 12. Entering Debug Mode
Normal
SPI: MCR (0000) and Normal Debug
Normal Debug
SPI: MCR (0000) and Standby Debug
Standby Debug
Figure 13. Transitions to Enter Debug Modes
33742
26
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Watchdog: Timeout 350 ms
Normal
ma
l
De
E
SPI: Normal Debug
or
db
y
:N
St
an
SPI: Standby Debug
Standby Debug
R
D
eb
ug
Standby
er
Sleep
& !BATFAIL & NOSTOP
& SPI: Sleep
R
g: T
rig
g
R
SP
I
SPI: Stop Debug & CS Low to
High Transition
SPI: Stop
Freescale Semiconductor, Inc...
Stop Debug
hd
o
bu
I:
R
Wa
tc
R
Wake-Up
Reset
g
SP
W
ak
eU
p
R
Reset Counter
(3.4 ms) Expired
Normal Request
SPI: Standby &
Watchdog: Trigger
Wake-Up
Stop (1)
E
SPI: Standby Debug
Normal Debug
SPI: Normal Debug
R
R
(1) If Stop mode is entered, it is entered without watchdog, no matter the WDSTOP bit.
(E) Debug mode entry point (Step 5 of the Debug mode entering sequence).
(R) Represents transitions to Reset mode due to VDD low.
Figure 14. Simplified 33742 State Diagram in Debug Modes
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MCU Flash Programming Configuration
To allow for the possibility of downloading software into the
application memory (MCU EEPROM or Flash), the 33742 is
capable of allowing (1) VDD to be forced by an external power
supply to 5.0 V and (2) the RST and the WDOG outputs to be
forced by external signal sources to 0 V or 5.0 V, both without
damaging the device. This allows, for example, the complete
application board to be supplied by external power supply and
external signal to be applied to the reset terminals. No functions
of the 33742 are operating. Figure 15 illustrates a typical
configuration for the connection of programming and debugging
tools.
The VDD regulator has an internal pass transistor between
VSUP and the VDD output terminal. Biasing the VDD output
terminal with a voltage greater than VSUP potential will force
current through the body diode of the internal pass transistor to
the VSUP terminal. Therefore, VSUP should be left open or
forced to a value equal to or above VDD.
The RST terminal is periodically pulled LOW for t RSTDUR time
(device in reset mode), before being pulled to VDD for 350 ms
typical (device in Normal Request mode). During the time reset
is LOW, the RST terminal sinks 5.0 mA maximum (IPDW).
VDD
Freescale Semiconductor, Inc...
VSUP (Open or > 5.0 V
RST
33742
WDOG
5.0 V
MCU with
Flash Memory
Programming Bus
Programming Tool
Note External supply and sources applied to VDD, RST, and WDOG test points on application circuit board.
Figure 15. Simplified Schematic for Microcontroller Flash Programming
33742
28
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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CAN BUS MODULE DESCRIPTION
Introduction
The 33742 features a high-speed CAN physical interface for
bus communication between 60 kbps up to 1.0 Mbps. Figure 16
below is a simplified block diagram of the CAN interface of the
33742.
V2
V2
V2
SPI control
Freescale Semiconductor, Inc...
TXD
Driver
QH
CANH
V2
CANH Line
Differential
Receiver
RXD
Bus Termination (60 Ω)
2.5 V
CANL Line
V2
CANL
Driver
QL
SPI Control
VSUP
Internal
Wake-Up
Signal
Wake-Up
Pattern
Recognition
Wake-Up
Receiver
SPI Control
Figure 16. Simplified Block Diagram of CAN Interface
CAN Interface Supply
CAN Driver Operation in TXRX Mode
The supply voltage for the CAN driver is the V2 terminal. The
CAN interface has also a supply path from the battery line,
through the VSUP terminal. This path is used in CAN Sleep
mode to allow wake-up detection.
When the CAN interface of the 33742 is in TXRX mode, the
driver has two states: recessive or dominant. The driver state is
controlled by the TXD terminal. The bus state is reported
through the RXD terminal.
During CAN communication (transmission and reception),
the CAN interface current is sourced from the V2 terminal.
During CAN low power mode, the current is sourced from the
VSUP terminal.
When TXD is HIGH, the driver is set in recessive state, and
CANH and CANL lines are biased to the voltage set at V2
divided by 2, or approximately. 2.5 V.
Main Operation Modes Description
When TXD is LOW, the bus is set into dominant state: CAN L
and CANH drivers are active. CANL is pulled to ground, and
CANH is pulled HIGH toward 5.0 V (voltage at V2).
The CAN interface of the 33742 has two main operation
modes: TXRX and Sleep mode. The modes are controlled by
the CAN SPI Register. In the TXRX mode, which is used for
communication, four different slew rates are available for the
user. In the Sleep mode, the user has the option of enabling or
disabling the remote CAN wake-up capability.
The RXD terminal reports the bus state: CANH minus CANL
voltage is compared versus an internal threshold (a few
hundred millivolts). If CANH minus CANL is below the
threshold, the bus is recessive and RXD is set HIGH. If CANH
minus CANL is above the threshold, the bus is dominant and
RXD is set LOW. This is illustrated in Figure 16, page 29.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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29
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TXD
CANH
Freescale Semiconductor, Inc...
CANL
Typ 2.5 V
Typ 2.5 V
VCANH -VCANL < 500 mV
VCANH -VCANL > 900 mV
RXD
CAN Recessive State
CAN Recessive State
CAN Dominant State
Figure 17. CAN Interface Levels
TXD and RXD Terminals
CAN TXRX Mode and Slew Rate Selection
The TXD terminal has an internal pullup to V2. The state of
TXD depends on the V2 status. RXD is a push-pull structure,
supplied by V2. When V2 is set at 5.0 V and CAN is TXRX
mode, RXD reports bus status. For details, refer to Table 2,
page 20, Table 4, below, and Table 5, page 31.
The slew rate selection is done via CAN register (refer to
Tables 16 through 18 on page 40). Four slew rates are
available, and controls the recessive to dominant and dominant
to recessive transitions. The delay time from TXD terminal to
CAN bus, from CAN bus to RXD and the TXD to RXD loop time
is affected by the slew rate selection.
Table 4. CAN Interface/33742 Modes and Terminal Status—Operation with Ballast on V2 (Note 44)
Mode
CAN Mode
(Controlled by SPI)
V2 Voltage
TXD Terminal
RXD Terminal
CANH/CANL
(Disconnected
from Other Node)
CAN
Communication
Unpowered
–
0V
LOW
LOW
Floating to GND
NO
Reset (with Ballast)
–
0V
LOW
LOW
Floating to GND
NO
Normal Request
(with Ballast)
–
0V
LOW
LOW
Floating to GND
NO
Normal
Sleep
5.0 V
0V
5.0 V
Floating to GND
NO
Normal
Normal
Slew Rate 0, 1, 2, 3
5.0 V
Internal Pullup
to V2
Report Bus State
HIGH if Bus
Recessive,
LOW if dominant
Bus Recessive
CANH = CANL =
2.5 V
YES
Standby with
External Ballast
Normal or Sleep
0V
LOW
LOW
Floating to GND
NO
Sleep
Sleep
0V
LOW
LOW
Floating to GND
NO.
Wake-up if enabled
Stop
Sleep
0V
LOW
LOW
Floating to GND
NO.
Wake-up if enabled
Notes
44.
33742
30
See also Figure 28, page 46.
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Freescale Semiconductor, Inc...
Table 5. CAN Interface/33742 Modes and Terminal Status—Operation without Ballast on V2 (Note 45)
Mode
CAN Mode
(Controlled by SPI)
V2 Voltage
TXD Terminal
RXD Terminal
CANH/CANL
(Disconnected
from Other Node)
CAN
Communication
Unpowered
–
0V
LOW
LOW
Floating to GND
NO
Reset (with Ballast)
–
0V
LOW
LOW
Floating to GND
NO
Normal Request
without Ballast.
V2 Connected to VDD
–
5.0 V
LOW
5.0 V
Floating to GND
NO
Standby without
External Ballast, V2
connected to VDD
Normal or Sleep
5.0 V
0V
5.0 V
Floating to GND
NO
Normal without
External Ballast. V2
Connected to VDD
Normal
Slew Rate 0, 1, 2,3
5.0 V
5.0 V
5.0 V
Bus Recessive
CANH = CANL =
2.5 V
YES
Normal without
External Ballast, V2
Connected to VDD
Sleep
5.0 V
0V
5.0 V
Floating to GND
NO
Sleep
Sleep
0V
LOW
LOW
Floating to GND
NO.
Wake-up if enabled
Stop
Sleep
0V
LOW
LOW
Floating to GND
NO.
Wake-up if enabled
Notes
45.
See also Figure 29, page 47.
CAN Sleep Mode
The 33742 offers two CAN Sleep modes:
• Sleep mode with CAN wake-up enable: detection of
incoming CAN message and SBC wake-up.
• Sleep mode with CAN wake-up disable: no detection of
incoming CAN message.
The CAN Sleep mode is done via the CAN SPI register.
In CAN Sleep mode (with wake-up enable or disable), the
CAN interface is internally supplied from the VSUP terminal. The
voltage at V2 terminal can be either 5.0 V or turned off. When
the CAN is in Sleep mode, the current sourced from V2 is
extremely low. In most cases the V2 voltage is off; however, the
CAN can be placed into Sleep mode even with 5.0 V applied on
V2.
In CAN Sleep mode, the CANH and CANL drivers are
disabled, and the receiver is also disabled. CANH and CANL
are high ohmic termination to ground.
CAN Signals in TXRX and Sleep Modes
When the CAN interface is set back into TXRX mode by an
SPI command, CAN H and CANL are set in recessive level.
This is illustrated in Figure 18.
TXD
CANH Dominant
CANH
CANL/CANH Recessive
2.5 V
CANL
CANL Dominant
Ground
RXD
CAN in TXRX Mode
CAN in Sleep Mode
(Wake-Up Enable or Disable)
CAN in TXRX Mode
(Controlled by SPI Command)
Figure 18. CAN Signals in TXRX and Sleep Modes
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31
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CAN in Sleep Mode with Wake-Up Enable
Pattern Wake-Up
When the CAN interface is in Sleep mode with wake up
enable, the CAN bus traffic is detected. The CAN bus wake up
is a pattern wake up.
In order to wake up the CAN interface, the following criteria
must be fulfilled:
• The CAN interface wake-up receiver must receive a
series of three consecutive valid dominant pulses, each of
them has to be longer than 500 ns and shorter than
500 µs.
• The distance between 2 pulses must be lower than
500 µs.
• The three pulses must occur within a time frame of 1.0 ms.
Freescale Semiconductor, Inc...
The pattern wake-up of the 33742 CAN interface allow wake-up
by any CAN message content.
Figure 19 below illustrates the CAN signals during a CAN
bus Sleep state and wake-up sequence.
TXD
CANH Dominant
CANH
2.5 V
CANL/CANH Recessive
CANH Dominant
CANH Dominant
CANH Dominant
Pulse # 1
Pulse # 2
Pulse # 3
CANL Dominant
CANL Dominant
CANL Dominant
CANL
CANL Dominant
Ground
CAN Bus Sleep State
RXD
CAN in TXRX Mode
Incoming CAN Message
CAN in Sleep Mode (Wake-Up Enable)
WU Receiver
Min 500 ns
Max 500 µs
Internal Wake-Up Signal
Figure 19. CAN Bus Signal During Can Sleep State and Wake-Up Sequence
33742
32
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Figure 20 illustrates how the wake-up signal is generated.
First the CAN signal is detected by a low consumption receiver
(WU receiver). Then the signal passes through a pulse width
filter, which discards the undesired pulses. The pulse must
have a width bigger than 0.5 µs and smaller than 500 µs to be
accepted. When a pulse is discarded, the pulse counter is reset
and no wake-up signal is generated. When a pulse is accepted,
the pulse counter is incremented and, after three pulses, the
internal wake-up signal is asserted.
Pulse OK
CANH
Pulse Width
Filter
CANL
Freescale Semiconductor, Inc...
WU Receiver
Each one of the pulses must be spaced by no more than
500 µs. If not, the counter will be reset and no wake-up signal
will be generated. This is accomplished by the wake-up timeout
generator. The wake-up cycle is completed (and the wake-up
flag reset) when the CAN interface is brought to CAN Normal
mode.
Counter
Latch
RST
Narrow
Pulse
+
RST
Internal Wake-Up
Signal
Timeout
Timeout
Generator
Standby
Figure 20. Wake-Up Functional Block Diagram
CAN Wake-Up Report
The CAN wake-up reports depend upon the 33742 low
power mode.
If the 33742 is placed into Sleep mode (VDD and V2 off), the
CAN wake-up or any wake-up results in VDD regulator turn on,
leading to MCU supply turn on and reset release. If the 33742
is in Stop mode (V2 off and VDD active), the CAN wake-up or
any wake-up is signalled by a pulse on the INT output. In
addition the CAN-WU bit is set in the CAN register.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
If the 33742 is in Normal or Standby mode and the CAN
interface is in Sleep mode with wake-up enable, the CAN wakeup is reported by the bit CANWU in the CAN register.
In the event the 33742 is in Normal mode and CAN Sleep
mode with wake-up enable, it is recommended that the user
check for the CAN WU bit prior to setting the 33742 in Sleep or
Stop mode in case bus traffic has occurred while the CAN
interface was in Sleep mode.
After CAN wake-up, a flag is set in the CAN register. Bit
CAN-WU reports the CAN wake-up event while the 33742 was
in Sleep or Stop mode. This bit is set until the CAN is in placed
by SPI command into TXRX mode and the CAN register read.
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CAN Bus Diagnostic
The 33742 can diagnose CANH or CANL lines short to GND,
short to VSUP , and short to VDD.
As illustrated in Figure 21, several single-ended
comparators are implemented on the CANH and CANL bus
H5
Hb
Freescale Semiconductor, Inc...
TXD
Diagnostic
Hg
lines. These comparators monitor the bus level in recessive and
dominant states. The information is then managed by a logic
circuit to properly determine the failure and report it. Table 6
indicates the state of the comparators in the event of bus failure
and the state of the drivers; that is, whether they are recessive
or dominant.
Vr5
VSUP (12 V–14 V)
Vrvb
VDD
Vrvb (VSUP - 2.0 V)
Vrg
CANH
Vrg
CANL
Logic
Lg
Lb
L5
VDD (5.0 V)
Vr5 (VDD - 0.43 V)
CANH Dominant Level (3.6 V)
Recessive Level (2.5 V)
Vrg (1.75 V)
Vrvb
CANL Dominant Level (1.4 V)
Vr5
GND (0 V)
Figure 21. CAN Bus Simplified Structure
Table 6. Short to GND, Short to VSUP , and Short to 5.0 V Detection Truth Table
Failure Description
Driver Recessive State
Driver Dominant State
Lg (Threshold 1.75 V)
Hg (Threshold 1.75 V)
Lg (Threshold 1.75 V)
Hg (Threshold 1.75 V)
No failure
1
1
0
1
CANL to GND
0
0
0
1
CANH to GND
0
0
0
0
Lb (Threshold VSUP -2.0 V) Hb (Threshold VSUP -2.0 V) Lb (Threshold VSUP -2.0 V)
Hb (Threshold VSUP -2.0 V)
No failure
0
0
0
0
CANL to VSUP
1
1
1
1
CANH to VSUP
1
1
0
1
L5 (Threshold VDD -0.43 V)
H5 (Threshold VDD -0.43 V) L5 (Threshold VDD -0.43 V)
H5 (Threshold VDD -0.43 V)
No failure
0
0
0
0
CANL to VDD
1
1
1
1
CANH to VDD
1
1
0
1
33742
34
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Detection Principle
In the recessive state, if one of the two bus lines is shorted to
GND, VDD, or VSUP, then voltage at the other line follows the
shorted line due to bus termination resistance and the high
impedance of the driver. For example, if CANL is shorted to
GND, CANL voltage is zero, and CANH voltage, as measured
by the Hg comparator, is also close to zero.
In the recessive state the failure detection to GND or VSUP is
possible. However, it is impossible to distinguish which bus line,
CANL or CANH, is shorted to GND or VSUP. In the dominant
state, the complete diagnostic is possible once the driver is
turned on.
Freescale Semiconductor, Inc...
CAN Bus Failure Reporting
CANL bus line failures (for example, CANL short to GND) is
reported in the SPI register TIM1/2. CANH bus line (for
example, CANH short to VSUP) is reported in the LPC register.
In addition CANF and CAN-UF bits in the CAN register
indicate that a CAN bus failure has been detected.
Non-Identified and Fully Identified Bus Failures
As indicated in Table 6, page 34, when the bus is in a
recessive state it is possible to detect an error condition;
however, is it not possible to fully identify which error. This is
called “non-identified” or “under-acquisition” bus failure. If there
is no communication (i.e., bus idle), it is still possible to warn the
MCU that the device has started to detect a bus failure.
TXD
Diag
2.0 V
VDD
RXD
RXD
Driver
Number of Samples for Proper Failure Detection
The failure detector requires at least one cycle of recessive
and dominant state to properly recognize the bus failure. The
error will be fully detected after five cycles of recessivedominant states. As long as the failure detection circuitry has
not detected the same error for five recessive-dominant cycles,
the bit “non-identified failure” (CAN-UF) will be set.
RXD Permanent Recessive Failure
The purpose of this detection mechanism is to diagnose an
external hardware failure at the RXD output terminal and to
ensure that a permanent failure at the RXD terminal does not
disturb network communication. In the event RXD is shorted to
a permanent high level signal (i.e., 5.0 V), the CAN protocol
module within the MCU cannot receive any incoming message.
Additionally, the CAN protocol module cannot distinguish the
bus idle state and could start communication at any time. To
prevent this, an RXD failure detection, as illustrated in Figure 22
and explained below, is necessary.
Diff Output
Sampling Sampling
Sampling
VDD
RXD Sense
When the detection mechanism is complete, the error will be
fully detected and reported in the TIM1/2 and LPC registers and
bit D1 will be reset to 0.
CANL
CANH
TXD
Driver
Logic
In the CAN register, bits D2 and D1 (CAN-F and CAN-UF,
respectively) are used to signal bus failure. Bit D2 reports a bus
failure and bit D1 indicates if the failure is identified or not (bit
D1 is set to 1 if the error is not identified).
RXD Output
CANH
60 Ω
Diff
CANL
Sampling
RXD Short to VDD
RXD Flag Latched
RXD Flag
Prop Delay
Note RXD Flag is neither the RXPR bit in the LPC register nor the CAN-F bit in the INTR register.
Figure 22. RXD Path and RXD Permanent Recessive Detection Principle
RXD Failure Detection
The 33742 senses the RXD output voltage at each LOW-toHIGH transition of the differential receiver. Excluding internal
propagation delay, RXD output should be LOW when the
differential receiver is LOW. In the event RXD is shorted to
5.0 V (e.g., to VDD), RXD will be tied to a high level and the RXD
short to 5.0 V can be detected at the next LOW-to-HIGH
transition of the differential receiver. Compete detection
requires three samples.
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When the error is detected, the flag is latched and the CAN
driver is disabled. The error is reported through the SPI register
LPC, bit RXPR.
Recovery Condition
The internal recovery is completed by the sampling of a
correct low level at TXD, as illustrated in Figure 23, page 36.
As soon as the RXD permanent recessive is detected, the
RXD driver is deactivated and a weak pulldown current source
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is activated in order to allow recovery conditions. The driver
stays disabled until the failure is cleared (RXD no longer
permanent recessive) and the bus driver is activated by an SPI
register command (write 1 to the CANCLR bit in the CAN
register).
CANL
CANH
Diff Output
Sampling
RXD Output
The TXD permanent dominant is used and activated also in
case of TXD short to RXD. The recovery condition for TXD
permanent dominant (recovery means the reactivation of the
CAN drivers) is done by an SPI command and is controlled by
the MCU.
The driver stays disabled until the failure is cleared (TXD no
longer permanent dominant) and the bus driver is activated by
an SPI register command (write 1 to bit CANCLR in the CAN
register).
TXD to RXD Short Circuit Failure
RXD Short to VDD
RXD Flag Latched
Freescale Semiconductor, Inc...
Sampling
Recovery
RXD no longer shorted to VDD
RXD Flag
Note RXD Flag is neither the RXPR bit in the LPC register
nor the CAN-F bit in INTR register.
Figure 23. RXD Recovery Conditions
Principle
In the event TXD is shorted to RXD when an incoming CAN
message is received, RXD is set LOW. Consequently, the TXD
terminal is LOW and drives CANH and CANL into the dominant
state. The bus is stuck in dominant and no further
communication is possible.
Detection and Recovery
TXD Permanent Dominant Failure
Principle
In the event TXD is set to a permanent low level, the CAN
bus is set into dominant level, and no communication is
possible. The 33742 has a TXD permanent timeout detector.
After timeout, the bus driver is disabled and the bus is released
in a recessive state. The TXD permanent dominant failure is
reported in the TIM1 register.
33742
36
The TXD permanent dominant timeout will be activated and
release the CANL and CANH drivers. However, at the next
incoming dominant bit, the bus will then be stuck again in
dominant. In order to avoid this situation, the recovery of the
failure (recovery means the reactivation of the CAN drivers) is
done by an SPI command and controlled by the MCU.
Internal Error Output Flags
There are internal error flags to signal whenever thermal
protection is activated or overcurrent detection occurs on the
CANL or CANH terminals (bit THERM-CUR). The errors are
reported in the CAN register.
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DEVICE FAULT OPERATION
Freescale Semiconductor, Inc...
Table 7 describes the relationship between device fault or
warning and the operation of the VDD, V2, CAN, and HS
interface.
Table 7. Fault/Warning
Fault/Warning
VDD
V2
CAN
HS
Battery Fail
Turn OFF
Turn OFF
Turn OFF due to V2.
No communication
OFF
VDD Temperature
Prewarning
Warning flag only.
Leave as is
No change
No change
No change
VDD Overtemperature
Turn OFF
Turn OFF
Turn OFF due to V2.
No communication
OFF
VDD Overcurrent
VDD regulator enters linear
mode. VDD undervoltage
reset may occurs. VDD
overtemperature
prewarning or shutdown
may occur
Turn OFF if VDD
undervoltage reset occurs
If V2 is OFF, turn OFF
and no communication
Turn OFF if VDD
undervoltage reset occurs
VDD Short Circuit
VDD undervoltage reset
occurs. VDD
overtemperature
prewarning or shutdown
may occur
Turn OFF
Turn OFF due to V2.
No communication
OFF
Watchdog Reset
ON
Turn OFF
Turn OFF due to V2.
No communication
OFF
V2LOW (e.g., V2 < 4.0 V)
No change
V2 out of range
Turn OFF due to V2 low
No change
HS Overtemperature
No change
No change
No change
OFF
HS Overcurrent
No change
No change
No change
HS overtemperature
may occur
VSUP LOW
No change
No change
No change
No change
CAN Overtemperature
No change
No change
Disable. As soon as
temperature falls, CAN is
re-enabled automatically
No change
CAN Overcurrent
No change
No change
(Note 46)
No change
CANH Short to GND
No change
No change (Note 47)
No communication
(Note 48)
No change
CANH Short to VDD
No change
No change
Communication OK
No change
CANH Short to VSUP
No change
No change
Communication OK
No change
CANL Short to GND
No change
No change
Communication OK
No change
CANL Short to VDD
No change
No change
No communication
(Note 48)
No change
CANL Short to VSUP
No change
No change
No communication
(Note 48)
No change
Notes
46. Refer to descriptions of CANH and CANL short to GND, VDD, and VSUP elsewhere in table.
47.
48.
Peak current 150 mA during TXD dominant only. Due to loss of communication, CAN controller reaches bus OFF state. Average current
out of V2 is below 10 mA.
Overcurrent might be detected. Bit THERM-CUR set in CAN register.
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SPI INTERFACE AND REGISTER DESCRIPTION
Data Format Description
Table 8 lists the possible reset conditions.
Figure 24 illustrates a register, an 8-bit SPI. The first three
bits are used to identify the internal 33742 register address.
Bit 4 is a read/write bit. The last four bits are data sent from the
MCU to the 33742 or read back from the 33742 to the MCU.
Freescale Semiconductor, Inc...
The state of the MISO has no significance during the write
operation. However, during the read operation the final four bits
of MISO have meaning; namely, they contain the content of the
accessed register.
MISO
Bit 7 Bit 6
A2
Bit 5
A1
A0
Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
R/W
D2
D1
D0
D3
Table 8. Possible Reset Conditions
Condition
Name
33742 Reset
POR
Power-ON Reset
33742 Mode
Transition
NR2R
Normal Request to Reset Mode
NR2N
Normal Request to Normal Mode
NR2STB
Normal Request to Standby Mode
MOSI
N2R
Normal to Reset Mode
STB2R
Standby to Reset Mode
STO2R
Stop to Reset Mode
STO2NR
Address
Data
33742 Mode
Note Read operation: R/W bit = 0; Write operation: R/W = 1.
Figure 24. Data Format Description
Definition
RESET
Stop to Normal Request
33742 in Reset Mode
Register Descriptions
The following tables in this section describe the SPI register
list and register bit meaning. Register reset value is also
described, along with the reset condition. Reset condition is the
condition causing the bit to be set at the reset value.
Table 9. List of Registers
Formal Name
and Link
Comment and Use
Register
Address
MCR
$000
Mode Control Register (MCR)
on page 39
Selection for Normal, Standby, Sleep,
Stop, and Debug modes
RCR
$001
Reset Control Register (RCR)
on page 40
Configuration for reset voltage level, CAN Sleep and Stop modes
CAN
$010
CAN Register (CAN) on page
40
CAN slew rate, Sleep and Wake-Up
enable/disable modes, drive enable after
failure
CAN wake-up and CAN failure status bits
IOR
$011
Input/Output Register (IOR)
on page 41
HS (High Side switch) control in Normal
and Standby mode
HS overtemperature bit, VSUP, and V2
Low status
WUR
$100
Wake-Up Register (WUR) on
page 42
Control of wake-up input polarity
Wake-up input and real time Lx input state
TIM
$101
Timing Register (TIM1/2) on
page 43
• TIM1: Watchdog timing control,
Watchdog Window (WDW) or
Watchdog Timeout (WTO) mode
• TIM2: Cyclic Sense and Forced
Wake-Up timing selection
CANL and TXD failure reporting
LPC
$110
Low Power Control Register
(LPC) on page 44
Control HS periodic activation in Sleep
and Stop modes, Forced Wake-Up mode
activation, CAN-INT mode selection
CANH and RXD failure reporting
INTR
$111
Interrupt Register (INTR) on
page 45
Enable or Disable of Interrupts
Interrupt source
33742
38
Write
Read
BATFAIL, general failure, VDD prewarning, and Watchdog flag
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Mode Control Register (MCR)
Table 11. Mode Control Register Control Bits
Tables 10 through 12 describe various Mode Control
Register information.
MCTR2 MCTR
1
Table 10. Mode Control Register
Freescale Semiconductor, Inc...
MCR
R/W
D3
D2
D1
D0
W
–
MCTR2
MCTR1
MCTR0
$000b
R
BATFAIL
(Note 49)
VDDTEMP
GFAIL
WDRST
Reset
Value
–
–
0
0
0
Reset
Condition
(Write)
(Note 50)
–
–
POR,
RESET
POR,
RESET
POR,
RESET
Notes
49. BATFAIL bit cannot be set by SPI. BATFAIL is set when VSUP
falls below 3.0 V.
50. See Table 8, page 38, for definitions of reset conditions.
MCTR
0
33742 Mode
Description
0
0
0
Enter/Exit
Debug Mode
To enter/exit Debug
Mode, refer to detailed
description in Debug
Mode: Hardware and
Software Debug with
the 33742, page 25.
0
0
1
Normal
–
0
1
0
Standby
–
0
1
1
Stop,
Watchdog OFF
(Note 51)
–
0
1
1
Stop,
Watchdog ON
(Note 51)
–
1
0
0
Sleep
(Note 52)
–
1
0
1
Normal
1
1
0
Standby
No Watchdog running.
Debug Mode.
1
1
1
Stop
Notes
51. Watchdog ON or OFF depends on RCR bit D3.
52. Before entering Sleep mode, bit BATFAIL in MCR must be
previously cleared (MCR read operation), and bit NOSTOP in
RCR must be previously set to 1.
Table 12. Mode Control Register Status Bits
Name
BATFAIL
VDDTEMP
GFAIL
WDRST
Value
Description
0
VSUP was not below VBF.
1
VSUP has been below VBF.
0
No overtemperature pre-warning.
1
Temperature pre-warning on VDD
regulator (bit latched).
0
No failure.
1
CAN Failure or HS overtemperature or
V2 low.
0
No watchdog reset occurred.
1
Watchdog reset occurred.
——————————————————
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Reset Control Register (RCR)
Table 14. Reset Control Register Control Bits
Tables 13 and 14 contain various Reset Control Register
information.
$001b
Reset Value
Freescale Semiconductor, Inc...
Reset
Condition
(Write)
(Note 53)
R/W
W
R
D3
D2
D1
WDSTOP
NOSTOP
CAN
SLEEP
RSTTH
1
0
0
0
–
–
POR,
RESET,
STO2NR
POR,
NR2N,
NR2STB
POR,
NR2N,
NR2STB
Value
WDSTOP
Table 13. Reset Control Register
RCR
Name
D0
POR
NOSTOP
CAN
SLEEP
RSTTH
Notes
53. See Table 8, page 38, for definitions of reset conditions.
Description
0
No Watchdog in Stop Mode.
1
Watchdog runs in Stop Mode.
0
Device cannot enter Sleep Mode.
1
Sleep mode allowed. Device can enter
Sleep Mode.
0
CAN Sleep Mode disable (despite D0 bit
in CAN register).
1
CAN Sleep Mode enabled (in addition to
D0 in CAN register).
0
Reset Threshold 1 selected (typ 4.6 V).
1
Reset Threshold 2 selected (typ 4.2 V).
——————————————————
CAN Register (CAN)
Tables 15 through 18 contain various CAN register
information. Table 15 describes control of the high-speed CAN
module, mode, slew rate, and wake-up.
Table 16. CANCLR Control Bits
Value
Table 15. CAN Register
CAN
$010b
R/W
D3
D2
D1
D0
W
CANCLR
SC1
SC0
MODE
R
CANWU
CAN-F
CAN-UF
THERMCUR
Reset Value
–
0
0
0
1
Reset
Condition
(Write)
(Note 54)
–
POR
POR
POR
NR2N,
STB2N
0
No effect.
1
Re-enables CAN driver after TXD permanent
dominant or RXD permanent recessive failure
occurred. Failure recovery conditions must occur to
re-enable.
High-Speed CAN Transceiver Modes
The MODE bit (D0) controls the state of the CAN interface,
TXRX or Sleep mode (Table 17). SC0 bit (D1) defines the slew
rate when the CAN module is in TXRX, and it controls the wakeup option (wake-up enable or disable) when the CAN module is
in Sleep mode.
Notes
54. See Table 8, page 38, for definitions of reset conditions.
33742
40
Description
Table 17. CAN High-Speed Transceiver Modes
SC1
SC0
MODE
CAN Mode
(Pass 1.1)
0
0
0
CAN TXRX, Slew Rate 0
0
1
0
CAN TXRX, Slew Rate 1
1
0
0
CAN TXRX, Slew Rate 2
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Table 18. CAN Register Status Bits
Name
Value
CANWU
CAN-F
CAN-UF
Freescale Semiconductor, Inc...
THERMCUR
Description
0
No CAN wake-up occurred.
1
CAN wake-up occurred.
0
No CAN failure.
1
CAN failure (Note 55).
0
Identified CAN failure (Note 55).
1
Non-identified CAN failure.
0
No overtemperature or overcurrent on
CANH or CANL drivers.
1
Overtemperature or overcurrent on
CANH or CANL drivers.
Notes
55. Error bits are latched in the CAN register.
——————————————————
Input/Output Register (IOR)
Table 20. HSON Control Bits
Tables 19 through 21 contain various Input/Output Register
information. Table 20 provides information about HS control in
Normal and Standby modes, while Table 21 provides status bit
information.
Table 19. Input/Output Register
IOR
R/W
D3
D2
D1
D0
W
–
HSON
–
–
R
V2LOW
HSOT
VSUPLOW
DEBUG
Reset
Value
–
–
0
–
–
Reset
Condition
(Write)
(Note 56)
–
–
POR
–
–
$011b
Value
0
HS OFF, in Normal and Standby modes.
1
HS ON, in Normal and Standby modes (Note 57).
Notes
57. When HS is turned OFF due to an overtemperature condition,
it can be turned ON again by setting the appropriate control bit
to 1. Error bits are latched in the IOR register.
Table 21. Input/Output Register Status Bits
Name
V2LOW
Notes
56. See Table 8, page 38, for definitions of reset conditions.
HS State
HSOT
VSUPLOW
DEBUG
Value
Description
0
V2 > 4.0 V.
1
V2 < 4.0 V.
0
No HS overtemperature.
1
HS overtemperature.
0
VSUP > 6.1 V.
1
VSUP < 6.1 V.
0
33742 not in Debug mode.
1
33742 accepts command to go to
Debug modes (no Watchdog).
——————————————————
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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41
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Wake-Up Register (WUR)
Table 23. Wake-Up Register Control Bits
Tables 22 through 24 contain various Wake-Up Register
information. Local wake-up inputs L0:L3 can be used in both
Normal and Standby modes as port expander, as well as for
waking up the 33742 from Sleep or Stop modes (Table 22).
LCTR3 LCTR2 LCTR1 LCTR0
R/W
D3
D2
D1
D0
W
LCTR3
LCTR2
LCTR1
LCTR0
R
L3WU
L2WU
L1WU
L0WU
Reset
Value
–
0
0
0
0
Reset
Condition
(Write)
(Note 58)
–
Freescale Semiconductor, Inc...
$100b
POR, NR2R, N2R, STB2R, STO2R
Notes
58. See Table 8, page 38, for definitions of reset conditions.
Wake-up inputs can be configured by pair. L0 and L1 can be
configured together, and L2 and L3 can be configured together
(Table 23).
L2:L3 Config
x
x
0
0
Inputs Disabled
x
x
0
1
High Level
Sensitive
x
x
1
0
Low Level
Sensitive
x
x
1
1
Both Level
Sensitive
0
0
x
x
Inputs Disabled
0
1
x
x
High Level
Sensitive
1
0
x
x
1
1
x
x
Table 22. Wake-Up Register
WUR
L0:L1 Config
–
–
Low Level
Sensitive
Both Level
Sensitive
x = Don’t care.
Table 24. Wake-Up Register Status Bits (Note 59)
Name
Value
Description
L3WU
0 or 1
L2WU
0 or 1
If bit = 1, wake-up occurred from Sleep
or Stop modes; if bit = 0, no wake-up
has occurred.
L1WU
0 or 1
L0WU
0 or 1
When device is in Normal or Standby
mode, bit reports the State on Lx
terminal (LOW or HIGH) (0 = Lx LOW,
1 = Lx HIGH)
Notes
59. WUR status bits have two functions. After 33742 wake-up,
they indicate the wake up source; for example, L2WU set at 1
if wake-up source is L2 input. After 33742 wake-up and once
the WUR register has been read, status bits indicate the realtime state of the Lx inputs (1 = Lx is above threshold, 0 = Lx
input is below threshold). If after a wake-up from Lx input a
watchdog timeout occurs before the first reading of the WUR
register, the LxWU bits are reset. This can occur only if the
33742 was in Stop Mode.
——————————————————
33742
42
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Timing Register (TIM1/2)
Tables 25 through 29 contain various Timing Register
information. The TIM register is composed of two subregisters:
1. TIM1—Controls the watchdog timing selection as well as
either the watchdog window or the watchdog timeout
option (Figure 25 and Figure 26, respectively). TIM1 is
selected when bit D3 is 0 (Table 25). Watchdog timing
characteristics are described in Table 26.
Window Closed
No Watchdog Clear Allowed
Watchdog Timing x 50%
Freescale Semiconductor, Inc...
Figure 25. Window Watchdog
Window Open for Watchdog Clear
Both subregisters also report the CANL and TXD diagnostic.
Watchdog Period
(Watchdog Timing Selected by TIM1 Bit WDW = 0)
Table 25. TIM1 Timing and
CANL Failure Diagnostic Register
R/W
D3
D2
D1
D0
W
0
WDW
WDT1
WDT0
$101b
R
Reset
Value
–
Reset
Condition
(Write)
(Note 60)
–
CANL2VDD CANL2BAT CANL2GND
–
0
TXPD
0
Table 27. Timing Register Status Bits
Name
Value
0
POR,
RESET
POR,
RESET
POR,
RESET
CANL2BAT
Notes
60. See Table 8, page 38, for definitions of reset conditions.
Table 26. TIM1 Control Bits
WDW WDT1 WDT0
Timing
(ms typ)
Parameter
0
0
0
9.75
Watchdog
Period 1
0
0
1
45
Watchdog
Period 2
0
Figure 26. Timeout Watchdog
CANL2VDD
–
1
0
100
Watchdog
Period 3
Watchdog Timing x 50%
Watchdog Period
(Watchdog Timing Selected by TIM1 Bit WDW =1)
2. TIM2—Selects an appropriate timing for sensing the
wake-up circuitry or cyclically supplying devices by
switching the HS on or off. TIM2 is selected when bit D3
is 1 (Table 27). Figure 27, page 44, describes HS
operation when cyclic sense is selected. Cyclic sense
timing characteristics are described in Table 29, page 44.
TIM1
Window Open for Watchdog Clear
CANL2GND
TXPD
Failure Description
0
No CANL short to VDD.
1
CANL short to VDD.
0
No CANL short to VSUP .
1
CANL short to VSUP .
0
No CANL short to GND.
1
CANL short to GND.
0
No TXD dominant
1
TXD dominant.
Description
Table 28. TIM2 Timing and
CANL Failure Diagnostic Register
TIM2
No Window
Watchdog
$101b
R/W
D3
D2
D1
D0
W
1
CSP2
CSP1
CSP0
R
CANL2VDD CANL2BAT CANL2GND
TXPD
0
1
1
350
Watchdog
Period 4
Reset
Value
–
–
0
0
0
1
0
0
9.75
Watchdog
Period 1
–
–
POR,
RESET
POR,
RESET
POR,
RESET
1
0
1
45
Watchdog
Period 2
Reset
Condition
(Write)
(Note 61)
1
1
0
100
Watchdog
Period 3
1
1
1
350
Watchdog
Period 4
Watchdog
Window
enabled
(Window
length is half
the Watchdog
Timing).
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Notes
61. See Table 8, page 38, for definitions of reset conditions.
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43
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Table 29. TIM2 Control Bits
Cyclic Sense Timing,
ON Time
CSP2 CSP1 CSP0
HS ON
HS
Cyclic Sense Timing, OFF Time
10 µs
HS OFF
Lx Sampling Point
Sample
time
Freescale Semiconductor, Inc...
Figure 27. HS Operation When Cyclic Sense Is Selected
Cyclic Sense
Timing (ms)
Parameter
0
0
0
4.6
Cyclic Sense/FWU Timing 1
0
0
1
9.25
Cyclic Sense/FWU Timing 2
0
1
0
18.5
Cyclic Sense/FWU Timing 3
0
1
1
37
Cyclic Sense/FWU Timing 4
1
0
0
74
Cyclic Sense/FWU Timing 5
1
0
1
95.5
Cyclic Sense/FWU Timing 6
1
1
0
191
Cyclic Sense/FWU Timing 7
1
1
1
388
Cyclic Sense/FWU Timing 8
——————————————————
Low Power Control Register (LPC)
Tables 30 through 34 contain various Low Power Control
Register information. The LPC register controls:
• The state of HS in Stop and Sleep modes (HS
permanently OFF or HS cyclic).
• Enable or disable of the forced wake-up function (33742
automatic wake-up after time spent in Sleep or Stop
modes; time is defined by the TIM2 subregister).
• Enable or disable the sense of the wake-up inputs (Lx) at
the sampling point of the Cyclic Sense period (LX2HS bit).
(Refer to Reset Control Register (RCR) on page 40 for
details of the LPC register setup required for proper cyclic
sense or direct wake-up operation.
Table 31. LX2HS Control Bits
Value
0
No.
1
Yes. Lx inputs sensed at sampling point.
Table 32. HSAUTO Control Bits
Value
OFF.
1
ON, HS Cyclic, period defined in TIM2 subregister.
Table 33. CAN-INT Control Bits
Value
(Note 63)
Table 30. Low Power Control Register
$110b
R/W
D3
D2
D1
D0
W
LX2HS
FWU
CAN-INT
HSAUTO
R CANH2VDD CANH2BAT CANH2GND
Reset
Value
–
Reset
Condition
(Write)
(Note 62)
–
0
0
0
RXPR
0
POR,
POR,
POR,
POR,
NR2R, N2R, NR2R, N2R, NR2R, N2R, NR2R, N2R,
STB2R,
STB2R,
STB2R,
STB2R,
STO2R
STO2R
STO2R
STO2R
Notes
62. See Table 8, page 38, for definitions of reset conditions.
33742
44
Auto-Timing HS in Sleep and Stop Modes
0
The LPC register also reports the CANH and RXD
diagnostic.
LPC
Wake-Up Inputs Supplied by HS
Description
0
Interrupt as soon as CAN bus failure detected.
1
Interrupt when CAN bus failure detected and fully
identified.
Notes
63. If CAN-INT is at 0, any undetermined CAN failure will be
latched in the CAN register (bit D1: CAN-UF) and can be
accessed by SPI (refer to CAN Register (CAN) on page 40).
After reading the CAN register or setting CAN-INT to 1, it will
be cleared automatically. The existence of CAN-UF always
has priority over clearing, meaning that a further undetermined
CAN failure does not allow clearing the CAN-UF bit.
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Table 34. LPC Status Bits
Name
Value
CANH2VDD
CANH2BAT
CANH2GND
Freescale Semiconductor, Inc...
RXPR
Failure Description
0
No CANH short to VDD.
1
CANH short to VDD.
0
No CANH short to VSUP.
1
CANH short to VSUP.
0
No CANH short to GND.
1
CANH short to GND.
0
No RXD permanent recessive.
1
RXD permanent recessive.
——————————————————
Interrupt Register (INTR)
Tables 35 through 37 contain various Interrupt Register
information. The INTR register allows masking or enabling the
interrupt source. A read operation identifies the interrupt
source. Table 37 provides status bit information. The status
bits of the INTR register content are copies of the IOR, CAN,
TIM, and LPC registers status content. To clear the Interrupt
Register bits, the IOR, CAN, TIM, and/or LPC registers must be
cleared (read register) and the recovery condition must occur.
Errors bits are latched in the CAN register and the IOR register.
Table 36. Interrupt Register Control Bits
Name
CANF
Description
Mask bit for CAN failures.
VDDTEMP
Mask bit for VDD medium temperature
(pre-warning).
HSOT - V2LOW
Mask bit for HS overtemperature AND
V2 < 4.0 V.
VSUPLOW
Mask bit for VSUP < 6.1 V.
Table 35. Interrupt Register
INTR
R/W
D3
D2
D1
D0
W
VSUPLOW
HSOTV2LOW
(Note 64)
VDDTEMP
CANF
R
VSUPLOW
HSOT
VDDTEMP
CANF
Reset Value
–
0
0
0
0
Reset
Condition
(Write)
(Note 65)
–
POR, RST
POR, RST
POR, RST
POR, RST
$111b
When the mask bit is set, the INT terminal goes low if the
appropriate condition occurs. Upon a wake-up condition from
Stop mode due to overcurrent detection (IDDS-WU1 or IDDS-WU2),
an INT pulse is generated; however, INTR register content
remains at 0000 (not bit set into the INTR register).
Table 37. Interrupt Register Status Bits
Name
VSUPLOW
Notes
64. If only HSOT - V2LOW interrupt is selected (only bit D2 set in
INTR register), reading INTR register bit D2 leads to two
possibilities:
1. Bit D2 = 1: Interrupt source is HSOT.
2. Bit D2 = 0: Interrupt source is V2LOW.
HSOT and V2LOW bits status are available in the IOR register.
65. See Table 8, page 38, for definitions of reset conditions.
HSOT
VDDTEMP
CANF
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Value
Description
0
No VSUP < 6.1 V.
1
VSUP < 6.1 V.
0
No HS overtemperature.
1
HS overtemperature.
0
No VDD medium temperature (prewarning).
1
VDD medium temperature (prewarning).
0
No CAN failure.
1
CAN failure.
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45
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PACKAGE AND THERMAL CONSIDERATIONS
The 33742 is a standard surface mount SOIC 28 package. In
order to improve the thermal performances of the SOIC 28
package, eight terminals are internally connected to the lead
frame and are used for heat transfer to the printed circuit board.
APPLICATIONS
Figure 28 shows a typical 33742 application.
VPWR
Q1
V2
R5
Freescale Semiconductor, Inc...
D1
VSUP monitor
VSUP
Rp
R1
to L0
C1
HS
Control
HS
L0
Rp
R2
SW2
L1
to L1
5.0 V/200 mA
VDD Monitor
C2
C6
SW1
V2CTRL
Dual Voltage Regulator
Programmable
Wake-Up Input
Mode Control
Oscillator
V2
L3
VDD
C3
C4
C5
INT
Interrupt
Watchdog
Reset
WDOG
RST
MOSI
SCLK
MISO
L2
C7
C10
V2
SPI Interface
MCU
CS
CANH
CANL
V2
1.0 Mbps CAN
Physical Interface
TXD
RXD
GND
SW3
R3
Rd
to L2
C8
Internal
Module
Supply
Safe Circuitry
Clamp(1)
SW4
R4
Rd
to L3
C9
Connector
Legend
D1: Example: 1N4002 type
Q1: MJD32C
R1, R2, R3, R4: 10 kΩ
Rp, Rd: Example: 1.0 kΩ depending on switch type.
R5: 2.2 kΩ
C1: 10 µF
C2: 100 nF
C3: 47 µF
C4: 100 nF
C5: 47 µF tantalum or 100 µF chemical
C6, C7, C8, C9, C10: 100 nF
(1) Clamp circuit to ensure max ratings for HS (HS from
-0.3 V to VSUP + 0.3) are respected.
Figure 28. 33742 Typical Application Schematic
33742
46
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VPWR
V2CTRL
D1
VSUP
C1
VSUP Monitor
V2
Dual Voltage Regulator
VDD Monitor
C2
5.0 V/200 mA
V2
VDD
C3
C4
33742 Partial Block Diagram
MCU
Freescale Semiconductor, Inc...
GND
Legend
D1: Example: 1N4002 type
C1: 10 µF
C2: 100 nF
C3: 47 µF
C4: 100 nF
Figure 29. 33742 Application Without External Ballast Transistor on V2 Regulator
CANH
R6
CH
CH
R5
R7
CANL (33742)
CANL
CAN Connector
CANH (33742)
CANH (33742)
CANH
CANL (33742)
CANL
CAN Connector
CL
CL
CS
Legend
R6, R7: 30 Ω
CL, CH: 220 pF
Legend
R5: 60 Ω
CL, CH: 220 pF
CS: > 470 pF
Figure 30. CAN Bus Standard Termination
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Figure 31. CAN Bus Split Termination
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47
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PACKAGE DIMENSIONS
DW SUFFIX
28-LEAD SOICW
PLASTIC PACKAGE
CASE 751F-05
ISSUE F
D
A
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSIONS.
4. MAXIMUM MOLD PROTRUSION 0.015 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
15
Freescale Semiconductor, Inc...
0.25
E
H
M
B
M
28
1
14
PIN 1 IDENT
A1
A
B
e
B
0.025
33742
48
C
M
C A
S
B
S
L
0.10
SEATING
PLANE
C
θ
DIM
A
A1
B
C
D
E
e
H
L
θ
MILLIMETERS
MIN
MAX
2.35
2.65
0.13
0.29
0.35
0.49
0.23
0.32
17.80
18.05
7.40
7.60
1.27 BSC
10.05
10.55
0.41
0.90
0°
8°
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Freescale Semiconductor, Inc...
NOTES
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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33742
49
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
NOTES
33742
50
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Freescale Semiconductor, Inc...
NOTES
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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33742
51
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied
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MC33742