bq3055 SLUSA91A – OCTOBER 2010 – REVISED JANUARY 2012 www.ti.com 2-Series, 3-Series, and 4-Series Li-Ion Battery Pack Manager Check for Samples: bq3055 FEATURES APPLICATIONS • • • • 1 • • • • • • • • • Fully Integrated 2-Series, 3-Series, and 4-Series Li-Ion or Li-Polymer Cell Battery Pack Manager and Protection Advanced Compensated End-of-Discharge Voltage (CEDV) Gauging High Side N-CH Protection FET Drive Integrated Cell Balancing Low Power Modes – Low Power: < 180 µA – Sleep < 76 µA Full Array of Programmable Protection Features – Voltage – Current – Temperature Sophisticated Charge Algorithms – JEITA – Enhanced Charging – Adaptive Charging Supports Two-Wire SMBus v1.1 Interface SHA-1 Authentication Compact Package: 30-Lead TSSOP Notebook/Netbook PCs Medical and Test Equipment Portable Instrumentation DESCRIPTION The bq3055 device is a fully integrated, single-chip, pack-based solution that provides a rich array of features for gas gauging, protection, and authentication for 2-series, 3-series, and 4-series cell Li-Ion and Li-Polymer battery packs. Using its integrated high-performance analog peripherals, the bq3055 device measures and maintains an accurate record of available capacity, voltage, current, temperature, and other critical parameters in Li-Ion or Li-Polymer batteries, and reports this information to the system host controller over an SMBus v1.1 compatible interface. The bq3055 provides software-based 1st-level and 2nd-level safety protection for overvoltage, undervoltage, overtemperature, and overcharge conditions, as well as hardware-based protection for overcurrent in discharge and short circuit in charge and discharge conditions. SHA-1 authentication with secure memory for authentication keys enables identification of genuine battery packs beyond any doubt. The compact 30-lead TSSOP package minimizes solution cost and size for smart batteries while providing maximum functionality and safety for battery gauging applications. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010–2012, Texas Instruments Incorporated bq3055 SLUSA91A – OCTOBER 2010 – REVISED JANUARY 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TA PART NUMBER PACKAGE PACKAGE DESIGNATOR PACKAGE MARKING –40°C to 85°C bq3055 TSSOP-30 DBT bq3055 (1) (2) (3) ORDERING INFORMATION (1) TUBE (2) TAPE AND REEL (3) bq3055DBT bq3055DBTR For the most current package and ordering information, see the Package Option Addendum at the end of the document, or see the TI website at www.ti.com. A single tube quantity is 50 units. A single reel quantity is 2000 units. THERMAL INFORMATION bq3055 THERMAL METRIC (1) TSSOP UNITS 30 PINS θJA, High K Junction-to-ambient thermal resistance (2) 73.1 (3) θJC(top) Junction-to-case(top) thermal resistance θJB Junction-to-board thermal resistance ψJT Junction-to-top characterization parameter ψJB Junction-to-board characterization parameter θJC(bottom) (1) (2) (3) (4) (5) (6) (7) 2 17.5 (4) 34.5 (5) Junction-to-case(bottom) thermal resistance 0.3 (6) (7) °C/W 30.3 n/a For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): bq3055 bq3055 SLUSA91A – OCTOBER 2010 – REVISED JANUARY 2012 www.ti.com TYPICAL IMPLEMENTATION 0.1 μF 0.1 μF 300 Ω 1 MΩ PACK+ 3 MΩ 0.1 μF 10 kΩ 3 MΩ 1 kΩ 1 μF PACK FUSE Control High Side N-CH FET Drive SHA-1 Authentication Charging Algorithms Cell Balancing AFE H/W Control Watchdog System Control Cell Voltage Mux/ Translation CEDV Gauging H/W Overcurrent/ Shortcircuit Protection 2.5V LDO VC1 CD VH 1 kΩ 0.1 μF 5.1 kΩ 5.1 kΩ 5.1 kΩ 10 kΩ DSG BAT VCC 20 kΩ FUSE 20 kΩ CHG 0.1 μF 220 kΩ PCHG RBI 100 Ω 0.1 μF 0.1 μF VC2 OUT 0.22 μF VDD nd 2 VM Level Protector VL 0.1 μF 1 kΩ REG25 100 Ω 0.1 μF VC3 1 kΩ 1 μF 100 Ω 0.1 μF Voltage Measurement Overvoltage / Undervoltage Protection Overtemperature Protection 3.3V LDO VB 1 kΩ Coulomb Counting Overcurrent Protection Temperature Measurement SMBus 1.1 SMBD 100 Ω TEST 0.1 μF 0.1 nF SMBD VC4 GND 1 μF REG33 SMBC 200 Ω 100 Ω PRES 200 Ω 100 Ω SMBC PRES 100 Ω 0.1 μF TS2 SRN 0.1 μF TS1 SRP 0.1 μF 10 kΩ VSS 10 kΩ 2 kΩ 100 Ω 5.6 V 1 kΩ 0.1 nF 100 Ω 5 mΩ PACK - Figure 1. bq3055 Implementation Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): bq3055 3 bq3055 SLUSA91A – OCTOBER 2010 – REVISED JANUARY 2012 www.ti.com Pin-Out Diagram bq3055 CHG 1 30 DSG BAT 2 29 PACK VC1 3 28 PCHG VC2 4 27 VCC VC3 5 26 FUSE VC4 6 25 TEST VSS 7 24 REG33 TS1 8 23 VSS SRP 9 22 REG25 SRN 10 21 RBI TS2 11 20 NC ¯¯¯¯¯ PRES 12 19 NC SMBD 13 18 NC NC 14 17 NC SMBC 15 16 NC Figure 2. bq3055 Pin-Out Diagram PIN FUNCTIONS PIN NAME PIN NUMBER TYPE (1) DESCRIPTION bq3055-DBT (1) 4 CHG 1 O Charge N-FET gate drive BAT 2 P Alternate power source VC1 3 I Sense input for positive voltage of top most cell in stack and cell balancing input for top most cell in stack VC2 4 I Sense input for positive voltage of third lowest cell in stack and cell balancing input for third lowest cell in stack VC3 5 I Sense input for positive voltage of second lowest cell in stack and cell balancing input for second lowest cell in stack VC4 6 I Sense input for positive voltage of lowest cell in stack and cell balancing input for lowest cell in stack VSS 7 P Device ground TS1 8 AI Temperature sensor 1 thermistor input SRP 9 AI Differential Coulomb Counter input SRN 10 AI Differential Coulomb Counter input TS2 11 AI Temperature sensor 2 thermistor input PRES 12 I SMBD 13 I/OD Host system present input NC 14 — SMBC 15 I/OD NC 16 — Not internally connected, connect to VSS NC 17 — Not internally connected, connect to VSS NC 18 — Not internally connected, connect to VSS NC 19 — Not internally connected, connect to VSS NC 20 — Not internally connected, connect to VSS RBI 21 P RAM backup SMBus v1.1 data line Not internally connected, connect to VSS SMBus v1.1 clock line P = Power Connection, O = Digital Output, AI = Analog Input, I = Digital Input, I/OD = Digital Input/Output Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): bq3055 bq3055 SLUSA91A – OCTOBER 2010 – REVISED JANUARY 2012 www.ti.com PIN FUNCTIONS (continued) PIN NAME PIN NUMBER TYPE (1) DESCRIPTION bq3055-DBT REG25 22 P 2.5-V regulator output VSS 23 P Device ground REG33 24 P 3.3-V regulator output TEST 25 — Test pin, connect to VSS through 2-kΩ resistor FUSE 26 O Fuse drive VCC 27 P Power supply voltage PCHG 28 I/OD PACK 29 P Alternate power source DSG 30 O Discharge N-FET gate drive Pre-charge P-FET gate drive ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range (unless otherwise noted) (1) DESCRIPTION PINS VALUE Supply voltage range, VMAX VCC, TEST, PACK w.r.t. Vss –0.3 V to 34 V Input voltage range, VIN VC1, BAT VVC2 – 0.3 V to VVC2 + 8.5 V or 34 V, whichever is lower VC2 VVC3 – 0.3 V to VVC3 + 8.5 V VC3 VVC4 – 0.3 V to VVC4 + 8.5 V VC4 VSRP – 0.3 V to VSRP + 8.5 V SRP, SRN –0.3 V to 0.3 V SMBC, SMBD VSS – 0.3 V to 6.0 V TS1, TS2, PRES –0.3 V to VREG25 + 0.3 V DSG –0.3 V to VPACK + 20 V or VSS + 34 V, whichever is lower CHG –0.3 V to VBAT + 20 V or VSS + 34 V, whichever is lower FUSE –0.3 V to 34 V RBI, REG25 –0.3 V to 2.75 V REG33 –0.3 V to 5.0 V Output voltage range, VO Maximum VSS current, ISS 50 mA Current for cell balancing, ICB ESD Rating 10 mA HBM, VCx Only 1 kV Functional Temperature, TFUNC –40 to 110°C Storage temperature range, TSTG –65 to 150°C Lead temperature (soldering, 10 s), TSOLDER 300°C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted) MIN Supply voltage VSTARTUP VCC, PACK TYP MAX UNIT 25 V BAT 3.8 VVC2 + 5.0 Start up voltage at PACK 3.0 5.5 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): bq3055 V 5 bq3055 SLUSA91A – OCTOBER 2010 – REVISED JANUARY 2012 www.ti.com RECOMMENDED OPERATING CONDITIONS (continued) Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted) MIN VIN Input voltage range MAX UNIT VC1, BAT VVC2 VVC2 + 5.0 V VC2 VVC3 VVC3 + 5.0 VC3 VVC4 VVC4 + 5.0 VC4 VSRP VSRP + 5.0 0 5.0 –0.2 0.2 VCn – VC(n+1), (n=1, 2, 3, 4) TYP PACK 25 SRP to SRN V CREG33 External 3.3V REG capacitor 1 µF CREG25 External 2.5V REG capacitor 1 µF TOPR Operating temperature –40 85 °C ELECTRICAL CHARACTERISTICS: Supply Current Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER ICC TEST CONDITIONS MIN TYP MAX UNIT Normal CHG on, DSG on, no Flash write 410 µA Sleep CHG on, DSG on, no SBS communication 160 µA CHG off, DSG off, no SBS communication 80 µA Shutdown 1 µA ELECTRICAL CHARACTERISTICS: Power On Reset (POR) Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted) MIN TYP MAX UNIT VIT– Negative-going voltage input PARAMETER At REG25 TEST CONDITIONS 1.9 2.0 2.1 V VHYS POR Hysteresis At REG25 65 125 165 mV ELECTRICAL CHARACTERISTICS: WAKE FROM SLEEP Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER VWAKE VWAKE Threshold MIN TYP MAX UNIT VWAKE = 1.2 mV TEST CONDITIONS 0.2 1.2 2.0 mV VWAKE = 2.4 mV 0.4 2.4 3.6 VWAKE = 5 mV 2.0 5.0 6.8 VWAKE = 10 mV 5.3 10 13 VWAKE_TCO Temperature drift of VWAKE accuracy 0.5 tWAKE Time from application of current and wake of bq3055 0.2 6 Submit Documentation Feedback %/°C 1 ms Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): bq3055 bq3055 SLUSA91A – OCTOBER 2010 – REVISED JANUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS: RBI RAM Backup Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN VRBI > V(RBI)MIN, VCC < VIT I(RBI) RBI data-retention input current V(RBI) RBI data-retention voltage TYP MAX UNIT 20 1100 nA VRBI > V(RBI)MIN, VCC < VIT, TA= 0°C to 70°C 500 1 V ELECTRICAL CHARACTERISTICS: 3.3V Regulator Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER VREG33 Regulator output voltage TEST CONDITIONS MIN TYP MAX UNIT 3.5 V 3.8 V < VCC or BAT ≤ 5 V, ICC ≤4 mA 2.4 5V < VCC or BAT ≤ 6.8 V, ICC ≤13 mA 3.1 3.3 3.5 V 6.8 V < VCC or BAT ≤ 20 V, ICC ≤ 30 mA 3.1 3.3 3.5 V IREG33 Regulator output current ΔV(VDDTEMP) Regulator output change with temperature VCC or BAT = 14.4 V, IREG33 = 2 mA 0.2 ΔV(VDDLINE) Line regulation VCC or BAT = 14.4 V, IREG33 = 2 mA 1 13 mV ΔV(VDDLOAD) Load regulation VCC or BAT = 14.4 V, IREG33 = 2 mA 5 18 mV I(REG33MAX) Current limit 2 mA % VCC or BAT = 14.4 V, VREG33 = 3 V 70 VCC or BAT = 14.4 V, VREG33 = 0 V 33 mA ELECTRICAL CHARACTERISTICS: 2.5V Regulator Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER TEST CONDITIONS IREG25 = 10 mA MIN TYP MAX 2.35 2.5 2.55 UNIT VREG25 Regulator output voltage IREG25 Regulator Output Current V ΔV(VDDTEMP) Regulator output change with temperature VCC or BAT = 14.4 V, IREG25 = 2 mA ΔV(VDDLINE) Line regulation VCC or BAT = 14.4 V, IREG25 = 2 mA 1 4 mV ΔV(VDDLOAD) Load regulation VCC or BAT = 14.4 V, IREG25 = 2 mA 20 40 mV I(REG33MAX) Current limit 3 mA 0.25 % VCC or BAT = 14.4 V, VREG25 = 2.3 V 65 VCC or BAT = 14.4 V, VREG25 = 0 V 23 mA ELECTRICAL CHARACTERISTICS: PRES, SMBD, SMBC Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX VIH High-level input PRES, SMBD, SMBC VIL Low-level input PRES, SMBD, SMBC 0.8 VOL Low-level output voltage SMBD, SMBC 0.4 CIN Input capacitance PRES, SMBD, SMBC ILKG Input leakage current PRES, SMBD, SMBC IWPU Weak Pull Up Current PRES, VOH = VREG25 – 0.5 V 60 RPD(SMBx) SMBC, SMBD Pull-Down TA = –40 to 100˚C 550 UNIT 2.0 V 5 775 Product Folder Link(s): bq3055 V pF 1 μA 120 μA 1000 kΩ Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated V 7 bq3055 SLUSA91A – OCTOBER 2010 – REVISED JANUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS: CHG, DSG FET Drive Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER V(FETON) V(FETOFF) tr Output voltage, charge, and discharge FETs on Output voltage, charge and discharge FETs off Rise time tf Fall time TEST CONDITIONS MIN TYP MAX UNIT VO(FETONDSG) = V(DSG) – VPACK, VGS connect 10 MΩ, VCC 3.8 V to 8.4 V 8.0 9.7 12 V VO(FETONDSG) = V(DSG) – VPACK, VGS connect 10 MΩ, VCC > 8.4 V 9.0 11 12 V VO(FETONCHG) = V(CHG) – VBAT, VGS connect 10 MΩ, VCC 3.8 V to 8.4 V 8.0 9.7 12 V VO(FETONCHG) = V(CHG) – VBAT, VGS connect 10 MΩ, VCC > 8.4 V 9.0 11 12 V VO(FETOFFDSG) = V(DSG) – VPACK –0.4 0.4 V VO(FETOFFCHG) = V(CHG) – VBAT –0.4 0.4 V CL= 4700 pF RG= 5.1 kΩ VCC < 8.4 VDSG: VBAT to VBAT + 4 V VCHG: VPACK to VPACK + 4 V 800 1400 μs CL = 4700 pF RG = 5.1 kΩ VCC > 8.4 VDSG: VBAT to VBAT + 4 V VCHG: VPACK to VPACK + 4 V 200 500 μs CL = 4700 pF RG = 5.1 kΩ VDSG: VBAT + VO(FETONDSG) to VBAT +1V VCHG: VPACK + VO(FETONCHG) to VPACK + 1 V 80 200 μs ELECTRICAL CHARACTERISTICS: PCHG FET Drive Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER VPU_PCHG PCHG Pull-Up Voltage VOL_PCHG PCHG Output Voltage Low TEST CONDITIONS IOL = 1 mA MIN TYP MAX UNIT VCC V 0.3 V ELECTRICAL CHARACTERISTICS: FUSE Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER VOH(FUSE) High Level FUSE Output VIH(FUSE) Weak pull-up current in off state (1) tR(FUSE) FUSE Output Rise Time ZO(FUSE) FUSE Output Impedance (1) 8 TEST CONDITIONS MIN VCC = 3.8 V to 9 V 2.4 VCC = 9 V to 25 V 7 TYP 8 MAX UNIT 8.5 V 9 V 2.8 V 100 CL = 1 nF, VCC = 9 V to 25 V, VOH(FUSE) = 0 V to 5 V nA 5 20 μs 2 5 kΩ Verified by design. Not production tested. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): bq3055 bq3055 SLUSA91A – OCTOBER 2010 – REVISED JANUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS: COULOMB COUNTER Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER VIN TEST CONDITIONS Input voltage range SRP – SRN Conversion time Single conversion MIN TYP –0.20 MAX UNIT 0.25 V 250 Resolution (no missing codes) ms 16 Effective resolution Single conversion, signed Offset error Post calibrated 15 Bits µV 10 Offset error drift –0.8% Full-scale error Bits 0.3 0.5 0.2% 0.8% Full-scale error drift 150 Effective input resistance µV/°C PPM/°C 2.5 mΩ ELECTRICAL CHARACTERISTICS: VC1, VC2, VC3, VC4 Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER VIN TEST CONDITIONS Input voltage range VC4 – VC3, VC3 – VC2, VC2 – VC1, VC1 – VSS Conversion time Single conversion MIN –0.20 MAX UNIT 8 V 32 Resolution (no missing codes) R(BAL) TYP ms 16 Bits Bits Effective resolution Single conversion, signed 15 RDS(ON) for internal FET at VDS > 2V VDS = VC4 – VC3, VC3 – VC2, VC2 – VC1, VC1 – VSS 200 310 430 Ω RDS(ON) for internal FET at VDS > 4V VDS = VC4 – VC3, VC3 – VC2, VC2 – VC1, VC1 – VSS 60 125 230 Ω ELECTRICAL CHARACTERISTICS: TS1, TS2 Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER R Internal Pull Up Resistor RDRIFT Internal Pull Up Resistor Drift From 25°C RPAD Internal Pin Pad resistance Input voltage range VIN TEST CONDITIONS MIN TYP MAX UNIT 16.5 17.5 19.0 KΩ 200 PPM/°C Ω 84 TS1 – VSS, TS2 – VSS 0.8 × VREG25 –0.20 Conversion Time V 16 Resolution (no missing codes) 16 Effective resolution 11 ms Bits 12 Bits ELECTRICAL CHARACTERISTICS: Internal Temperature Sensor Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER TEST CONDITIONS Temperature sensor voltage V(TEMP) MIN TYP MAX UNIT –1.9 –2.0 –2.1 mV/°C Conversion Time 16 Resolution (no missing codes) 16 Effective resolution 11 Bits 12 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): bq3055 ms Bits 9 bq3055 SLUSA91A – OCTOBER 2010 – REVISED JANUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS: Internal Thermal Shutdown Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP 125 MAX UNIT TMAX2 Maximum REG33 temperature 175 TRECOVER Recovery hysteresis temperature 10 °C tPROTECT Protection time 5 µs ELECTRICAL CHARACTERISTICS: High Frequency Oscillator Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER f(OSC) MIN TYP TA = –20°C to 70°C –2% ±0.25% 2% TA = –40°C to 85°C –3% ±0.25% 3% 3 6 Operating frequency of CPU Clock f(EIO) Frequency error (1) (2) t(SXO) Start-up time (3) (1) (2) (3) TEST CONDITIONS MAX 4.194 TA = –25°C to 85°C UNIT MHz ms The frequency error is measured from 4.194 MHz. The frequency drift is included and measured from the trimmed frequency at VREG25 = 2.5V, TA = 25°C. The startup time is defined as the time it takes for the oscillator output frequency to be ±3% when the device is already powered. ELECTRICAL CHARACTERISTICS: Low Frequency Oscillator Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER f(LOSC) Frequency error (1) (2) f(LEIO) t(LSXO) (1) (2) (3) TEST CONDITIONS MIN TYP Operating frequency Start-up time (3) MAX 32.768 kHz TA = –20°C to 70°C –1.5% ±0.25% 1.5% TA = –40°C to 85°C –2.5% ±0.25% 2.5% TA = –25°C to 85°C UNIT 100 μs The frequency drift is included and measured from the trimmed frequency at VCC = 2.5V, TA = 25°C. The frequency error is measured from 32.768 kHz. The startup time is defined as the time it takes for the oscillator output frequency to be ±3%. ELECTRICAL CHARACTERISTICS: Internal Voltage Reference Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER VREF TEST CONDITIONS Internal Reference Voltage VREF_DRIFT Internal Reference Voltage Drift MIN TYP MAX 1.215 1.225 1.230 UNIT V TA = –25°C to 85°C ±80 PPM/°C TA = 0°C to 60°C ±50 PPM/°C ELECTRICAL CHARACTERISTICS: Flash Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER (1) TEST CONDITIONS Data retention Flash programming write-cycles MIN TYP MAX UNIT 10 Years Data Flash 20k Cycles Instruction Flash 1k Cycles ICC(PROG_DF) Data Flash-write supply current TA = –40°C to 85°C 3 4 mA ICC(ERASE_DF) Data Flash-erase supply current TA = –40°C to 85°C 3 18 mA (1) Verified by design. Not production tested. 10 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): bq3055 bq3055 SLUSA91A – OCTOBER 2010 – REVISED JANUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS: OCD Current Protection Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN 50 RSNS = 1 25 TYP MAX UNIT 200 mV 100 mV V(OCD) OCD detection threshold voltage range, typical RSNS = 0 ΔV(OCDT) OCD detection threshold voltage program step RSNS = 0 10 RSNS = 1 5 V(OFFSET) OCD offset –10 10 V(Scale_Err) OCD scale error –10 10 % t(OCDD) Over Current in Discharge Delay 1 31 ms t(OCDD_STEP) OCDD Step options t(DETECT) Current fault detect time VSRP – SRN = VTHRESH + 12.5 mV tACC Over Current and Short Circuit delay time accuracy Accuracy of typical delay time mV mV mV 2 –20 ms 160 µs 20 % ELECTRICAL CHARACTERISTICS: SCD1 Current Protection Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted) MAX UNIT SCD1 detection threshold voltage range, typical PARAMETER RSNS = 0 100 450 mV RSNS = 1 50 225 mV ΔV(SCD1T) SCD1 detection threshold voltage program step RSNS = 0 V(OFFSET) SCD1 offset –10 10 mV V(Scale_Err) SCD1 scale error –10 10 % t(SCD1D) Short Circuit in Discharge Delay V(SDC1) TEST CONDITIONS MIN TYP 50 RSNS = 1 mV 25 mV AFE.STATE_CNTL[SCDDx2] = 0 0 915 µs AFE.STATE_CNTL[SCDDx2] = 1 0 1830 µs AFE.STATE_CNTL[SCDDx2] = 0 61 AFE.STATE_CNTL[SCDDx2] = 1 122 t(SCD1D_STEP) SCD1D Step options t(DETECT) Current fault detect time VSRP – SRN = VTHRESH + 12.5 mV tACC Over Current and Short Circuit delay time accuracy Accuracy of typical delay time –20 µs µs 160 µs 20 % ELECTRICAL CHARACTERISTICS: SCD2 Current Protection Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT 100 TYP 450 mV RSNS = 1 50 225 mV V(SDC2) SCD2 detection threshold voltage range, typical RSNS = 0 ΔV(SCD2T) SCD2 detection threshold voltage program step RSNS = 0 50 RSNS = 1 25 V(OFFSET) SCD2 offset V(Scale_Err) SCD2 scale error t(SCD1D) Short Circuit in Discharge Delay –10 mV mV 10 mV –10 10 % AFE.STATE_CNTL[SCDDx2] = 0 0 458 µs AFE.STATE_CNTL[SCDDx2] = 1 0 915 µs AFE.STATE_CNTL[SCDDx2] = 0 30.5 AFE.STATE_CNTL[SCDDx2] = 1 61 t(SCD2D_STEP) SCD2D Step options t(DETECT) Current fault detect time VSRP – SRN = VTHRESH + 12.5 mV tACC Over Current and Short Circuit delay time accuracy Accuracy of typical delay time –20 µs µs 160 µs 20 % Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): bq3055 11 bq3055 SLUSA91A – OCTOBER 2010 – REVISED JANUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS: SCC Current Protection Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN –100 RSNS = 1 –50 TYP MAX UNIT –300 mV –225 mV V(SCCT) SCC detection threshold voltage range, typical RSNS = 0 ΔV(SCCDT) SCC detection threshold voltage program step RSNS = 0 –50 RSNS = 1 –25 V(OFFSET) SCC offset –10 V(Scale_Err) SCC scale error –10 10 % t(SCCD) Short Circuit in Charge Delay 0 915 ms t(SCCD_STEP) SCCD Step options t(DETECT) Current fault detect time VSRP – SRN = VTHRESH + 12.5 mV tACC Over Current and Short Circuit delay time accuracy Accuracy of typical delay time mV mV 10 61 –20 mV ms 160 µs 20 % ELECTRICAL CHARACTERISTICS: SBS Timing Characteristics Typical values stated where TA = 25ºC and VCC = 14.4 V, Min/Max values stated where TA= –40ºC to 85ºC and VCC = 3.8 V to 25 V (unless otherwise noted) TEST CONDITIONS MIN SMBus operating frequency PARAMETER Slave mode, SMBC 50% duty cycle 10 fMAS SMBus master clock frequency Master mode, no clock low slave extend tBUF Bus free time between start and stop 4.7 µs tHD:STA Hold time after (repeated) start 4.0 µs tSU:STA Repeated start setup time 4.7 µs tSU:STO Stop setup time 4.0 µs tHD:DAT Data hold time 300 ns tSU:DAT Data setup time 250 ns fSMB See (1) TYP MAX UNIT 100 kHz 51.2 tTIMEOUT Error signal/detect tLOW Clock low period tHIGH Clock high period See (2) tHIGH Clock high period See (2) 50 µs tLOW:SEXT Cumulative clock low slave extend time See (3) 25 ms tLOW:MEXT Cumulative clock low master extend time See (4) 10 ms 300 ns 1000 ns (5) Clock/data fall time See tR Clock/data rise time See (6) (3) (4) (5) (6) 12 35 ms µs 4.7 tF (1) (2) 25 kHz Disabled 4.0 The bq3055 times out when any clock low exceeds tTIMEOUT. tHIGH, Max, is the minimum bus idle time. SMBC = 1 for t > 50 µs causes reset of any transaction involving bq3055 that is in progress. This specification is valid when the THIGH_VAL=0. If THIGH_VAL = 1, then the value of THIGH is set by THIGH_1,2 and the timeout is not SMBus standard. tLOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop. tLOW:MEXT is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop. Rise time tR = VILMAX – 0.15) to (VIHMIN + 0.15) Fall time tF = 0.9 VDD to (VILMAX – 0.15) Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): bq3055 bq3055 SLUSA91A – OCTOBER 2010 – REVISED JANUARY 2012 www.ti.com tR tSU(STOP) tF tF tDH(STA) T(BUF) SMBC SMBC SMBD SMBD P tR tW(H) S tW(L) tHD(DATA) tSU(DATA) tSU(STA) t(TIMEOUT) SMBC SMBC SMBD SMBD S Figure 3. SMBus Timing Diagram Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): bq3055 13 bq3055 SLUSA91A – OCTOBER 2010 – REVISED JANUARY 2012 www.ti.com FEATURE SET Primary (1st Level) Safety Features The bq3055 supports a wide range of battery and system protection features that can easily be configured. The primary safety features include: • • • • • Cell Overvoltage/Undervoltage Protection Charge and Discharge Overcurrent Short-Circuit Charge and Discharge Over-Temperature AFE Watchdog Secondary (2nd Level) Safety Features The secondary safety features of the bq3055 can be used to indicate more serious faults via the FUSE pin. This pin can be used to blow an in-line fuse to permanently disable the battery pack from charging or discharging. The secondary safety protection features include: • Safety Overvoltage • Safety Overcurrent in Charge and Discharge • Safety Over-Temperature in Charge and Discharge • Charge FET, Discharge FET, and Pre-Charge FET Faults • Cell Imbalance Detection • Fuse Blow by Secondary Voltage Protection IC • AFE Register Integrity Fault (AFE_P) • AFE Communication Fault (AFE_C) Charge Control Features The bq3055 charge control features include: • • • • • • • Supports JEITA temperature ranges. Reports charging voltage and charging current according to the active temperature range Handles more complex charging profiles. Allows for splitting the standard temperature range into two sub-ranges and allows for varying the charging current according to the cell voltage Reports the appropriate charging current needed for constant current charging and the appropriate charging voltage needed for constant voltage charging to a smart charger using SMBus broadcasts Reduce the charge difference of the battery cells in fully charged state of the battery pack gradually using a voltage-based cell balancing algorithm during charging. A voltage threshold can be set up for cell balancing to be active. This prevents fully charged cells from overcharging and causing excessive degradation and also increases the usable pack energy by preventing premature charge termination. Supports pre-charging/zero-volt charging Supports charge inhibit and charge suspend if battery pack temperature is out of temperature range Reports charging fault and also indicate charge status via charge and discharge alarms Gas Gauging The bq3055 uses the CEDV algorithm to measure and calculate the available capacity in battery cells. The bq3055 accumulates a measure of charge and discharge currents and compensates the charge current measurement for the temperature and state-of-charge of the battery. The bq3055 estimates self-discharge of the battery and also adjusts the self-discharge estimation based on temperature. See the bq3055 Technical Reference Manual (SLUU440) for further details. Lifetime Data Logging Features The bq3055 offers limited lifetime data logging for the following critical battery parameters: • Lifetime Maximum Temperature • Lifetime Minimum Temperature 14 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): bq3055 bq3055 SLUSA91A – OCTOBER 2010 – REVISED JANUARY 2012 www.ti.com • • Lifetime Maximum Battery Cell Voltage Lifetime Minimum Battery Cell Voltage Authentication • • The bq3055 supports authentication by the host using SHA-1. SHA-1 authentication by the gas gauge is required for unsealing and full access. Power Modes The bq3055 supports three power modes to reduce power consumption: • In Normal Mode, the bq3055 performs measurements, calculations, protection decisions, and data updates in 0.25-second intervals. Between these intervals, the bq3055 is in a reduced power stage. • In Sleep Mode, the bq3055 performs measurements, calculations, protection decisions, and data updates in adjustable time intervals. Between these intervals, the bq3055 is in a reduced power stage. The bq3055 has a wake function that enables exit from Sleep mode when current flow or failure is detected. • In Shutdown Mode, the bq3055 is completely disabled. Configuration Oscillator Function The bq3055 fully integrates the system oscillators and does not require any external components to support this feature. System Present Operation The bq3055 checks the PRES pin periodically (1s). If PRES input is pulled to ground by the external system, the bq3055 detects this as system present. 2-, 3-, or 4-Cell Configuration In a 2-cell configuration, VC1 is shorted to VC2 and VC3. In a 3-cell configuration, VC1 is shorted to VC2. Cell Balancing The device supports cell balancing by bypassing the current of each cell during charging or at rest. If the device's internal bypass is used, up to 10 mA can be bypassed and multiple cells can be bypassed at the same time. Higher cell balance current can be achieved by using an external cell balancing circuit. In external cell balancing mode, only one cell at a time can be balanced. The cell balancing algorithm determines the amount of charge needed to be bypassed to balance the capacity of all cells. Internal Cell Balancing When internal cell balancing is configured, the cell balance current is defined by the external resistor RVC at the VCx input. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): bq3055 15 bq3055 SLUSA91A – OCTOBER 2010 – REVISED JANUARY 2012 www.ti.com RVC VC1 RVC VC2 RVC VC3 RVC VC4 VSS External Cell Balancing When external cell balancing is configured, the cell balance current is defined by RB. Only one cell at a time can be balanced. RVC VC1 RVC VC2 RVC VC3 RVC VC4 RB RB RB RB VSS 16 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): bq3055 bq3055 SLUSA91A – OCTOBER 2010 – REVISED JANUARY 2012 www.ti.com BATTERY PARAMETER MEASUREMENTS Charge and Discharge Counting The bq3055 uses an integrating delta-sigma analog-to-digital converter (ADC) for current measurement, and a second delta-sigma ADC for individual cell and battery voltage and temperature measurement. The integrating delta-sigma ADC measures the charge/discharge flow of the battery by measuring the voltage drop across a small-value sense resistor between the SR1 and SR2 pins. The integrating ADC measures bipolar signals from –0.25 V to 0.25 V. The bq3055 detects charge activity when VSR = V(SRP) – V(SRN) is positive, and discharge activity when VSR = V(SRP) – V(SRN) is negative. The bq3055 continuously integrates the signal over time, using an internal counter. The fundamental rate of the counter is 0.65 nVh. Voltage The bq3055 updates the individual series cell voltages at 0.25-second intervals. The internal ADC of the bq3055 measures the voltage, and scales and calibrates it appropriately. This data is also used to calculate the impedance of the cell for the CEDV gas-gauging. Current The bq3055 uses the SRP and SRN inputs to measure and calculate the battery charge and discharge current using a 5-mΩ to 20-mΩ typ. sense resistor. Auto Calibration The bq3055 provides an auto-calibration feature to cancel the voltage offset error across SRN and SRP for maximum charge measurement accuracy. The bq3055 performs auto-calibration when the SMBus lines stay low continuously for a minimum of 5 s. Temperature The bq3055 has an internal temperature sensor and inputs for two external temperature sensors. All three temperature sensor options are individually enabled and configured for cell or FET temperature. Two configurable thermistor models are provided to allow the monitoring of cell temperature in addition to FET temperature, which may be of a higher temperature type. Communications The bq3055 uses SMBus v1.1 with Master Mode and packet error checking (PEC) options per the SBS specification. SMBus On and Off State The bq3055 detects an SMBus off state when SMBC and SMBD are low for two or more seconds. Clearing this state requires that either SMBC or SMBD transition high. The communication bus will resume activity within 1 ms. SBS Commands See the bq3055 Technical Reference Manual (SLUU440) for further details. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): bq3055 17 bq3055 SLUSA91A – OCTOBER 2010 – REVISED JANUARY 2012 www.ti.com APPLICATION SCHEMATIC 18 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): bq3055 PACKAGE OPTION ADDENDUM www.ti.com 5-Jun-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) BQ3055DBT ACTIVE TSSOP DBT 30 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BQ3055DBTR ACTIVE TSSOP DBT 30 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 12-Jun-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant BQ3055DBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 BQ3055DBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 12-Jun-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) BQ3055DBTR TSSOP DBT 30 2000 346.0 346.0 33.0 BQ3055DBTR TSSOP DBT 30 2000 346.0 346.0 33.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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