MOTOROLA MC10319

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The MC10319 is an 8–bit high speed parallel flash A/D converter. The
device employs an internal Grey Code structure to eliminate large output
errors on fast slewing input signals. It is fully TTL compatible, requiring a
+ 5.0 V supply and a wide tolerance negative supply of – 3.0 to – 6.0 V.
Three–state TTL outputs allow direct drive of a data bus or common I/O
memory.
The MC10319 contains 256 parallel comparators across a precision input
reference network. The comparator outputs are fed to latches and then to an
encoder network, to produce an 8–bit data byte plus an overrange bit. The
data is latched and converted to 3–state LS–TTL outputs. The overrange bit
is always active to allow for either sensing of the overrange condition or ease
of interconnecting a pair of devices to produce a 9–bit A/D converter.
Applications include video display and radar processing, high speed
instrumentation and TV broadcast encoding.
• Internal Grey Code for Speed and Accuracy, Binary Outputs
•
•
•
•
•
•
•
•
•
HIGH SPEED
8–BIT ANALOG–TO–DIGITAL
FLASH CONVERTER
SEMICONDUCTOR
TECHNICAL DATA
P SUFFIX
PLASTIC PACKAGE
CASE 709
8–Bit Resolution/9–Bit Typical Accuracy
Easily Interconnected for 9–Bit Conversion
DW SUFFIX
PLASTIC PACKAGE
CASE 751F
(SO–28L)
3–State LS–TTL Outputs with True/Complement Enable Inputs
25 MHz Sampling Rate
Wide Input Range: 1.0 to 2.0 Vpp, between ± 2.0 V
Low Input Capacitance: 50 pF
Low Power Dissipation: 618 mW
No Sample/Hold Required for Video Bandwidth Signals
PIN CONNECTIONS
(P only)
Single Clock Cycle Conversion
VRM 1
24 VRT
GND 2
23 VRB
OVER– 3
RANGE
22 GND
Representative Block Diagram
Analog
Input
Vin
(14)
VRT
(24)
VRM
(1)
Logic
VCC(A)
(15)
Bias
256
Comparators
VEE
(13)
VCC(D)
(11, 17)
MC10319
Differential
Latch
Array
GND
(2, 12,
16, 22)
Bias
Grey Code
Translator
Output
Latches
and
ECL–TTL
Converters
D7 4
21 D0
D6 5
20 EN
D5 6
19 EN
D4 7
18 CLOCK
D3 8
17 VCC(D)
D2 9
16 GND
D1 10
15 VCC(A)
Over–
Range
(3)
D7 (4)
VCC(D) 11
14 VIN
D6 (5)
GND 12
13 VEE
D5 (6)
D4 (7)
D3 (8)
D2 (9)
ORDERING INFORMATION
D1 (10)
D0 (21)
VRB
(23)
Clock
(18)
(19)
Enable
(20)
Enable
Device
Operating
Temperature Range
MC10319DW
MC10319P
 Motorola, Inc. 1996
MOTOROLA ANALOG IC DEVICE DATA
TA = 0° to +70°C
Package
SO–28L
Plastic
Rev 0
1
MC10319
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VCC(A),(D)
VEE
+ 7.0
– 7.0
Vdc
Positive Supply Voltage Differential
VCC(D)–
VCC(A)
– 0.3 to + 0.3
Vdc
Digital Input Voltage (Pins 18 to 20)
VI(D)
– 0.5 to + 7.0
Vdc
Analog Input Voltage (Pins 1, 14, 23, 24)
VI(A)
– 2.5 to + 2.5
Vdc
Reference Voltage Span (Pin 24 to Pin 23)
–
2.3
Vdc
Applied Output Voltage (Pins 4 to 10, 21 in 3–State)
–
– 0.3 to + 7.0
Vdc
Junction Temperature
TJ
+ 150
°C
Storage Temperature
Tstg
– 65 to + 150
°C
Supply Voltage
Devices should not be operated at these values. The “Recommended Operating Limits” table provides
guidelines for actual device operation.
RECOMMENDED OPERATING LIMITS
Characteristic
Symbol
Min
Typ
Max
Unit
VCC(A)
VCC(D)
+ 4.5
+ 5.0
+ 5.5
Vdc
∆VCC
– 0.1
0
+ 0.1
Vdc
Power Supply Voltage (Pin 13)
VEE
– 6.0
– 5.0
– 3.0
Vdc
Digital Input Voltages (Pins 18 to 20)
VI(D)
0
–
+ 5.0
Vdc
Analog Input (Pin 14)
VI(A)
– 2.1
–
+ 2.1
Vdc
Voltage @ VRT (Pin 24)
VRT
– 1.0
–
+ 2.1
Vdc
Voltage @ VRB (Pin 23)
VRB
– 2.1
–
+ 1.0
Vdc
VRT – VRB
∆VR
+ 1.0
–
+ 2.1
Vdc
VRB – VEE
–
1.3
–
–
Vdc
Vo
0
–
5.5
Vdc
Clock Pulse Width – High
Clock Pulse Width – Low
tCKH
tCKL
5.0
15
20
20
–
–
ns
Clock Frequency
fCLK
0
–
25
MHz
TA
0
–
+ 70
°C
Power Supply Voltage (Pin 15)
Power Supply Voltage (Pins 11, 17)
VCC(D) – VCC(A)
Applied Output Voltage (Pins 4 to 10, 21 in 3–State)
Operating Ambient Temperature
ELECTRICAL CHARACTERISTICS (0°
t TA t 70°C, VCC = 5.0 V, VEE = – 5.2 V, VRT = +1.0 V, VRB = – 1.0 V, unless noted.)
Characteristic
Symbol
Min
Typ
Max
Unit
N
–
–
8.0
Bits
TRANSFER CHARACTERISTICS (fCKL = 25 MHz)
Resolution
Monotonicity
MON
Guaranteed
Bits
Integral Nonlinearity
INL
–
± 1/4
± 1.0
LSB
Differential Nonlinearity
DNL
–
–
± 1.0
LSB
DP
–
1
–
Deg.
DG
–
1
–
Differential Phase (See Figure 16)
Differential Gain (See Figure 16)
Power Supply Rejection Ratio
(4.5 V
VCC
5.5 V, VEE = – 5.2 V)
(– 6.0 V
VEE
– 3.0 V, VCC = + 5.0 V)
t t
t t
2
PSRR
%
LSB/V
–
–
0.1
0
–
–
MOTOROLA ANALOG IC DEVICE DATA
MC10319
ELECTRICAL CHARACTERISTICS – continued
(0°
t TA t 70°C, VCC = 5.0 V, VEE =
– 5.2 V, VRT = +1.0 V, VRB = – 1.0 V, unless otherwise noted.)
Characteristic
Symbol
Min
Input Current @ Vin = VRB (See Figure 5)
IINL
– 100
Input Current @ Vin = VRT (See Figure 5)
IINH
–
Input Capacitance (VRT – VRB = 2.0 V, See Figure 4)
Cin
–
Input Capacitance (VRT – VRB = 1.0 V, See Figure 4)
Cin
Typ
Max
Unit
0
–
µA
60
150
µA
36
–
pF
–
55
–
pF
VOS
–
0.1
–
LSB
Ladder Resistance (VRT to VRB, TA = 25°C)
Rref
104
130
156
Ω
Temperature Coefficient
TC
–
+ 0.29
–
%/°C
Ladder Capacitance (Pin 1 open)
Cref
–
25
–
pF
Input Voltage – High (Pins 19 to 20)
VIHE
2.0
–
–
V
Input Voltage – Low (Pins 19 to 20)
VILE
–
–
0.8
V
Input Current @ 2.7 V
IIHE
–
0
20
µA
IIL1
– 400
– 100
–
µA
Input Current @ 0.4 V @ EN (EN = 0 V)
IIL2
– 400
– 100
–
µA
Input Current @ 0.4 V @ EN (EN = 2.0 V)
IIL3
– 20
– 2.0
–
µA
VIKE
– 1.5
– 1.3
–
V
Input Voltage High
VIHC
2.0
–
–
Vdc
Input Voltage Low
VILC
–
–
0.8
Vdc
Input Current @ 0.4 V (See Figure 7)
IILC
– 400
– 80
–
µA
Input Current @ 2.7 V (See Figure 7)
IIHC
– 100
– 20
–
µA
Input Clamp Voltage (IIK = – 18 mA)
VIKC
– 1.5
– 1.3
–
Vdc
High Output Voltage (IOH = – 400 µA, VCC = 4.5 V, See Figure 8)
VOH
2.4
3.0
–
V
Low Output Voltage (IOL = 4.0 mA, See Figure 9)
VOL
–
0.35
0.4
V
Output Short Circuit Current* (VCC = 5.5 V)
ISC
–
35
–
mA
Output Leakage Current (0.4
VO
2.4 V, See Figure 3,
VCC = 5.5 V, D0 to D7 in 3–State Mode)
ILK
– 50
–
+ 50
Cout
–
9.0
–
pF
VCC(A) Current (4.5 V
ICC(A)
10
17
25
mA
VCC(D) Current (4.5 V
ICC(D)
50
90
133
mA
IEE
– 14
– 10
– 6.0
mA
PD
–
618
995
mW
ANALOG INPUTS (Pin 14)
Bipolar Offset Error
REFERENCE
ENABLE INPUTS (VCC = 5.5 V) (See Figure 6)
Input Current @ 0.4 V @ EN (0
t EN t 5.0 V)
Input Clamp Voltage (IIK = – 18 mA)
CLOCK INPUTS (VCC = 5.5 V)
DIGITAL OUTPUTS
t t
Output Capacitance (D0 to D7 in 3–State Mode)
µA
*Only one output is to be shorted at a time, not to exceed 1 second.
POWER SUPPLIES
t VCC(A) t 5.5 V) (Outputs unloaded)
t VCC(D) t 5.5 V) (Outputs unloaded)
VEE Current (– 6.0 t VEE t – 3.0 V)
Power Dissipation (VRT – VRB = 2.0 V) (Outputs unloaded)
MOTOROLA ANALOG IC DEVICE DATA
3
MC10319
TIMING CHARACTERISTICS (TA = 25°C, VCC = + 5.0 V, VEE = – 5.2 V, VRT = + 1.0 V, VRB = – 1.0 V,
see System Timing Diagram, Figure 1.)
Characteristic
Symbol
Min
Typ
Max
Unit
Min Clock Pulse Width – High
tCKH
–
5.0
–
ns
Min Clock Pulse Width – Low
tCKL
–
15
–
ns
Max Clock Rise, Fall Time
tR,F
–
100
–
ns
Clock Frequency
fCLK
0
30
25
MHz
tCKDV
–
19
–
ns
tAD
–
4.0
–
ns
tH
–
6.0
–
ns
Data High to 3–State from Enable Low*
tEHZ
–
27
–
ns
Data Low to 3–State from Enable Low*
tELZ
–
18
–
ns
Data High to 3–State from Enable High*
tEHZ
–
32
–
ns
Data Low to 3–State from Enable High*
tELZ
–
18
–
ns
Valid Data from Enable High (Pin 20 = 0 V)*
tEDV
–
15
–
ns
Valid Data from Enable Low (Pin 19 = 5.0 V)*
tEDV
–
16
–
ns
ttr
–
8.0
–
ns
INPUTS
OUTPUTS
New Data Valid from Clock Low
Aperture Delay
Hold Time
Output Transition Time* (10% to 90%)
*See Figure 2 for output loading.
PIN FUNCTION DESCRIPTION
Pin
4
F
Function
i
P Suffix
DW Suffix
D
Description
i i
VRM
1
1
GND
2, 12
16, 22
2, 13, 17
18, 25, 26
OVR
3
3
D7–D0
4 to 10, 21
4 to 10, 24
VCC(D)
11, 17
11, 12
19, 20
VEE
13
14
Negative power supply. Nominally – 5.2 V, it can range from – 3.0 to – 6.0 V, and must
be more negative than VRB by 1.3 V. Reference to analog ground.
Vin
14
15
Signal voltage input. This voltage is compared to the reference to generate a digital
equivalent. Input impedance is nominally 16 to 33K in parallel with 36 pF.
VCC(A)
15
16
Power supply for the analog section. + 5.0 V, ± 10% required. Reference to analog
ground.
CLK
18
21
Clock input. TTL compatible.
EN
19
22
Enable input. TTL compatible, a logic 1 (and EN at a logic 0) enables the data outputs.
A logic 0 puts the outputs in a 3–state mode.
EN
20
23
Enable input. TTL compatible, a logic 0 (and EN at a logic 1) enables the data outputs.
A logic 1 puts the outputs in a 3–state mode.
VRB
23
27
The bottom (most negative point) of the internal reference resistor ladder.
VRT
24
28
The top (most positive point) of the internal reference resistor ladder.
The midpoint of the reference resistor ladder. Bypassing can be done at this point to
improve performance at high frequencies.
Digital ground. The pins should be connected directly together, and through a low
impedance path to the power supply.
Overrange output. Indicates Vin is more positive than VRT 1/2 LSB. This output does
not have 3–state capability.
Digital Outputs. D7 (Pin 4) is the MSB. D∅ (Pin 21 or 24) is the LSB. LS–TTL
compatible with 3–state capability.
Power supply for the digital section. + 5.0 V, ± 10% required. Reference to digital
ground.
u
MOTOROLA ANALOG IC DEVICE DATA
MC10319
Figure 1. System Timing Diagram
tCKH
tCKL
3.0 V
Clock
1.5 V
1.5 V
1.5 V
1.5 V
tAD
Vin
tAD
Sample 1
Sample 2
tCKDV
tH
Old Data
D7–D0, OR
Sample 1
Sample 2
tCKDV and tH measured at output levels of 0.8 and 2.4 V.
3.0 V
EN
0.9 V
0.9 V
3.0 V
EN
0.9 V
tEHZ
tEDV
tEDV
tEDV
High Data
Output
0.9 V
2.4 V
2.4 V
0.5 V
0.5 V
tEDV
tELZ
Low Data
Output
0.8 V
tEDV
0.8 V
0.4 V
Figure 2. Data Output Test Circuit
Figure 3. Output 3–State Leakage Current
200
D0 – D7
3.0 kΩ
Diodes = 1N914 or equivalent, C1 ≈ 15 pF
MOTOROLA ANALOG IC DEVICE DATA
LEAKAGE CURRENT ( µA)
VCC
1.0 kΩ
0.4 V
Outputs
Active
3–State
C1
tEDV
100
50
0
– 50
– 100
– 200
– 1.0
Pin 19 = 0 V
0
1.0
0°C
t TA t 70°C
2.0
3.0
4.0
APPLIED VOLTAGE (VOLTS)
5.0
6.0
7.0
5
MC10319
Figure 4. Input Capacitance @ Vin (Pin 14)
Figure 5. Input Current @ Vin (Pin 14)
100
80
Iin, INPUT CURRENT (µ A)
25°C
C, CAPACITANCE (pF)
80
60
VRT – VRB = 1.0 V
40
VRT – VRB = 2.0 V
0°C
60
70°C
40
20
0
0.1 V
20
VRT
VRB
– 2.5
VRB
Vin, INPUT VOLTAGE (VOLTS)
Vin, INPUT VOLTAGE (VOLTS)
Figure 6. Input Current @ Enable, Enable
Figure 7. Clock Input Current
10
0
– 10
40
20
Iin, INPUT CURRENT (µ A)
Iin, INPUT CURRENT (µ A)
+ 2.5
VRT
– 30
Pin 19 Current
2 V < Pin 20 < 5 V
– 50
Pin 19 (Pin 20 = 0 V)
Pin 20 (0 < Pin 19 < 5 V)
– 70
+ 70°C
– 90
– 20
– 40
70°C
– 60
25°C
– 80
0°C
25°C
– 110
0
– 100
0°C
– 130
– 120
0
2.0
1.0
5.5
0
1.0
2.0
Vin, INPUT VOLTAGE (VOLTS)
3.0
4.0
5.0
6.0
Vin, INPUT VOLTAGE (VOLTS)
Figure 8. Output Voltage versus Output Current
Figure 9. Output Voltage versus Output Current
VOL, OUTPUT VOLTAGE (VOLTS)
VOH ,OUTPUT VOLTAGE (VOLTS)
0.5
5.0
4.0
3.0
0° and 70°C
25°C
0.3
0.2
0.1
4.5 V < VCC < 5.5 V
0
0
– 100
– 200
– 300
IOH, OUTPUT CURRENT (µA)
6
0.4
– 400
0
2.0
4.0
6.0
8.0
IOL, OUTPUT CURRENT (mA)
MOTOROLA ANALOG IC DEVICE DATA
MC10319
Figure 11. Supply Current versus Temperature
–12
112
IEE, SUPPLY CURRENT, PIN 13 (mA)
ICC , SUPPLY CURRENT, PINS 11, 15, 17 (mA)
Figure 10. Supply Current versus Temperature
110
108
106
–11
–10
–9.0
104
VCC = 5.0 V
102
VEE = – 5.2 V
–8.0
0
20
40
60
TA, AMBIENT TEMPERATURE (°C)
70
0
20
40
60
TA, AMBIENT TEMPERATURE (°C)
Figure 12. Differential Linearity Error
Figure 13. Integral Linearity Error
1/2
LSB
1/2
LSB
0
0
– 1/2
LSB
– 1/2
LSB
VRT = 2.0 V, VRB = 0 V
Fs = 25 MHz
0
32
64
VRT = 2.0 V, VRB = 0 V
Fs = 25 MHz
96
128
160
192
224
0
256
32
Figure 14. Differential Linearity Error
1/2
LSB
0
0
– 1/2
LSB
– 1/2
LSB
VRT = 2.0 V, VRB = 0 V
Fs = 12.5 MHz
32
64
64
96
128
160
192
224
256
224
256
Figure 15. Integral Linearity Error
1/2
LSB
0
70
VRT = 2.0 V, VRB = 0 V
Fs = 12.5 MHz
96
128
160
MOTOROLA ANALOG IC DEVICE DATA
192
224
256
0
32
64
96
128
160
192
7
MC10319
DESIGN GUIDELINES
Introduction
Reference
The MC10319 is a high speed, 8–bit, parallel (“flash”) type
analog–to–digital converter containing 256 comparators at
the front end. See Figure 17 for a block diagram. The
comparators are arranged such that one input of each is
referenced to evenly spaced voltages, derived from the
reference resistor ladder. The other input of the comparators
is connected to the input signal (Vin). Some of the
comparator′s differential outputs will be “true,” while other
comparators will have “not true” outputs, depending on their
relative position. Their outputs are then latched, and
converted to an 8–bit Grey code by the Differential Latch
Array. The Grey code ensures that any input errors due to
cross talk, feed–thru, or timing disparities result in glitches at
the output of only a few LSBs, rather than the more traditional
1/2 scale and 1/4 scale glitches.
The Grey code is then translated to an 8–bit binary code,
and the differential levels are translated to TTL levels before
being applied to the output latches. Enable inputs at this final
stage permit the TTL outputs (except overrange) to be put
into a high impedance (3–state) condition.
The reference resistor ladder is composed of a string of
equal value resistors to provide 256 equally spaced voltages
for the comparators (see Figure 17 for the actual
configuration). The voltage difference between adjacent
comparators corresponds to 1 LSB of the input range. The
first comparator (closest to VRB) is referenced 1/2 LSB above
VRB, and 256th comparator (for the overrange) is referenced
1/2 LSB below VRT. The total resistance of the ladder is
nominally 130 Ω, ± 20%, requiring 15.4 mA @ 2.0 V, and
7.7 mA @ 1.0 V. There is a nominal warm–up change of
≈ + 9.0% in the ladder resistance due to the + 0.29%/°C
temperature coefficient.
The minimum recommended span [VRT – VRB] is 1.0 V. A
lower span will allow offsets and nonlinearities to become
significant. The maximum recommended span is 2.1 V due to
power limitations of the resistor ladder. The span may be
anywhere within the range of – 2.1 to + 2.1 V with respect to
ground, and VRB must be at least 1.3 V more positive than
VEE. The reference voltages must be stable and free of noise
and spikes, since the accuracy of a conversion is directly
related to the quality of the reference.
In most applications, the reference voltages will remain
fixed. In applications involving a varying reference for
modulation or signal scrambling, the modulating signal may
be applied to VRT, or VRB, or both. The output will vary
inversly with the reference signal, introducing a nonlinearity
into the transfer function. The addition of the modulating
signal and the dc level applied to the reference must be such
that the absolute voltage at VRT and VRB is maintained within
the values listed in the Recommended Operating Limits. The
RMS value of the span must be maintained 2.1 V.
VRM (Pin 1) is the midpoint of the resistor ladder, excluding
the Overrange comparator. The voltage at VRM is:
ANALOG SECTION
Signal Input
The signal voltage to be digitized (Vin) is applied
simultaneously to one input of each of the 256 comparators
through Pin 14. The other inputs of the comparators are
connected to 256 evenly spaced voltages derived from the
reference ladder. The output code depends on the relative
position of the input signal and the reference voltages. The
comparators have a bandwidth of 50 MHz, which is more
than sufficient for the allowable (Nyquist Theorem) input
frequency of 12.5 MHz.
The current into Pin 14 varies linearly from 0 (when
Vin = VRB) to ≈60 µA (when Vin = VRT). If Vin is taken below
VRB or above VRT, the input current will remain at the value
corresponding to VRB and VRT respectively (see Figure 5).
However, Vin must be maintained within the absolute range of
± 2.5 V (with respect to ground) – otherwise excessive
currents will result at Pin 14, due to internal clamps.
The input capacitance at Pin 14 is typically 36 pF if
[VRT – VRB] is 2.0 V, and increases to 55 pF if [VRT – VRB]
is reduced to 1.0 V (see Figure 4). The capacitance is
constant as Vin varies from VRT down to ≈0.1 V above VRB.
Taking Vin to VRB will show an increase in the capacitance of
≈50%. If Vin is taken above VRT, or below VRB, the
capacitance will stay at the values corresponding to VRT
and VRB, respectively.
The source impedance of the signal voltage should be
maintained below 100 Ω (at the frequencies of interest) in
order to avoid sampling errors.
u
8
p
V
RT
) VRB * 1ń2 LSB
2.0
In most applications, bypassing this pin to ground (0.1 µF) is
sufficient to maintain accuracy. In applications involving very
high frequencies, and where linearity is critical, it may be
necessary to trim the voltage at the midpoint. A means for
accomplishing this is indicated in Figure 18.
Power Supplies
VCC(A) is the positive power supply for the comparators,
and VCC(D) is the positive power supply for the digital portion.
Both are to be + 5.0 V, ± 10%, and the two are to be within
100 mV of each other. There is indirect internal coupling
between VCC(D) and VCC(A). If they are powered separately,
and one supply fails, there will be current flow through the
MC10319 to the failed supply.
MOTOROLA ANALOG IC DEVICE DATA
MC10319
ICC(A) is nominally 17 mA, and does not vary with clock
frequency or with Vin. It does vary linearly with VCC(A). ICC(D)
is nominally 90 mA, and is independent of clock frequency. It
does vary, however, by 6 to 7 mA as Vin is changed, with the
lowest current occurring when Vin = VRT. It varies linearly
with VCC(D).
VEE is the negative power supply for the comparators,
and is to be within the range – 3.0 to – 6.0 V. Additionally,
VEE must be at least 1.3 V more negative than VRB. IEE is a
nominal – 10 mA, and is independent of clock frequency, Vin,
and VEE.
For proper operation, the supplies must be bypassed at
the IC. A 10 µF tantalum, in parallel with a 0.1 µF ceramic is
recommended for each supply to ground.
DIGITAL SECTION
Clock
The Clock input is TTL compatible with a typical
frequency range of 0 to 30 MHz. There is no duty cycle
limitations, but the minimum low and high times must be
adhered to. See Figure 7 for the input current requirements.
The conversion sequence is shown in Figure 19, and is
as follows:
• On the rising edge, the data output latches are latched
with old data, and the comparator output latches are
released to follow the input signal (Vin).
• During the high time, the comparators track the input
signal. The data output latches retain the old data.
• On the falling edge, the comparator outputs are latched
with the data immediately prior to this edge. The
conversion to digital occurs within the device, and the
data output latches are released to indicate the new data
within 20 ns.
• During the clock low time, the comparator outputs remain
latched, and the data output latches remain transparent.
A summary of the sequence is that data present at Vin
just prior to the Clock falling edge is digitized and
available at the data outputs immediately after that same
falling edge.
The comparator output latches provide the circuit with an
effective sample–and–hold function, eliminating the need for
an external sample–and–hold.
Enable Inputs
The two Enable inputs are TTL compatible, and are used
to change the data outputs (D7–D0) from active to 3–state.
This capability allows cascading two MC10319s into a 9–bit
configuration, flip–flopping two MC10319s into a 50 MHz
configuration, connecting the outputs directly to a data bus,
multiplexing multiple converters, etc. See the Applications
Information section for more details. For the outputs to be
active, Pin 19 must be a Logic “1”, and Pin 20 must be a Logic
“0”. Changing either input will put the outputs into the high
impedance mode. The Enable inputs affect only the state
of the outputs – they do not inhibit a conversion. The input
current into Pins 19 and 20 is shown in Figure 6, and the
input/output timing is shown in Figure 1 and 20. Leaving
either pin open is equivalent to a Logic “1”, although good
design practice dictates that an input should never be
left open.
The Overrange output (Pin 3) is not affected by the Enable
inputs as it does not have 3–state capability.
Outputs
The Data outputs are TTL level outputs with high
impedance capability. Pin 4 is the MSB (D7), and Pin 21 is the
LSB (D0). The eight outputs are active as long as the Enable
inputs are true (Pin 19 = high, Pin 20 = low). The timing of the
outputs relative to the Clock input and the Enable inputs is
shown in Figures 1 and 20. Figures 8 and 9 indicate the
output voltage versus load current, while Figure 3 indicates
the leakage current when in the high impedance mode.
The output code is natural binary, depicted in the
table below.
The Overrange output (Pin 3) goes high when the input,
Vin, is more positive than VRT – 1/2 LSB. This output is
always active – it does not have high impedance capability.
Besides being used to indicate an input overrange, it is
additionally used for cascading two MC10319s to form a
9–bit A/D converter (see Figure 27).
Table 1. Output Code
VRT, VRB (V)
I
Input
uVRT – 1/2 LSB
VRT – 1/2 LSB
VRT – 1 LSB
VRT – 1–1/2 LSB
Midpoint
VRB + 1/2 LSB
VRB
t
2.048 V, 0 V
+ 1.0 V, – 1.0 V
+ 1.0 V, 0 V
Output
Code
O
Overrange
2.044 V
2.040 V
2.036 V
1.024 V
4.0 mV
0V
0.9961 V
0.992 V
0.988 V
0.000 V
– 0.9961 V
– 1.0 V
0.9980 V
0.9961 V
0.9941 V
0.5000 V
1.95 mV
0V
FFH
FFH
FFH
FEH ↔ FFH
80H
00H ↔ 01H
00H
1
0↔1
0
0
0
0
0
u2.044V
MOTOROLA ANALOG IC DEVICE DATA
t
u0.9961 V
t
u0.9980 V
t
9
MC10319
APPLICATIONS INFORMATION
Power Supplies, Grounding
The PC board layout, and the quality of the power supplies
and the ground system at the IC are very important in order
to obtain proper operation. Noise, from any source, coming
into the device on VCC, VEE, or ground can cause an
incorrect output code due to interaction with the analog
portion of the circuit. At the same time, noise generated
within the MC10319 can cause incorrect operation if that
noise does not have a clear path to ac ground.
Both the VCC and VEE power supplies must be decoupled
to ground at the IC (within 1I max) with a 10 µF tantalum and
a 0.1 µF ceramic. Tantalum capacitors are recommended
since electrolytic capacitors simply have too much
inductance at the frequencies of interest. The quality of the
VCC and VEE supplies should then be checked at the IC with
a high frequency scope. Noise spikes (always present when
digital circuits are present) can easily exceed 400 mV peak,
and if they get into the analog portion of the IC, the operation
can be disrupted. Noise can be reduced by inserting resistors
and/or inductors between the supplies and the IC.
If switching power supplies are used, there will usually be
spikes of 0.5 V or greater at frequencies of 50 to 200 kHz.
These spikes are generally more difficult to reduce because
of their greater energy content. In extreme cases, 3–terminal
regulators (MC78L05ACP, MC7905.2CT), with appropriate
high frequency filtering, should be used and dedicated to
the MC10319.
The ripple content of the supplies should not allow their
magnitude to exceed the values in the Recommended
Operating Limits table.
The PC board tracks supplying VCC and VEE to the
MC10319 should preferably not be at the tail end of the bus
distribution, after passing through a maze of digital circuitry.
The MC10319 should be close to the power supply, or the
connector where the supply voltages enter the board. If the
VCC and VEE lines are supplying considerable current to
other parts of the boards, then it is preferable to have
dedicated lines from the supply or connector directly to
the MC10319.
The four ground pins (2, 12, 16, and 22) must be
connected directly together. Any long path between them can
cause stability problems due to the inductance (at 25 MHz) of
the PC tracks. The ground return for the signal source must
be noise free.
Reference Voltage Circuits
Since the accuracy of the conversion is directly related to
the quality of the references, it is imperative that accurate and
stable voltages be provided to VRT and VRB. If the reference
span is 2.0 V, then 1/2 LSB is only 3.9 mV, and it is desireable
that VRT and VRB be accurate to within this amount, and
furthermore, that they do not drift more than this amount once
10
set. Over the temperature range of 0° to 70°C, a maximum
temperature coefficient of 28 ppm/°C is required.
The voltage supplies used for digital circuits should
preferably not be used as a source for generating VRT and
VRB, due to the noise spikes (50 to 400 mV) present on the
supplies and on their ground lines. Generally ± 15 V, or
± 12 V, are available for analog circuits, and are usually
clean compared to supplies used for digital circuits,
although ripple may be present in varying amounts. Ripple
is easier to filter out than spikes, however, and so these
supplies are preferred.
Figure 21 depicts a circuit which can provide an
extremely stable voltage to VRT at the current required
(the maximum reference current is 19.2 mA @ 2.0 V). The
MC1403 series of reference sources has very low
temperature coefficients, good noise rejection, and a high
initial accuracy, allowing the circuit to be built without an
adjustment pot if the VRT voltage is to remain fixed at one
value. Using 0.1% wirewound resistors for the divider
provides sufficient accuracy and stability in many cases.
Alternately, resistor networks provide high ratio accuracies,
and close temperature tracking. If the application requires
VRT to be changed periodically, the two resistors can be
replaced with a 20 turn, cermet potentiometer. Wirewound
potentiometers should not be used for this type of
application since the pot’s slider jumps from winding to
winding, and an exact setting can be difficult to obtain.
Cermet pots allow for a smooth continuous adjustment.
In Figure 21, R1 reduces the power dissipation in the
transistor, and can be carbon composition. The 0.1 µF
capacitor in the feedback path provides stability in the unity
gain configuration. Recommended op amps are: LM358,
MC34001 series, LM308A, LM324, and LM11C. Offset drift is
the key parameter to consider in choosing an op amp, and
the LM308A has the lowest drift of those mentioned. Bypass
capacitors are not shown in Figure 21, but should always be
provided at the input to the 2.5 V reference, and at the power
supply pins of the op amp.
Figure 22 shows a simpler and more economical circuit,
using the LM317LZ regulator, but with lower initial accuracy
and temperature stability. The op amp/current booster is not
needed since the LM317LZ can supply the current directly. In
a well controlled environment, this circuit will suffice for many
applications. Because of the lower initial accuracy, an
adjustment pot is a necessity.
Figure 23 shows two circuits for providing the voltage to
VRB. The circuits are similar to those of Figures 21 and 22,
and have similar accuracy and stability. The output
transistor is a PNP in this case since the circuit must sink the
reference current.
MOTOROLA ANALOG IC DEVICE DATA
MC10319
VIDEO APPLICATIONS
symmetrical about ground (e.g., ± 1.0 V), the adjustment can
be eliminated, and the midpoint connected to ground. The
use of latches on the outputs is optional, depending on
the application.
The MC10319 is suitable for digitizing video signals
directly without signal conditioning, although the standard
1.0 Vpp video signal can be amplified to a 2.0 Vpp signal for
slightly better accuracy. Figure 24 shows the input (top
trace) and reconstructed output of a standard NTSC test
signal, sampled at 25 MSPS, consisting of a sync pulse,
3.58 MHz color burst, a 3.58 MHz signal in a Sin2x
envelope, a pulse, a white level signal, and a black level
signal. Figure 25 shows a Sin2x pulse that has been
digitized and reconstructed at 25 MSPS. The width of the
pulse is ≈450 ns at the base. Figure 26 shows an application
circuit for digitizing video.
50 MHz, 8–Bit A/D Converter
Figure 28 shows how two MC10319s can be connected
together in a flip–flop arrangement in order to have an
effective conversion speed of 50 MHz. The 74F74 D–type
flip–flop provides a 25 MHz clock to each converter, and at
the same time, controls the Enables so as to alternately
enable and disable the outputs. The Overranges do not have
3–state capability, and so cannot be paralleled. Instead they
are OR’d together. The use of latches is optional, and
depends on the application. Data should be latched, or
written to RAM (in a DMA operation), on the high–to–low
transition of the 50 MHz clock.
9–Bit A/D Converter
Figure 27 shows how two MC10319s can be connected to
form a 9–bit converter. In this configuration, the outputs
(D7 to D0) of the two 8–bit converters are paralleled. The
outputs of one device are active, while the outputs of the
other are in the 3–state mode. The selection is made by the
Overrange output of the lower MC10319, which controls
Enable inputs on the two devices. Additionally, this output
provides the 9th bit.
The reference ladders are connected in series, providing
the 512 steps required for 9 bits. The input voltage range is
determined by VRT of the upper MC10319, and VRB of the
lower device. A minimum of 1.0 volt is required across each
converter. The 500 Ω pot (20 turn cermet) allows for
adjustment of the midpoint since the reference resistors of
the two MC10319s may not be identical in value. Without the
adjustment, a non–equal voltage division would occur,
resulting in a nonlinear conversion. If the references are to be
Negative Voltage Regulator
In the cases where a negative power supply is not
available (neither the – 3.0 to – 6.0 V, nor a higher negative
voltage from which to derive it), the circuit of Figure 29 can be
used to generate – 5.0 V from the + 5.0 V supply. The PC
board space required is small (≈ 2.0 in2), and it can be
located physically close to the MC10319. The MC34063A is
a switching regulator, and in Figure 29 is configured in an
inverting mode of operation. The regulator operating
specifications are also given.
Figure 16. Differential Phase and Gain Test
Video
Signal
(See Below)
MC10319
DUT
8
74F374
Latch
HDS–1250
12–Bit D/A
8
D3
1.024 Vpp
to
Analyzer
D0
Clock
VRT
120
100
571.4 mV
(40 IRE)
80
60
40
285.7 mV
2.000 V
1.429 V
(100 IRE)
20
0
– 20 IRE
VRB
Video Input Signal
1.
2.
3.
4.
Input waveform: 571.4 mVpp, sine wave @ 3.579545 MHz, dc levels as shown above.
MC10319 clock at 14.31818 MHz (4x) asynchronous to input.
Differential gain: peak–to–peak output @ each IRE level compared to that at 0 IRE.
Differential phase: Phase @ each IRE level compared to that @ 0 IRE.
MOTOROLA ANALOG IC DEVICE DATA
11
MC10319
Figure 17. Representative Block Diagram
( + 5.0 V )
VCC(A)
24
VRT
R/2
15
23
VRB
( + 5.0 V )
VCC(D)
11,17
256
R
ECL-to-TTL
Converter
and
Latches
255
R
254
Vin
VRT
R
14
VRB
R
129
R
VRM
1
0.1
128
D
I
F
F
E
R
E
N
T
I
A
L
L
A
T
C
H
3 OR
3
Grey
Code
Grey
Code
to
Binary
Converter
S
T
A
T
E
C
I
R
C
U
I
T
Binary
4
D7
5
D6
6
D5
7
D4
8
D3
9
D2
10
D1
21
D0
TTL
Outputs
A
R
R
A
Y
R
R
3
R
Reference
Resistor
Ladder
R
2
+ 130256W
+ 0.508 W
R
R/2
1
13
2,12,16, 22
VEE
(– 3.0 to – 6.0 V)
20
Enable
Clock
(0 to 25 MHz)
12
19
18
Enable
MOTOROLA ANALOG IC DEVICE DATA
MC10319
Figure 18. Adjusting VRM for Improved Linearity
Figure 21. Precision VRT Voltage Source
R1 = 100 Ω for + 5.0 V
R1 = 620 Ω for + 15 V
+ 5.0 V
10 µF
0.1
+ 5.0 V
VCC(A)
EN
VCC(D)
+ 5.0 to + 40 V
EN
In
2.5 V
Reference
(See Table)
MC10319
25 MHz
Clock
VRT
500 Ω
CLK
OR
VRT
D7
Output
Data
VRM
0.1
VRB
R1
0.1
GND
1.5 k
+
D0
VRB
Input
Signal
Out
1.0
kΩ
or
2N2222A
–
to
VRT
620
2.0 kΩ
0.1
Vin
VEE
GND
– 5.2 V
10 µF
2.5 V References
0.1
MC1403
MC1403A
0.5 mV
0.5 mV
40
25
7.0 mV
4.4 mV
± 1%
± 1%
Line Regulation
TC (ppm/°C) max
∆Vout for 0 to + 70°C
Initial Accuracy
Figure 19. Conversion Sequence
Clock
Figure 22. Voltage Source for VRT Pin
Comparator outputs latched.
(Valid data available after tCKDV)
+ 5.0 to
+ 40 V
10 µF
In
LM317LZ
Adj.
1.25 to 2.00 V
Out
240
to VRT
1.0 µF
Latches Comparator outputs,
opens data output latches.
Data outputs latched, releases
Comparator Latches.
510
200
LM317LZ
Figure 20. Enable to Output Critical Timing
EN
0.9 V
12
D0 – D7
TC (ppm/°C) max
0.9 V
21
∆Vout for 0 to + 70°C
Initial Accuracy
D0 – D7
EN
Line Regulation
1.0 mV
60
8.4 mV
± 4%
3–State
0.9 V
12
0.9 V
16
Valid Data
Timing @ D7 to D0 measured where waveform starts to change.
Indicated time values are typical @ 25_C, and are in ns.
MOTOROLA ANALOG IC DEVICE DATA
13
MC10319
Figure 23. Voltage Sources for VRB Pin
0.1
620
2.5 V
Regulator
1.0
kΩ
2.0
kΩ
LM337MT
10 µF
–
+
OR
In
to
VRB
2N2907A
100
Adj.
Out (– 1.25 to – 2.00 V)
120
to VRB
1.0 µF
270
1.5
kΩ
R1
–2.5 V
– 5.0
to
– 40 V
– 5.0 to
– 40 V
0.1
R2
2.5 V Reference
R1 = 100 Ω for – 5.0 V
R1 = 620 Ω for – 15 V
Line Regulation
TC (ppm/°C) max
R2 = 620 Ω for – 5.0 V
R1 = 3.0 kΩ for – 15 V
∆ Vout for 0 to + 70°C
Initial Accuracy
LM337MT
1.0 mV
48
6.7 mV
± 4%
Figure 24. Composite Video Waveform
500 mV
INPUT
OUTPUT
5.0 µs
200 mV
Figure 25. SIN2 x Waveform
500 mV
INPUT
OUTPUT
200 mV
14
100 ns
MOTOROLA ANALOG IC DEVICE DATA
MC10319
Figure 26. Application Circuit for Digitizing Video
+ 5.0 V
10 µF
0.1
14.3 MHz Clock
+ 5.0 V
VCC(A)
EN
+ 15 V
+ 2.5 V
Regulator
EN
620 Ω
1/2 W
1.5 kΩ
+
–
0.1
A1
1.0 kΩ
2N2222A
+ 1.0 V
620
VRT
– 1.0 V
620
–
A1
+
3.0 kΩ
D7
Output
Data
D0
VRB
2N2907A
Vin
1.5 kΩ
0.1
OR
MC10319
VRM
0.1
1.0 kΩ
CLK
Iref
0.1
0.1
– 2.5 V
Regulator
VCC(D)
620 Ω
1/2 W
– 2.5 V
VEE
GND
– 5.2 V
10 µF
0.1
– 15 V
MC34080
2.0 kΩ
+
–
0.01
Offset
1.0 kΩ
1.0 kΩ
3.0 pF
1.0 kΩ
Video Input
(1.0 Vpp)
u10 µF
2.0 kΩ
–
25 Ω
+
MC34080
50 Ω
NOTES: 1)
2)
3)
4)
5)
MC34080is powered from ± 15 V supplies. MC34083 (Dual) may be used.
Bypass capacitors required at power supply pins of all ICs.
Ground plane required over all parts of circuit board.
Care in layout around MC34080is necessary for good frequency response.
A1 = MC34002.
MOTOROLA ANALOG IC DEVICE DATA
15
MC10319
Figure 27. 9–Bit A/D Converter
GND
0 to 25 MHz
Clock
+ 2.0 V
0.1
EN
OR
CLK
D7
MC10319
VRT
VRM
D0
VRB
EN
+ 5.0 V
Vin V
EE VCC(D) VCC(A)
500 Ω
10 µF
0.1
0.1
– 5.2 V
CLK
VEE VCC(D) VCC(A)
0.1
VRB
OR
D8
D7
D7
D0
D0
MC10319
Vin
+ 5.0 V
EN
GND
16
OR
EN
CLK
Vin
0.1
VRT
VRM
– 2.0 V
10 µF
Latches
(Optional)
MOTOROLA ANALOG IC DEVICE DATA
MC10319
Figure 28. 50 MHz 8–Bit A/D Converter
GND
50 MHz
Clock
CK
D
74F74
Q
EN
Q
CLK
+ 1.0 V
0.1
VRT
EN
OR
D7
MC10319
(#1)
VRM
D0
VRB
+ 5.0 V
Vin
VEE
VCC(D) VCC(A)
10 µF
0.1
– 5.2 V
10 µF
VCC(D) VCC(A)
EN VEE
VRT
0.1
74F32
VRM
OR
0.1
OR
VRB
– 1.0 V
MC10319
CLK
(#2)
D7
D7
D0
D0
Vin
Vin
EN
+ 5.0 V
GND
Latches
(Optional)
50 MHz Clock
Q
D0 – D7 (#1)
Valid Data
D0 – D7 (#2)
Figure 29. – 5.0 V Regulator
Vin
(4.5 to
5.5 V)
Test
Line Regulation
2.2 Ω
100 µF
Load Regulation
6
7
8
1
2
MC34063A
5
3
470 pF
3.0 kΩ
540 µH
4
Conditions
t t 5.5 V,
Vin = 5.0 V, 8.0 mA t
Iout t 20 mA
4.5 V
Vin
Iout = 10 mA
Output Ripple
Vin = 5.0 V, Iout = 20 mA
Short Circuit Iout
Vin = 5.0 V, R1 = 0.1 Ω
Efficiency
Vin = 5.0 V, Iout = 50 mA
Results
0.16%
0.4%
2.0 mVpp
140 mA
52%
1N5819
1.0 kΩ
470 µF
1.0 µH
MOTOROLA ANALOG IC DEVICE DATA
Vout
– 5.0 V/20 mA
470 µF
17
MC10319
GLOSSARY
Aperture Delay – The time difference between the sampling
signal (typically a clock edge) and the actual analog signal
converted. The actual signal converted may occur before or
after the sampling signal, depending on the internal
configuration of the converter.
Bipolar Input – A mode of operation whereby the analog
input (of an A/D), or output (of a DAC), includes both
negative and positive values. Examples are – 1.0 to + 1.0 V,
– 5.0 to + 5.0 V, – 2.0 to + 8.0 V, etc.
Bipolar Offset Error – The difference between the actual
and ideal locations of the 00H to 01H transition, where the
ideal location is 1/2 LSB above the most negative
reference voltage.
Load Regulation – The ability of a voltage regulator to
maintain a certain output voltage as the load current is varied.
The error is typically expressed as a percent of the nominal
output voltage.
LSB – Least Significant Bit. It is the lowest order bit of a
binary code.
Monotonicity – The characteristic of the transfer function
whereby increasing the input code (of a DAC), or the input
signal (of an A/D), results in the output never decreasing.
MSB – Most Significant Bit. It is the highest order bit of a
binary code.
Natural Binary Code – A binary code defined by:
N = An2n + . . . + A323 + A222 + A121 + A020
Bipolar Zero Error – The error (usually expressed in LSBs)
of the input voltage location (of an A/D) of the 80H to 81H
transition. The ideal location is 1/2 LSB above zero volts in
the case of an A/D setup for a symmetrical bipolar input
(e.g., – 1.0 to + 1.0 V).
where each “A” coefficient has a value of 1 or 0. Typically, all
zeroes correspond to a zero input voltage of an A/D, and all
ones correspond to the most positive input voltage.
Differential Nonlinearity – The maximum deviation in the
actual step size (one transition level to another) from the ideal
step size. The ideal step size is defined as the Full Scale
Range divided by 2n (n = number of bits). This error must be
within ± 1 LSB for proper operation.
Offset Binary Code – Applicable only to bipolar input (or
output) data converters, it is the same as Natural Binary,
except that all zeros correspond to the most negative input
voltage (of an A/D), while all ones correspond to the most
positive input.
ECL – Emitter coupled logic.
Power Supply Sensitivity – The change in a data
converter′s performance with changes in the power supply
voltage(s). This parameter is usually expressed in percent of
full scale versus ∆V.
Full Scale Range (Actual) – The difference between the
actual minimum and maximum end points of the analog input
(of an A/D).
Full Scale Range (Ideal) – The difference between the
actual minimum and maximum end points of the analog input
(of an A/D), plus one LSB.
Gain Error – The difference between the actual and
expected gain (end point to end point), with respect to the
reference, of a data converter. The gain error is usually
expressed in LSBs.
Grey Code – Also known as reflected binary code, it is a
digital code such that each code differs from adjacent codes
by only one bit. Since more than one bit is never changed at
each transition, race condition errors are eliminated.
Integral Nonlinearity – The maximum error of an A/D, or
DAC, transfer function from the ideal straight line connecting
the analog end points. This parameter is sensitive to
dynamics, and test conditions must be specified in order to
be meaningful. This parameter is the best overall indicator of
the device′s performance.
Line Regulation – The ability of a voltage regulator to
maintain a certain output voltage as the input to the regulator
is varied. The error is typically expressed as a percent of the
nominal output voltage.
18
Nyquist Theorem – See Sampling Theorem.
Quantitization Error – Also known as digitization error or
uncertainty. It is the inherent error involved in digitizing an
analog signal due to the finite number of steps at the digital
output versus the infinite number of values at the analog
input. This error is a minimum of ± 1/2 LSB.
Resolution – The smallest change which can be discerned
by an A/D converter, or produced by a DAC. It is usually
expressed as the number of bits (n), where the converter has
2n possible states.
Sampling Theorem – Also known as the Nyquist Theorem.
It states that the sampling frequency of an A/D must be no
less that 2x the highest frequency (of interest) of the analog
signal to be digitized in order to preserve the information of
that analog signal.
Unipolar Input – A mode of operation whereby the analog
input range (of an A/D), or output range (of a DAC), includes
values of a signal polarity. Examples are 0 to + 2.0 V, 0 to
– 5.0 V, 2.0 to 8.0 V, etc.
Unipolar Offset Error – The difference between the actual
and ideal locations of the 00H to 01H transition, where the
ideal location is 1/2 LSB above the most negative
input voltage.
MOTOROLA ANALOG IC DEVICE DATA
MC10319
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC PACKAGE
CASE 709–02
ISSUE C
24
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
13
B
1
12
A
DIM
A
B
C
D
F
G
H
J
K
L
M
N
L
C
N
K
H
F
D
G
M
SEATING
PLANE
J
MILLIMETERS
MIN
MAX
31.37
32.13
13.72
14.22
3.94
5.08
0.36
0.56
1.02
1.52
2.54 BSC
1.65
2.03
0.20
0.38
2.92
3.43
15.24 BSC
0_
15_
0.51
1.02
INCHES
MIN
MAX
1.235
1.265
0.540
0.560
0.155
0.200
0.014
0.022
0.040
0.060
0.100 BSC
0.065
0.080
0.008
0.015
0.115
0.135
0.600 BSC
0_
15_
0.020
0.040
DW SUFFIX
PLASTIC PACKAGE
CASE 751F–04
(SO–28L)
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
–A–
15
28
14X
–B–
1
P
0.010 (0.25)
M
B
M
14
28X
D
0.010 (0.25)
M
T A
S
B
M
S
R
X 45 _
C
26X
–T–
G
SEATING
PLANE
K
F
J
MOTOROLA ANALOG IC DEVICE DATA
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
17.80
18.05
7.40
7.60
2.35
2.65
0.35
0.49
0.41
0.90
1.27 BSC
0.23
0.32
0.13
0.29
0_
8_
10.01
10.55
0.25
0.75
INCHES
MIN
MAX
0.701
0.711
0.292
0.299
0.093
0.104
0.014
0.019
0.016
0.035
0.050 BSC
0.009
0.013
0.005
0.011
0_
8_
0.395
0.415
0.010
0.029
19
MC10319
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
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20
◊
*MC10319/D*
MOTOROLA ANALOG IC DEVICE
DATA
MC10319/D