Data Sheet A m p l i fy t h e H u m a n E x p e r i e n c e CDK1302 8-bit, 750 MSPS, Flash A/D Converter The CDK1302 is a full parallel (flash) analog-to-digital converter capable of digitizing full scale (0 to -2V) inputs into eight-bit digital words at an update rate of 750 MSPS. The ECL-compatible outputs are demultiplexed into two separate output banks, each with differential data ready outputs to ease the task of data capture. The CDK1302’s wide input bandwidth and low capacitance eliminate the need for external track-and-hold amplifiers for most applications. A proprietary decoding scheme reduces metastable errors to the 1 LSB level. The CDK1302 operates from a single – 5.2V supply, with a nominal power dissipation of 5.5W. Applications n Digital oscilloscopes n Transient capture n Radar, EW, ECM n Direct RF down-conversion The CDK1302 is available in an 80-lead surface-mount MQuad package over the industrial temperature range (-25°C to +85°C). Block Diagram CDK1302 8-bit, 750 MSPS, Flash A/D Converter General Description features n 1:2 Demuxed ECL compatible outputs n Wide input bandwidth – 900MHz n Low input capacitance – 15pF n Metastable errors reduced to 1 LSB n Monolithic for low cost n Gray code output REV 1A Ordering Information Part Number Package Pb-Free RoHS Compliant Operating Temperature Range Packaging Method CDK1302AEMQ80 MQUAD-80 Yes Yes -25°C to +85°C Rail CDK1302AEMQ80_Q MQUAD-80 No No -25°C to +85°C Rail CDK1302BEMQ80 MQUAD-80 Yes Yes -25°C to +85°C Rail CDK1302BEMQ80_Q MQUAD-80 No No -25°C to +85°C Rail Moisture sensitivity level for all parts is MSL-1. ©2008 CADEKA Microcircuits LLC www.cadeka.com Data Sheet Pin Configuration MQUAD-80 CDK1302 8-bit, 750 MSPS, Flash A/D Converter CDK1302 Pin Assignments VEE AGND Description Negative Supply Nominally -5.2V Analog Ground VRTF Reference Voltage Force Top, Nominally 0V VRTS Reference Voltage Sense Top VRM Reference Voltage Middle, Nominally -1V VRBF Reference Voltage Force Bottom, Nominally -2V VRBS Reference Voltage Sense Bottom VIN Analog Input Voltage, Can Be Either Voltage or Sense DGND REV 1A Pin Name Digital Ground D0-D7A Data Output Bank A D0-D7B Data Output Bank B DRA Data Ready Bank A DRA Not Data Ready Bank A DRB Data Ready Bank B DRB Not Data Ready Bank B D8A Overrange Output Bank A D8B Overrange Output Bank B CLK Clock Input CLK Clock Input ©2008 CADEKA Microcircuits LLC www.cadeka.com 2 Data Sheet Absolute Maximum Ratings The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots. Supply Voltages Negative Supply Voltage (VEE to GND) Ground Voltage Differential Input Voltages Analog Input Reference Input Digital Input Reference Current Input (VRT to VRB) Min Max Unit -7.0 -0.5 +0.5 +0.5 V V +0.5 +0.5 +0.5 VEE +0.5 VEE +0.5 VEE +0.5 35 V V V mA 0 -28 mA Output Voltages Digital Output Current CDK1302 8-bit, 750 MSPS, Flash A/D Converter Parameter Reliability Information Parameter Min Storage Temperature Range -65 Typ Max Unit +150 °C Max Unit +85 +125 +150 +300 °C °C °C °C Recommended Operating Conditions Min Operating Temperature Range - ambient Operating Temperature - case Operating Temperature - junction Lead Temperature, (soldering 10 seconds) -25 ©2008 CADEKA Microcircuits LLC Typ www.cadeka.com REV 1A Parameter 3 Data Sheet Electrical Characteristics (TJ = TC = TA = +25°C , VEE = -5.2V, VRB = -2.0V, VRM = -1.0V, VRT = 0.00V, ƒCLK = 750MHz, Duty Cycle=50%, unless otherwise specified) CDK1302A Symbol Parameter Conditions Min Max Min 8 Typ Max 8 Units CDK1302 8-bit, 750 MSPS, Flash A/D Converter Resolution Typ CDL1302B bits DC Performance DLE Differential Linearity Error(1) ƒclk = 100MHz -1.0 +1.0 -1.5 +1.5 LSB ILE Integral Linearity Error(1) ƒclk = 100MHz -0.85 +0.95 -0.95 +1.5 LSB No Missing Codes Guaranteed Guaranteed Analog Input Input Voltage Range(1) Input Bias Current(1) VRB VIN = 0V Input Resistance Input Capacitance VRT 0.75 Over Full Input Range VRB 2.0 0.75 VRT V 2.0 mA 15 15 kΩ 15 15 pF 900 900 MHz Input Bandwidth Small Signal Large Signal 500 500 MHz Offset Error(2) VRT -30 +30 -30 +30 mV Offset Error(2) VRB -30 +30 -30 +30 mV Input Slew Rate 5 5 V/ns Clock Synchronous Input Currents 2 2 μA Reference Input 60 Ladder Resistance(1) Reference Bandwidth 80 60 30 80 Ω 30 MHz Timing Characteristics 750 Maximum Sample Rate(1) Acquisition Time CLK to Data Delay (2) CLK to Data Ready Delay(2) 750 MHz 2 2 ps 250 250 ps 0.9 1.4 1.9 0.9 1.4 1.9 ns 1.25 1.75 2.25 1.25 1.75 2.25 ns REV 1A Aperture Jitter Dynamic Performance SNR THD SFDR SINAD Signal-to-Noise Ratio Total Harmonic Distortion Spurious Free Dynamic Range Signal-to-Noise and Distortion ƒIN = 50MHz(1) 46 44 ƒIN = 250MHz(1) 44 42 dB ƒIN = 50MHz(1) -45 -43 dBc ƒIN = 250MHz(1) -37 -35 dBc ƒIN = 50MHz(1) 48 44 dB ƒIN = 250MHz(1) 40 36 dB ƒIN = 50MHz 43 41 dB 36 34 dB (1) ƒIN = 250MHz(1) dB Notes: 1. 100% production tested at +25°C. 2. Parameter is guaranteed (but not tested) by design and characterization data. 3. Typical Thermal Impedance: θJC = +4°C/W. ©2008 CADEKA Microcircuits LLC www.cadeka.com 4 Data Sheet Electrical Characteristics (TJ = TC = TA = +25°C , VEE = -5.2V, VRB = -2.0V, VRM = -1.0V, VRT = 0.00V, ƒCLK = 750MHz, Duty Cycle=50%, unless otherwise specified) CDK1302A Symbol Parameter Conditions Typ -1.1 -0.7 Max Min Typ -1.1 -0.7 Max Units CDK1302 8-bit, 750 MSPS, Flash A/D Converter Min CDK1302B Dynamic Inputs Input High Voltage(1) CLK, CLK Input Low Voltage CLK, CLK (1) -1.8 -1.5 -1.8 V -1.5 V tPWH Clock Pulse Width High(1) 0.67 0.5 0.67 0.5 ns tPWL Clock Pulse Width Low(1) 0.67 0.5 0.67 0.5 ns Logic 1 Voltage(1) -1.1 -0.9 -1.1 -0.9 Digital Outputs Logic 0 Voltage(1) -1.8 -1.5 -1.8 V -1.5 V Rise Time 20% to 80% 450 450 ps Fall Time 20% to 80% 450 450 ps Power Supply Requirements VEE Voltage Range(2) IEE Current (1) -4.95 VIN = 0V Power Dissipation(1) -5.2 -5.45 -4.95 -5.2 -5.45 V 1.05 1.2 1.05 1.2 A 5.5 6.25 5.5 6.25 W Notes: 1. 100% production tested at +25°C. 2. Parameter is guaranteed (but not tested) by design and characterization data. 3. Typical Thermal Impedance: θJC = +4°C/W. REV 1A ©2008 CADEKA Microcircuits LLC www.cadeka.com 5 Data Sheet General Description The CDK1302 has true differential analog and digital data paths from the preamplifiers to the output buffers (Current Mode Logic) for reducing potential missing codes while rejecting common mode noise. Signature errors are also reduced by careful layout of the analog circuitry. The output drive capability of the device can provide full ECL swings into 50Ω loads. CDK1302 8-bit, 750 MSPS, Flash A/D Converter The CDK1302 is one of the fastest monolithic 8-bit parallel flash A/D converters available today. The nominal conversion rate is 750 MSPS and the analog bandwidth is in excess of 900MHz. A major advance over previous flash converters is the inclusion of 256 input preamplifiers between the reference ladder and input comparators (see block diagram). This not only reduces clock transient kickback to the input and reference ladder due to a low AC beta, but also reduces the effect of the dynamic state of the input signal on the latching characteristics of the input comparators. The preamplifiers act as buffers and stabilize the input capacitance so that it remains constant over different input voltage and frequency ranges and therefore makes the part easier to drive than previous flash converters. The preamplifiers also add a gain of two to the input signal so that each comparator has a wider overdrive or threshold range to “trip” into or out of the active state. This gain reduces metastable states that can cause errors at the output. REV 1A Figure 1. Typical Interface Circuit Diagram ©2008 CADEKA Microcircuits LLC www.cadeka.com 6 Data Sheet Typical Interface Circuit VEE, AGND, DGND VEE is the supply pin with AGND as ground for the device. The power supply pins should be bypassed as close to the device as possible with at least a 0.01μF ceramic capacitor. A 10μF tantalum can also be used for low frequency suppression. DGND is the ground for the ECL outputs and is to be referenced to the output pulldown voltage and appropriately bypassed as shown in Figure 1. VIN (Analog Input) CLK, CLK (Clock Inputs) The clock inputs are designed to be driven differentially with ECL levels. The duty cycle of the clock should be kept at 50% to avoid causing larger second harmonics. If this is not important to the intended application, then duty cycles other than 50% may be used. D0 To D8, DR, DR, (A and B) Table 1. Output Coding VIN D8 D7–D0 > -0.5 LSB 1 10000000 -0.5 LSB 1 0 10000000 10000000 -1.5 LSB 0 0 10000000 10000001 • • • • • • 0 0 11000000 01000000 • • • • • • -2.0V +0.5 LSB 0 0 00000001 00000000 < (-2.0V +0.5 LSB) 0 00000000 • • • > -1.0V • • • REV 1A There are two analog input pins that are tied to the same point internally. Either one may be used as an analog input sense and the other for input force. This is convenient for testing the source signal to see if there is sufficient drive capability. The pins can also be tied together and driven by the same source. The CDK1302 is superior to similar devices due to a preamplifier stage before the comparators. This makes the device easier to drive because it has constant capacitance and induces less slew rate distortion. There are two reference inputs and one external reference voltage tap. These are -2V (VRB force and sense), midtap (VRM) and AGND (VRT force and sense). The reference pins and tap can be driven by op amps as shown in Figure 1 or VRM may be bypassed for limited temperature operation. These voltage inputs can be bypassed to AGND for further noise suppression if so desired. Indicates the transition between the two codes Thermal Management The typical thermal impedance is as follows: ΘCA = +17 °C/W in still air with no heat sink We highly recommend that a heat sink be used for this device with adequate air flow to ensure rated performance of the device. We have found that a Thermalloy 17846 heat sink with a minimum air flow of 1 meter/second (200 linear feet per minute) provides adequate thermal performance under laboratory tests. Application specific conditions should be taken into account to ensure that the device is properly heat sinked. The digital outputs can drive 50Ω to ECL levels when pulled down to -2V. When pulled down to -5.2V, the outputs can drive 130Ω to 1kΩ loads. All digital outputs are grey code with the coding as shown in Table 1. Cadeka recommends using differential receivers on the outputs of the data ready lines to ensure the proper output rise and fall times. ©2008 CADEKA Microcircuits LLC www.cadeka.com CDK1302 8-bit, 750 MSPS, Flash A/D Converter The circuit in Figure 1 is intended to show the most elaborate method of achieving the least error by correcting for integral linearity, input induced distortion, and power supply/ ground noise. This is achieved by the use of external reference ladder tap connections, input buffer, and supply decoupling. Please contact the factory for the CDK1302 evaluation board application note that contains more detailson interfacing the CDK1302. The function of each pinand external connections to other components is as follows: VRBF, VRBS, VRTF, VRTS, VRM (Reference Inputs) 7 Data Sheet Operation CDK1302 8-bit, 750 MSPS, Flash A/D Converter The CDK1302 has 256 preamp/comparator pairs which are each supplied with the voltage from VRT to VRB divided equally by the resistive ladder as shown in the block diagram. This voltage is applied to the positive input of each preamplifier/comparator pair. An analog input voltage applied at VIN is connected to the negative inputs of each preamplifier/comparator pair. The comparators are then clocked through each one’s individual clock buffer. When the CLK pin is in the low state, the master or input stage of the comparators compare the analog input voltage to the respective reference voltage. When the CLK pin changes from low to high the comparators are latched to the state prior to the clock transition and output logic codes in sequence from the top comparators, closest to VRT (0V), down to the point where the magnitude of the input signal changes sign (thermometer code). The output of each comparator is then registered into four 64-to-6 bit decoders when the CLK is changed from high to low. At the output of the decoders is a set of four 7-bit latches which are enabled (“track”) when the clock changes from high to low. From here, the output of the latches are coded into 6 LSBs from 4 columns and 4 columns are coded into 2 MSBs. Finally, 8 ECL output latches and buffers are used to drive the external loads. The conversion takes one clock cycle from the input to the data outputs. REV 1A Figure 2. Timing Diagram ©2008 CADEKA Microcircuits LLC www.cadeka.com 8 Data Sheet Schematic Diagrams Input Circuit Output Circuit Clock Circuit MQUAD-80 Package MQUAD-80 MILLIMETERS MIN TYP MAX 22.95 23.45 19.74 19.84 12.00 13.74 13.84 16.95 17.45 0.80 0.30 0.45 2.76 3.40 0.25 0.60 18.40 2.51 0° 7° 0.73 1.03 For additional information regarding our products, please visit CADEKA at: cadeka.com CADEKA Headquarters Loveland, Colorado T: 970.663.5452 T: 877.663.5452 (toll free) CADEKA, the CADEKA logo design, COMLINEAR and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies. CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright ©2008 by CADEKA Microcircuits LLC. All rights reserved. A m p l i fy t h e H u m a n E x p e r i e n c e REV 1A SYMBOL A B C D E F G H I J K L M INCHES MIN TYP MAX 0.904 0.923 0.777 0.781 0.472 0.541 0.545 0.667 0.687 0.031 0.012 0.018 0.109 0.134 0.010 0.024 0.724 0.099 0.110 0° 7° 0.029 0.041 CDK1302 8-bit, 750 MSPS, Flash A/D Converter Mechanical Dimensions