SPT7755
8-BIT, 750 MSPS FLASH A/D CONVERTER
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
1:2 Demuxed ECL Compatible Outputs
Wide Input Bandwidth - 900 MHz
Low Input Capacitance - 15 pF (MQUAD)
Metastable Errors Reduced to 1 LSB
Monolithic for Low Cost
Gray Code Output
Digital Oscilloscopes
Transient Capture
Radar, EW, ECM
Direct RF Down-Conversion
GENERAL DESCRIPTION
etary decoding scheme reduces metastable errors to the
1 LSB level. The SPT7755 operates from a single -5.2 V
supply, with a nominal power dissipation of 5.5 W.
The SPT7755 is a full parallel (flash) analog-to-digital converter capable of digitizing full scale (0 to -2 V) inputs into
eight-bit digital words at an update rate of 750 MSPS. The
ECL-compatible outputs are demultiplexed into two separate
output banks, each with differential data ready outputs to
ease the task of data capture. The SPT7755's wide input
bandwidth and low capacitance eliminate the need for external track-and-hold amplifiers for most applications. A propri-
The SPT7755 is available in an 80L surface-mount MQUAD
package over the industrial temperature range of -25 to
+85 °C. Contact the factory for availability of die and /883
versions.
CLK CLK
BLOCK DIAGRAM
CLOCK
BUFFER
Analog
V RT Input
Preamp
DEMUX
CLOCK
BUFFER
Comparator
256
128
VRM
127
64
63
2
1
D8B
D7B
•
•
D5B
•
•
D2B
D7
(MSB)
D6
D5
D4
D3
D2
D1
DO
(LSB)
1:2 DEMULTIPLEXER
151
256 TO 8 BIT DECODER
WITH METASTABLE ERROR CORRECTION
152
D8
(OVR)
D1B
D0B
D8A
D7A
•
•
•
D5A
•
•
•
D2A
D1A
ECL OUTPUT BUFFERS AND LATCHES
255
DRB (DATA READY)
DRB (DATA READY)
D8B (OVR)
D7B (MSB)
D6B
D5B
D4B
D3B
D2B
D1B
D0B (LSB)
DRA (DATA READY)
DRA (DATA READY)
D8A (OVR)
D7A (MSB)
D6A
D5A
D4A
D3A
D2A
D1A
D0A (LSB)
BANK B
BANK A
D0A
VRB
Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA
Phone: (719) 528-2300 FAX: (719) 528-2370
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
Negative Supply Voltage (VEE TO GND) ........ .-7.0 to +0.5 V
Ground Voltage Differential ............................. .-0.5 to +0.5 V
Output
Digital Output Current ........................................ 0 to -28 mA
Temperature
Operating Temperature, ambient ...................... .-25 to +85 °C
case ................................... +125 °C
junction ............................... +150 °C
Lead Temperature, (soldering 10 seconds). ............. +300 °C
Storage Temperature ...................................... -65 to +150 °C
Input Voltage
Analog Input Voltage ....................................... +0.5 V to VEE
Reference Input Voltage ................................. +0.5 V to VEE
Digital Input Voltage ........................................ +0.5 V to VEE
Reference Current VRT to VRB ................................. 35 mA
Notes: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
TJ = TC = TA = +25 °C , VEE=-5.2 V, VRB=-2.00 V, V RM=-1.0 V, VRT =0.00 V, fclk=750 MHz, Duty Cycle=50%, unless otherwise specified.
PARAMETERS
Resolution
DC Accuracy (+25 °C)
Integral Nonlinearity
Differential Nonlinearity
No Missing Codes
Analog Input
Input Voltage Range
Input Bias Current
Input Resistance
Input Capacitance
Input Bandwidth
Small Signal
Large Signal
Offset Error VRT
Offset Error VRB
Input Slew Rate
Clock Synchronous
Input Current
TEST
CONDITIONS
TEST
LEVEL
MIN
fCLK = 100 kHz
fCLK = 100 kHz
I
I
-1.0
-0.85
VIN=0 V
Over Full Input Range
I
I
V
V
V
V
IV
IV
V
VRB
.75
15
15
+1.0
+0.95
-1.5
-0.95
VRT
2.0
VRB
V
60
Timing Characteristics
Maximum Sample Rate
Aperture Jitter
Acquisition Time
CLK to Data Ready Delay
Clock to Data Delay
I
V
V
IV
IV
750
0.9
1.25
900
500
+30
+30
Bits
+1.5 LSB
+1.5 LSB
Guaranteed
.75
15
15
900
500
-30
-30
SPT7755B
TYP MAX UNITS
8
Guaranteed
I
V
SPT
MIN
8
Reference Input
Ladder Resistance
Reference Bandwidth
Dynamic Performance
Signal-To-Noise Ratio
(without Harmonics)
fIN = 50 MHz
fIN = 250 MHz
Total Harmonic Distortion
fIN = 50 MHz
fIN = 250 MHz
SPT7755A
TYP
MAX
-30
-30
VRT V
2.0 mA
kΩ
pF
MHz
MHz
+30 mV
+30 mV
V/ns
5
5
2
2
µA
80
30
Ω
MHz
80
30
60
750
2
250
1.4
1.75
1.9
2.25
0.9
1.25
2
250
1.4
1.75
MHz
ps
ps
1.9 ns
2.25 ns
I
I
46
44
44
42
dB
dB
I
I
-45
-37
-43
-35
dBc
dBc
2
SPT7755
3/5/97
ELECTRICAL SPECIFICATIONS
TJ = TC = TA = +25 °C , VEE=-5.2 V, VRB=-2.00 V, V RM=-1.0 V, VRT =0.00 V, fclk=750 MHz, Duty Cycle=50%, unless otherwise specified.
PARAMETERS
TEST
CONDITIONS
TEST
LEVEL
Dynamic Performance
Signal-to-Noise and Distortion
fIN = 50 MHz
fIN = 250 MHz
Spurious Free Dynamic Range
fIN = 50 MHz
fIN = 250 MHz
Digital Inputs
Input High Voltage
(CLK, NCLK)
Input Low Voltage
(CLK, NCLK)
Clock Pulse Width High (tPWH)
Clock Pulse Width Low (tPWL)
Digital Outputs
Logic "1" Voltage
Logic "0" Voltage
Rise Time
Fall Time
Power Supply Requirements
Voltage VEE
Current IEE
Power Dissipation
20 to 80%
20 to 80%
MIN
SPT7755A
TYP
MAX
MIN
SPT7755B
TYP MAX UNITS
I
I
43
36
41
34
dB
dB
I
I
48
40
44
36
dB
dB
I
-1.1
-0.7
I
I
I
0.67
0.67
-1.8
0.5
0.5
I
I
V
V
-1.1
IV
I
I
-4.95
-0.9
-1.8
450
450
-5.2
1.05
5.5
-1.1
-0.7
0.67
0.67
-1.8
0.5
0.5
-1.5 V
ns
ns
-1.1
-0.9
-1.8
450
450
V
-1.5 V
ps
ps
-4.95
-5.2
1.05
5.5
-5.45 V
1.2 A
6.25 W
-1.5
-1.5
-5.45
1.2
6.25
V
Typical Thermal Impedance: θJC = +4 °C/W.
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
TEST LEVEL
I
100% production tested at the specified temperature.
II
100% production tested at TA =25 °C, and sample
tested at the specified temperatures.
III
QA sample tested only at the specified temperatures.
IV
Parameter is guaranteed (but not tested) by design
and characterization data.
V
Parameter is a typical value for information purposes
only.
VI
100% production tested at TA = 25 °C. Parameter is
guaranteed over specified temperature range.
Unless otherwise noted, all tests are pulsed
tests; therefore, TJ = TC = TA .
SPT
TEST PROCEDURE
3
SPT7755
3/5/97
and frequency ranges and therefore makes the part easier to
drive than previous flash converters. The preamplifiers also
add a gain of two to the input signal so that each comparator
has a wider overdrive or threshold range to "trip" into or out
of the active state. This gain reduces metastable states that
can cause errors at the output.
GENERAL DESCRIPTION
The SPT7755 is one of the fastest monolithic 8-bit parallel
flash A/D converters available today. The nominal conversion rate is 750 MSPS and the analog bandwidth is in excess
of 900 MHz. A major advance over previous flash converters
is the inclusion of 256 input preamplifiers between the
reference ladder and input comparators (see block diagram). This not only reduces clock transient kickback to the
input and reference ladder due to a low AC beta but also
reduces the effect of the dynamic state of the input signal on
the latching characteristics of the input comparators. The
preamplifiers act as buffers and stabilize the input capacitance so that it remains constant over different input voltage
The SPT7755 has true differential analog and digital data
paths from the preamplifiers to the output buffers (Current
Mode Logic) for reducing potential missing codes while
rejecting common mode noise.
Signature errors are also reduced by careful layout of the
analog circuitry. The output drive capability of the device can
provide full ECL swings into 50 Ω loads.
Figure 1 - SPT7755 Typical Interface Circuit
**
VIN
VIN
50 Ω
VRTS
R
+
U1
-
22 Ω
VRM
*
R
22 Ω 2N2907
VRBS
VRBF
*
-5.2 V
CLK
U2
NCLK
50 Ω
DGND
-2 V
Pulldown
(Analog)
.1 µF
AGND
50 Ω
VEE
Convert
50 Ω
-5.2 V
50 Ω
-2.0 V
Reference
+ U1
BANK
A
DRB (DATA READY)
DRB (DATA READY)
D8B (OVR)
D7B (MSB)
D6B
D5B
D4B
D3B
D2B
D1B
D0B (LSB)
DRA (DATA READY)
DRA (DATA READY)
D8A (OVR)
D7A (MSB)
D6A
D5A
D4A
D3A
D2A
D1A
D0A (LSB)
VRTF
BANK B
VIN
*
-2.0 V
Pulldown
(Digital)
FB= Ferrite bead
U1= OP291 or equivalent with low offset/noise.
R = 1 k Ω; 0.1% matched.
FB
= AGND
-5.2 V
= DGND
U2= Motorola ECLinPS Lite, MC10EL16, differential receiver
with 250 ps (typ) propagation delay.
* = 10 µF Tantalum Capacitor and 0.1 µF Chip Capacitor
** = Care must be taken to avoid exceeding the maximum rating
for the input, especially during power up sequencing of the
analog input driver.
SPT
4
SPT7755
3/5/97
TYPICAL INTERFACE CIRCUIT
(VRM) and AGND (V RT force and sense). The reference pins
and tap can be driven by op amps as shown in figure 1 or VRM
may be bypassed for limited temperature operation. These
voltage inputs can be bypassed to AGND for further noise
suppression if so desired.
The circuit in figure 1 is intended to show the most elaborate
method of achieving the least error by correcting for integral
linearity, input induced distortion and power supply/ground
noise. This is achieved by the use of external reference
ladder tap connections, input buffer and supply decoupling.
Please contact the factory for the SPT7755 evaluation board
applications note that contains more details on interfacing the
SPT7755. The function of each pin and external connections
to other components is as follows:
Table I - Output Coding
VIN
VEE, AGND, DGND
VEE is the supply pin with AGND as ground for the device. The
power supply pins should be bypassed as close to the device
as possible with at least a .01 µF ceramic capacitor. A 1 µF
tantalum can also be used for low frequency suppression.
DGND is the ground for the ECL outputs and is to be
referenced to the output pulldown voltage and appropriately
bypassed as shown in figure 5.
VIN (ANALOG INPUT)
There are two analog input pins that are tied to the same point
internally. Either one may be used as an analog input sense
and the other for input force. This is convenient for testing the
source signal to see if there is sufficient drive capability. The
pins can also be tied together and driven by the same source.
The SPT7755 is superior to similar devices due to a preamplifier stage before the comparators. This makes the device
easier to drive because it has constant capacitance and
induces less slew rate distortion.
D8 D7 • • • D0
> -0.5 LSB
1
10000000
-0.5 LSB
1
0
10000000
10000000
-1.5 LSB
0
0
10000000
10000001
•
•
•
•
•
•
•
•
•
-1.0 V
0
0
11000000
01000000
•
•
•
•
•
•
•
•
•
-2.0 V+ 1/2 LSB
0
0
00000001
00000000
< (-2.0 V +1/2 LSB)
0
00000000
CLK, CLK (CLOCK INPUTS)
Indicates the transition between the two codes
The clock inputs are designed to be driven differentially with
ECL levels. The duty cycle of the clock should be kept at 50%
to avoid causing larger second harmonics. If this is not
important to the intended application, then duty cycles other
than 50% may be used.
THERMAL MANAGEMENT
The typical thermal impedance is as follows:
D0 TO D8, DR, NDR (A AND B)
ΘCA = +17 °C/W in still air with no heat sink
The digital outputs can drive 50 Ω to ECL levels when pulled
down to -2 V. When pulled down to -5.2 V, the outputs can
drive 130 Ω to 1 kΩ loads. All digital outputs are grey code with
the coding as shown in table 1.
We highly recommend that a heat sink be used for this device
with adequate air flow to ensure rated performance of the
device. We have found that a Thermalloy 17846 heat sink
with a minimum air flow of 1 meter/second (200 linear feet per
minute) provides adequate thermal performance under laboratory tests. Application specific conditions should be taken
into account to ensure that the device is properly heat sinked.
VRBF, VRBS, VRTF, VRTS, VRM
(REFERENCE INPUTS)
There are two reference inputs and one external reference
voltage tap. These are -2 V (VRB force and sense), mid-tap
SPT
5
SPT7755
3/5/97
are latched to the state prior to the clock transition and output
logic codes in sequence from the top comparators, closest to
VRT (0 V), down to the point where the magnitude of the input
signal changes sign (thermometer code). The output of each
comparator is then registered into four 64-to-6 bit decoders
when the CLK is changed from high to low. At the output of the
decoders is a set of four 7-bit latches which are enabled
("track") when the clock changes from high to low. From here,
the output of the latches are coded into 6 LSBs from 4
columns and 4 columns are coded into 2 MSBs. Finally, 8
ECL output latches and buffers are used to drive the external
loads. The conversion takes one clock cycle from the input to
the data outputs.
OPERATION
The SPT7755 has 256 preamp/comparator pairs which are
each supplied with the voltage from VRT to VRB divided
equally by the resistive ladder as shown in the block diagram.
This voltage is applied to the positive input of each preamplifier/comparator pair. An analog input voltage applied at VIN is
connected to the negative inputs of each preamplifier/comparator pair. The comparators are then clocked through each
one's individual clock buffer. When the CLK pin is in the low
state, the master or input stage of the comparators compare
the analog input voltage to the respective reference voltage.
When the CLK pin changes from low to high the comparators
Figure 2 - Timing Diagram
N
VIN
N+6
N+5
N+1
N+2
N+4
N+7
1.3 ns
N+3
CLK
NCLK
DRA
NDRA
1.4 ns typ
Data Bank A
N-2
N
N+2
N+4
1.75 ns typ
DRB
NDRB
1.4 ns typ
N-1
Data Bank B
N+1
N+3
1.75 ns typ
Figure 3 - Subcircuit Schematics
INPUT CIRCUIT
OUTPUT CIRCUIT
CLOCK INPUT
AGND
AGND
DGND
AGND
VIN
VR
CLK
CLK
Data Out
VEE
SPT
VEE
6
SPT7755
3/5/97
PACKAGE OUTLINE
80-PIN MQUAD
F
G
H
I
SYMBOL
A
J
B
INCHES
MIN
MAX
MILLIMETERS
MIN
MAX
A
0.937
0.945
23.80
24.00
B
C
0.777
0.472 TYP
0.785
19.72
12.0 TYP
19.93
D
E
F
0.541
0.701
0.032 TYP
0.549
0.709
13.73
17.80
0.80 TYP
13.94
18.00
G
H
I
J
0.014 TYP
0.114
.006 TYP
0.724 TYP
K
L
M
0.099
7°
0.026
0.122
0.109
0.036
0.36 TYP
2.90
0.15 TYP
18.4 TYP
2.51
7°
0.66
3.10
2.77
0.91
M
C
D
E
SPT
K
L
7
SPT7755
3/5/97
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