SEMICONDUCTOR TECHNICAL DATA The MC10H/100H660 is a 4–bit ECL input, translating DRAM address driver, ideally suited for driving TTL compatible DRAM inputs from an ECL system. It is designed for use in high capacity, highly interleaved DRAM memory boards, that directly interface to a high speed, pipelined ECL bus interface, where new operations may be initiated to the board at up to a 50 MHz rate. The latch provides the capability for the memory controller to propagate new addresses to different banks without having to wait for the address timing constraints to be satisfied from a previous memory operation. The dual output fanout reduces input loading from the controller by a factor of two, thus significantly improving board etch propagation delays from the controller, without the need for additional ECL buffering. The H660 features special TTL outputs which do not have an IOS limiting resistor, therefore allowing rapid charging of the load capacitance. Output voltage levels are designed specifically for driving DRAM inputs. The output stages feature separate power and ground pins to isolate output switching noise from internal circuitry, and also to improve simultaneous switching performance. The 10H version is compatible with MECL 10H ECL logic levels. The 100H version is compatible with 100K levels. • • • • FN SUFFIX PLASTIC PACKAGE CASE 776–02 LOGIC SYMBOL ECL Inputs DRAM Driver Outputs VEE VCCE High Capacitive Drive Outputs to Drive DRAM Address Inputs Extra TTL and ECL Power/Ground Pins to Minimize Switching Noise Dual Supply 10.7 ns Max. D to Q into 300 pF Q0A D D0 OGND0 Q0B Q EN R IVT01 OVT01 IGND01 PIN NAMES PIN FUNCTION OGND[0:3] OVT01, OVT23 IGND01, IGND23 IVT01, IVT23 VEE VCCE D[0:3] Q[0:3]A, Q[0:3]B LEN R Output Ground (0V) Output VCCT (+5.0 V) Internal TTL Ground (OV) Internal TTL VCCT (+5.0 V) ECL Neg. Supply (–5.2/ –4.5 V) ECL Ground (0V) Data Inputs (ECL) Data Outputs (TTL levels) Latch Enable (ECL) Reset (ECL) Q1A D D1 EN R Q2A D D2 Q2A OGND2 Q2B OVT23 Q3A OGND3 Q3B 24 23 22 21 20 19 OGND2 Q2B Q EN R IVT23 OVT23 IGND23 Q3A D D3 25 OGND1 Q1B Q OGND3 Q3B Q EN R LEN IGND23 Q1A 28 16 VCCE OVT01 1 Pinout: 28–Lead PLCC 15 (Top View) VCCE D LEN R Q Q0B 2 14 D3 OGND0 3 13 D2 Q0A 4 12 R L H X X H H L X L L L H L H Q0 L 5 6 7 8 9 10 11 LEN 17 D1 27 D0 OGND1 VEE IVT23 VEE 18 IGND01 26 IVT01 Q1B R TRUTH TABLE 3/93 Motorola, Inc. 1996 2–121 REV 5 MC10H660 MC100H660 DC CHARACTERISTICS: VCCT = 5.0 V ± 10%; VEE = – 5.2 V ± 5% (10H version); VEE = – 4.2 V to –5.5 V (100H version) 0°C Symbol Characteristic IEE Power Supply Current ICCH min 25°C max min 85°C max min max Unit ECL 41.8 44.0 46.2 mA TTL 77.0 77.1 79.2 mA 94.6 95.7 96.8 mA ICCL Condition TTL CHARACTERISTICS: VCCT = 5.0 V ± 10%; VEE = – 5.2 V ± 5% (10H version); VEE = – 4.2 V to –5.5 V (100H version) 0°C Symbol Characteristic min VOH Output HIGH Voltage 2.6 VOL Output LOW Voltage IOS Output Short Circuit Current* 25°C max min 85°C max 2.6 min max 2.6 Unit Condition V IOH = – 24 mA 0.50 0.50 0.50 V IOL = 24 mA * * * V See Note 1 1. The outputs must not be shorted to ground, as this will result in permanent damage to the device. The high drive outputs of this device do not include a limiting IOS resistor. Minimum recommended load capacitance is 100 pF. Precise output performance and waveforms will depend on the exact nature of the actual load. The lumped load is of course an approximation to a real memory system load. AC Characteristics: VCCT = 5.0 V ± 10%; VEE = – 5.2 V ± 5% (10H version) VEE = – 4.2 V to –5.5 V (100H version) 0°C 25°C Symbol Characteristic min ts Set–up Time, D to LEN 0.5 0.5 0.5 ns tn Hold Time, D to LEN 1.5 1.5 1.5 ns tw(H) LEN Pulse Width, HIGH 2.0 2.0 2.0 ns tR tF Output Rise/Fall Time 0.8 V – 2.0 V 0.5 2.0 0.5 2.0 0.5 2.0 ns CL = 200 pF tPLH tPHL Propagation Delay to Output D 3.0 4.0 4.5 6.0 8.0 9.5 3.0 4.0 4.5 6.0 8.0 9.5 3.0 4.0 4.5 6.0 8.0 9.5 ns CL = 100 pF CL = 200 pF CL = 300 pF 50% point of ECL input to 1.5 V point of TTL output LEN 4.3 4.9 5.4 6.9 8.9 10.4 4.3 4.9 5.4 6.9 8.9 10.4 4.3 4.9 5.4 6.9 8.9 10.4 ns CL = 100 pF CL = 200 pF CL = 300 pF tPHL Propagation Delay to Output R 4.1 4.5 5.0 9.1 8.5 10.0 4.1 4.5 5.0 9.1 8.5 10.0 4.1 4.5 5.0 9.1 8.5 10.0 ns CL = 100 pF CL = 200 pF CL = 300 pF tPLH Propagation Delay to Output D 3.9 4.8 5.8 5.9 7.2 8.8 3.9 4.8 5.8 5.9 7.2 8.8 4.0 5.0 5.9 6.1 7.4 8.9 ns CL = 100 pF CL = 200 pF CL = 300 pF 50% point of ECL input to 2.4 V point of TTL output LEN 4.7 5.5 6.3 7.1 8.3 9.5 4.7 5.5 6.3 7.1 8.3 9.5 4.8 5.6 6.4 7.2 8.4 9.6 ns CL = 100 pF CL = 200 pF CL = 300 pF Propagation Delay to Output D 4.5 6.0 7.0 6.7 9.0 10.6 4.5 6.0 7.0 6.7 9.0 10.6 4.4 6.0 6.9 6.6 9.0 10.3 ns CL = 100 pF CL = 200 pF CL = 300 pF 50% point of ECL input to 0.8 V point of TTL output LEN 4.0 4.9 6.0 6.0 7.3 9.0 4.0 4.9 6.0 6.0 7.3 9.0 4.0 4.9 5.9 6.0 7.3 8.9 ns CL = 100 pF CL = 200 pF CL = 300 pF R 4.3 6.1 7.2 6.5 9.1 10.8 4.3 6.1 7.2 6.5 9.1 10.8 4.3 6.1 7.2 6.5 9.1 10.8 ns CL = 100 pF CL = 200 pF CL = 300 pF tPHL MOTOROLA max 2–122 min 85°C max min max Unit Condition MECL Data DL122 — Rev 6 MC10H660 MC100H660 OUTPUT STRUCTURE POWER VS FREQUENCY – Output Q0A Structure Shown INTERNAL TTL POWER – typical POWER VS FREQUENCY PER BIT 700 IVT01 PDYNAMIC = CL ƒ VSWING VCC OVT01 600 PTOTAL = PSTATIC + PDYNAMIC Power, mW 500 300 PF 400 200 PF 100 PF 300 50 PF Q0A 200 NO LOAD 100 OGND0 INTERNAL TTL GROUND 0 IGND01 0 20 40 60 80 100 120 FREQUENCY, MHZ 10H ECL DC Characteristics: VCCT = 5.0 V ± 10%; VEE = – 5.2 V ± 5% 0°C min 25°C max S b l Symbol Characteristic Ch i i IIH IIL Input HIGH Current Input LOW Current 1.5 VIH VIL Input HIGH Voltage Input LOW Voltage –1170 –1950 min 85°C max 225 1.0 – 840 –1480 min max U i Unit 145 µA µA – 720 –1445 mV mV 145 1.0 –1130 –1950 – 810 –1480 –1060 –1950 C di i Condition 100H ECL DC Characteristics: VCCT = 5.0 V ± 10%; VEE = – 4.2 V to – 5.5 V 0°C S b l Symbol Characteristic Ch i i min IIH IIL Input HIGH Current Input LOW Current 1.5 VIH VIL Input HIGH Voltage Input LOW Voltage –1165 –1810 MECL Data DL122 — Rev 6 25°C max min 225 85°C max 145 1.0 – 880 –1475 min –1165 –1810 2–123 max U i Unit 145 µA µA – 880 –1475 mV mV 1.0 – 880 –1475 –1165 –1810 C di i Condition MOTOROLA MC10H660 MC100H660 AC TEST SET–UP CL = 100 pF 450 Ω D.U.T. B 50 Ω 100 PF PULSE GEN. A 50 Ω SCOPE The MC10H/100 H660 ECL–TTL DRAM Address Driver The MC 10H/100H660 was designed for use in high capacity, highly interleaved DRAM memory boards, that directly interface to a high speed, pipelined ECL bus interface, where new operations may be initiated to the board at a 50 MHz rate ( e.g. bipolar RISC systems). The following briefly discusses the major design features of the part over existing semiconductor devices traditionally used in interfacing DRAMs in high performance system environments. 1. ECL Translator High performance memory systems of the past that were interfaced to ECL buses had to rely on separate ECL translators and DRAM drivers to interface to large DRAM arrays, which is acceptable if the module is not highly interleaved and the bus cycle time is comparable to the DRAM access time. This becomes inadequate as the cycle time of the interface becomes significantly faster than the address timing requirements of the RAM, and as the degree of internal board interleaving increases. These higher performance demands require that the internal address and control signals propagated to the DRAM drivers be implemented in ECL, thus requiring the integration of the driver and translator functions. Integration of the translator/drive function also reduces access latency, as well as keeping DRAM timing parameters from being violated, due to the excessive delays encountered with separate parts. 2. MOS Drive Capacity Outputs are specifically designed for driving large numbers of DRAMs ( 300 pF), which reduce the number of parts and power requirements needed per board. Output voltage levels are designed specifically for driving DRAM inputs. No ECL [ MOTOROLA translator parts on the market today provide the designer with this drive capability as well as the flexibility to vary the number of DRAMs that are driven by the part. 3. Transparent Latch The latch is added to provide the capability for a memory controller to propagate new addresses to different banks without having to wait for the address timing constraints to be satisfied from a previous memory operation. For system implementations where this is acceptable, the user has the capability to keep the latch open, thus having the part act as an address translator/buffer, with minimal performance impact due to the additional propagation delay incurred from the internal latch. The latch is controlled within an already existing DRAM timing signal. 4. 1:2 Output Fanout This function is useful in that it reduces input loading from the controller by a factor of two, thus significantly improving board etch propagation delays from the controller to the large number of translators, without the addition of ECL glue logic parts to reduce the loading. In large memory boards, so many translators are needed that this type of organization is not a handicap. 5. Low Skew, Low Propagation Delay Low skew of the part as well as fast propagation delay enable faster overall DRAM operation to be attained than is possible with existing parts. 6. Power and Package Pin Layout The H660 is specifically designed with additional power and ground pins to greatly improve simultaneous switching performance over existing driver parts. 2–124 MECL Data DL122 — Rev 6 MC10H660 MC100H660 OUTPUT WAVEFORMS simulated Example 1. An output load consisting of just CL = 50 pF results in overshoot at the output Q: 8 VOLTAGE 6 Q 4 2 0 D –2 0 25 50 75 TIME Example 2. In a memory system application, use of an external source resistor is suggested. Simulations run with RS = 8Ω and CL = 300pF leads to clean waveforms both at the output, Q, and at point Qp: QP RS = 8 Ω Q H660 OUTPUT CL = 300pF 8 6 VOLTAGE 4 Q 2 QP 0 D –2 0 25 50 75 TIME MECL Data DL122 — Rev 6 2–125 MOTOROLA MC10H660 MC100H660 OUTLINE DIMENSIONS FN SUFFIX PLASTIC PLCC PACKAGE CASE 776–02 ISSUE D 0.007 (0.180) B T L–M M N S T L–M S S Y BRK –N– 0.007 (0.180) U M N S D Z –M– –L– W 28 D X G1 0.010 (0.250) T L–M S N S S V 1 VIEW D–D A 0.007 (0.180) R 0.007 (0.180) M T L–M S N S C M T L–M S N 0.007 (0.180) H Z M T L–M N S S S K1 E 0.004 (0.100) G J S K SEATING PLANE F VIEW S G1 0.010 (0.250) –T– T L–M S N S M T L–M S N S VIEW S NOTES: 1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM –T–, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). MOTOROLA 0.007 (0.180) 2–126 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 ––– 0.025 ––– 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 ––– 0.020 2_ 10_ 0.410 0.430 0.040 ––– MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 ––– 0.64 ––– 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 ––– 0.50 2_ 10_ 10.42 10.92 1.02 ––– MECL Data DL122 — Rev 6 MC10H660 MC100H660 Motorola reserves the right to make changes without further notice to any products herein. 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How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 MFAX: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 ◊ MECL Data DL122 — Rev 6 2–127 *MC10H660/D* MC10H660/D MOTOROLA