MOTOROLA MC14032BCL

SEMICONDUCTOR TECHNICAL DATA
The MC14032B and MC14038B triple serial adders have the clock and
carry reset inputs common to all three adders. The carry is added on the
positive–going clock transition for the MC14032B, and on the negative–
going clock transition for the MC14038B. Typical applications include serial
arithmetic units, digital correlators, digital servo control systems, datalink
computers, and flight control computers.
L SUFFIX
CERAMIC
CASE 620
•
•
•
•
Buffered Outputs
Single–Phase Clocking
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range.
• Pin–for–Pin Replacement for CD4032B and CD4038B.
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P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
– 0.5 to + 18.0
V
Vin, Vout
Input or Output Voltage (DC or Transient)
– 0.5 to VDD + 0.5
V
lin, lout
Input or Output Current (DC or Transient),
per Pin
± 10
mA
PD
Power Dissipation, per Package†
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
260
_C
TL
Lead Temperature (8–Second Soldering)
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.
MC14032B
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
TA = – 55° to 125°C for all packages.
BLOCK DIAGRAM
A1 10
B1 11
INVERT 1 7
A2 13
B2 12
INVERT 2 5
A3
B3
INVERT 3
CLOCK
CARRY RESET
S
9 S1
ADDER 2
4 S2
15
14
2
3
6
ADDER 3
1 S3
MC14038B
A
B
S
D Q
D Q
CR
CR
INVERT
CARRY
RESET
ADDER 1
VDD = PIN 16
VSS = PIN 8
LOGIC DIAGRAMS
(ONE SECTION AND COMMON INPUTS SHOWN)
A
B
Plastic
Ceramic
SOIC
INVERT
CARRY
RESET
D Q
C
CLOCK
TO
NEXT
STAGE
D Q
C
CLOCK
TO
NEXT
STAGE
REV 3
1/94
MC14032B
Motorola, Inc. 1995
MC14038B
128
MOTOROLA CMOS LOGIC DATA
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Output Voltage
Vin = VDD or 0
Symbol
– 55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
“0” Level
VOL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
IOL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current
Iin
15
—
± 0.1
—
± 0.00001
± 0.1
—
± 1.0
µAdc
Input Capacitance
(Vin = 0)
Cin
—
—
—
—
5.0
7.5
—
—
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
“1” Level
VIH
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
mAdc
IT = (0.96 µA/kHz) f + IDD
IT = (1.93 µA/kHz) f + IDD
IT = (2.80 µA/kHz) f + IDD
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.003.
PIN ASSIGNMENT
MOTOROLA CMOS LOGIC DATA
S3
1
16
VDD
INV 3
2
15
A3
C
3
14
B3
S2
4
13
A2
INV 2
CARRY
RESET
INV 1
5
12
B2
6
11
B1
7
10
A1
VSS
8
9
S1
MC14032B MC14038B
129
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SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL
Propagation Delay Time
A, B or Invert to Sum
tPLH, tPHL = (1.7 ns/pF) CL + 195 ns
tPLH, tPHL = (0.66 ns/pF) CL + 87 ns
tPLH, tPHL = (0.5 ns/pF) CL + 65 ns
tPLH,
tPHL
VDD
Vdc
Min
Typ #
Max
5.0
10
15
—
—
—
100
50
40
200
100
80
Unit
ns
ns
Clock to Sum
tPLH, tPHL = (1.7 ns/pF) CL + 415 ns
tPLH, tPHL = (0.66 ns/pF) CL + 147 ns
tPLH, tPHL = (0.5 ns/pF) CL + 110 ns
5.0
10
15
—
—
—
280
120
90
1400
300
230
5.0
10
15
—
—
—
500
180
135
2400
600
450
ns
Input Setup Time
tsu
5.0
10
15
10
10
10
– 10
0
0
—
—
—
ns
Clock Pulse Frequency
fcl
5.0
10
15
—
—
—
4.0
10
12
1.0
2.5
4.0
MHz
tTHL, tTLH
5.0
10
15
—
—
—
—
—
—
15
5
4
µs
Clock Rise and Fall Times
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
TIMING DIAGRAMS
MC14032B
WORD 1 + WORD 2
MC14038B
WORD 3 + WORD 4
A
B
C
INV
A
B
C
INV
CR
S
CR
S
TRUE SUM
WORD 1: 0.0111100 = + 60
WORD 2: 0.0110010 = + 50
0.1101110 = + 110
COMPLEMENTED
SUM
WORD 3: 1.1011011 = – 37
WORD 4: 1.1001110 = – 50
1.0101001 = – 87
WORD 1 + WORD 2
WORD 3 + WORD 4
TRUE SUM
COMPLEMENTED
SUM
WORD 1: 1.1000011 = – 61
WORD 2: 1.1001101 = – 51
1.0010000 = – 112
WORD 3: 0.0100100 = + 36
WORD 4: 0.0110001 = + 49
0.1010101 = + 85
NOTE: Unused input pins must be connected to either VDD or VSS.
MC14032B MC14038B
130
MOTOROLA CMOS LOGIC DATA
VDS = VOL
VDS = VOH – VDD
VDD = – VGS
VDD = VGS
VOH
VOL
VDD
VDD
S1
A1
B1
INV1
A2
B2
INV2 S2
A3
B3
INV3
CLOCK
CR
S3
S1
A1
B1
INV1
A2
B2
INV2 S2
A3
B3
INV3
CLOCK
CR
S3
IOH
EXTERNAL
POWER
SUPPLY
VSS
IOL
EXTERNAL
POWER
SUPPLY
VSS
Figure 1. Typical Output Source Test Circuit
Figure 2. Typical Output Sink Test Circuit
VDD
500 pF
0.01 µF
CERAMIC
ID
VDD
PROGRAMMABLE
PULSE
GENERATOR
S1
A1
B1
INV1
A2
B2
INV2 S2
A3
B3
INV3
CLOCK
CR
S3
VSS
20 ns
50%
CLOCK
VARIABLE
WIDTH
CL
20 ns
90%
VDD
10%
VSS
VDD
90%
CL
A,B
10%
tTHL
VSS
tTLH
CL
Figure 3. Power Dissipation Test Circuit and Waveforms
MOTOROLA CMOS LOGIC DATA
MC14032B MC14038B
131
VDD
S1
A1
B1
INV1
A2
B2
INV2 S2
A3
B3
INV3
CLOCK
CR
S3
PROGRAMMABLE
PULSE
GENERATOR
CL
CL
VSS
CL
MC14032B
VDD
A
50%
VSS
VDD
50%
B
VSS
tsu
VDD
50%
CLOCK
VSS
tPLH
tPHL
tPLH
tPHL
VOH
90%
50%
10%
SUM
VOL
tTLH
tTHL
MC14038B
A
VDD
50%
VSS
B
VDD
50%
tsu
CLOCK
VSS
VDD
50%
VSS
SUM
tPHL
90%
50%
10%
tTHL
tPLH
tPHL
tPLH
VOH
VOL
tTLH
Figure 4. Switching Time Test Circuit and Waveforms
MC14032B MC14038B
132
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
–A–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–B–
C
L
DIM
A
B
C
D
E
F
G
H
K
L
M
N
–T–
K
N
SEATING
PLANE
M
E
F
J
G
D
16 PL
0.25 (0.010)
16 PL
0.25 (0.010)
M
T A
T B
M
S
INCHES
MIN
MAX
0.750
0.785
0.240
0.295
–––
0.200
0.015
0.020
0.050 BSC
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
19.05
19.93
6.10
7.49
–––
5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0_
15 _
0.51
1.01
S
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
16
9
1
8
B
F
C
L
S
–T–
SEATING
PLANE
K
H
G
D
J
16 PL
0.25 (0.010)
MOTOROLA CMOS LOGIC DATA
M
T A
M
M
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
MC14032B MC14038B
133
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
–B–
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
–T–
SEATING
PLANE
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
J
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
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MC14032B MC14038B
134
◊
*MC14032B/D*
MOTOROLA CMOS LOGIC
DATA
MC14032B/D