MOTOROLA MC14014B

SEMICONDUCTOR TECHNICAL DATA
The MC14014B and MC14021B 8–bit static shift registers are constructed
with MOS P–channel and N–channel enhancement mode devices in a single
monolithic structure. These shift registers find primary use in parallel–to–
serial data conversion, synchronous and asynchronous parallel input, serial
output data queueing; and other general purpose register applications
requiring low power and/or high noise immunity.
L SUFFIX
CERAMIC
CASE 620
•
•
•
•
•
•
•
•
Synchronous Parallel Input/Serial Output (MC14014B)
Asynchronous Parallel Input/Serial Output (MC14021B)
Synchronous Serial Input/Serial Output
Full Static Operation
“Q” Outputs from Sixth, Seventh, and Eighth Stages
Double Diode Input Protection
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
• MC14014B Pin–for–Pin Replacement for CD4014B
• MC14021B Pin–for–Pin Replacement for CD4021B
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
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ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
– 0.5 to + 18.0
V
Vin, Vout
Input or Output Voltage (DC or Transient)
– 0.5 to VDD + 0.5
V
lin, lout
Input or Output Current (DC or Transient),
per Pin
± 10
mA
PD
Power Dissipation, per Package†
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
260
_C
TL
Lead Temperature (8–Second Soldering)
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
TA = – 55° to 125°C for all packages.
TRUTH TABLE
SERIAL OPERATION:
t
Clock DS P/S
0
0
1
0
0
0
1
0
n
n+1
n+2
n+3
X
0
P2
7
P3
6
Q7
t=n+7
Q8
t=n+8
0
1
0
1
?
0
1
0
?
?
0
1
Q6
Q7
Q8
Clock
MC14014B MC14021B DS
X
X
X
P/S
Pn
0
*Qn
1
1
1
1
0
* Q6, Q7, & Q8 are available externally
X = Don’t Care
LOGIC DIAGRAM
P1
Q6
t=n+6
PARALLEL OPERATION:
X
9
Plastic
Ceramic
SOIC
P6
5
P7
14
P8
15
1
P/S
11
D
DS
Q
C
D
C
Q
D
Q
C
D
Q
D
Q
D
C
Q
C
Q
C
Q
10
CLOCK
VDD = PIN 16
VSS = PIN 8
P4 = PIN 4
P5 = PIN 13
2
Q6
12
Q7
3
Q8
REV 3
1/94
MOTOROLA
Motorola, Inc. 1995
CMOS LOGIC DATA
MC14014B MC14021B
51
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Symbol
– 55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
Output Voltage
Vin = VDD or 0
“0” Level
VOL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
Vin = 0 or VDD
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
IOL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current
Iin
15
—
± 0.1
—
± 0.00001
± 0.1
—
± 1.0
µAdc
Input Capacitance
(Vin = 0)
Cin
—
—
—
—
5.0
7.5
—
—
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
—
—
—
5.0
10
15
—
—
—
0.005
0.010
0.015
5.0
10
15
—
—
—
150
300
600
µAdc
IT
5.0
10
15
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
(VO = 0.5 or 4.5 Vdc) “1” Level
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
IOH
Source
Sink
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
Vdc
mAdc
IT = (0.75 µA/kHz) f + IDD
IT = (1.50 µA/kHz) f + IDD
IT = (2.25 µA/kHz) f + IDD
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.0015.
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.
MC14014B MC14021B
52
PIN ASSIGNMENT
P8
1
16
VDD
Q6
2
15
P7
Q8
3
14
P6
P4
4
13
P5
P3
5
12
Q7
P2
6
11
DS
P1
7
10
C
VSS
8
9
P/S
MOTOROLA CMOS LOGIC DATA
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SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
VDD
Vdc
Min
Typ #
Max
5.0
10
15
—
—
—
100
50
40
200
100
80
5.0
10
15
—
—
—
400
170
115
800
340
230
Unit
ns
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL
Propagation Delay Time (Clock to Q, P/S to Q)
tPHL, tPLH = (1.7 ns/pF) CL + 315 ns
tPHL, tPLH = (0.66 ns/pF) CL + 137 ns
tPHL, tPLH = (0.5 ns/pF) CL + 90 ns
tPLH,
tPHL
Clock Pulse Width
tWH
5.0
10
15
400
175
135
150
75
40
—
—
—
ns
fcl
5.0
10
15
—
—
—
3.0
6.0
8.0
1.5
3.0
4.0
MHz
tWH
5.0
10
15
400
175
135
150
75
40
—
—
—
ns
Setup Time
P/S to Clock
tsu
5.0
10
15
200
100
80
100
50
40
—
—
—
ns
Hold Time
Clock to P/S
th
5.0
10
15
20
20
25
– 2.5
– 10
0
—
—
—
ns
Setup Time
Data (Parallel or Serial) to
Clock or P/S
tsu
5.0
10
15
350
80
60
150
50
30
—
—
—
ns
Hold Time
Clock to Ds
th
5.0
10
15
45
35
35
0
0
5
—
—
—
ns
Hold Time
Clock to Pn
th
5.0
10
15
50
45
45
25
20
20
—
—
—
ns
tr(cl)
5.0
10
15
—
—
—
—
—
—
15
5
4
µs
Clock Frequency
Parallel/Serial Control Pulse Width
Input Clock Rise Time
ns
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
VDD
PULSE
GENERATOR
P/S
C
P6
P7
P8
DS
Vout
Q6
PULSE
GENERATOR
Q7
Q8
VDD
IOH
EXTERNAL
POWER
SUPPLY
P/S
C
P6
P7
P8
DS
Vout
Q6
Q7
Q8
IOL
EXTERNAL
POWER
SUPPLY
Preset output under test to a logic “1” level.
Figure 1. Output Source Current Test Circuit
MOTOROLA CMOS LOGIC DATA
Figure 2. Output Sink Current Test Circuit
MC14014B MC14021B
53
VDD
500 µF
ID
0.01 µF
CERAMIC
P/S
C
P1
P2
P3
P4
P5
P6
P7
P8
DS
PULSE
GENERATOR 1
PULSE
GENERATOR 2
Q6
CL
Q7
CL
Q8
VSS
CL
1
f
CLOCK
50%
DATA
Figure 3. Power Dissipation Test Circuit and Waveform
SW 1
VDD
1
PULSE
GENERATOR 1
2
PULSE
GENERATOR 2
2
1
2
1
SWITCH POSITION 1 = PARALLEL IN
SWITCH POSITION 2 = SERIAL IN
VDD
P/S
C
P1
P2
P3
P4
P5
P6
P7
P8
DS
20 ns
PARALLEL OR
SERIAL DATA
INPUT
Q6
90%
50%
10%
tsu
tWH
Q7
90%
50%
10%
tWH
tPLH
90%
50%
10%
CL
VSS
VSS
tTHL
CLOCK OR P/S
INPUT
Q8
20 ns
VDD
Q
OUTPUT
SW 2
tTLH
VDD
VSS
tWL
tPHL
VOH
VOL
tTHL
tWL = tWH = 50% DUTY CYCLE
Figure 4. Switching Time Test Circuit and Waveforms
MC14014B MC14021B
54
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
–A–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–B–
C
L
DIM
A
B
C
D
E
F
G
H
K
L
M
N
–T–
K
N
SEATING
PLANE
M
E
F
J
G
D
16 PL
0.25 (0.010)
16 PL
0.25 (0.010)
M
T A
T B
M
S
INCHES
MIN
MAX
0.750
0.785
0.240
0.295
–––
0.200
0.015
0.020
0.050 BSC
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
19.05
19.93
6.10
7.49
–––
5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0_
15 _
0.51
1.01
S
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
16
9
1
8
B
F
C
L
S
–T–
SEATING
PLANE
K
H
G
D
J
16 PL
0.25 (0.010)
MOTOROLA CMOS LOGIC DATA
M
T A
M
M
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
MC14014B MC14021B
55
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
–B–
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
–T–
SEATING
PLANE
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
J
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
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MC14014B MC14021B
56
◊
*MC14014B/D*
MOTOROLA CMOS LOGIC
DATA
MC14014B/D