MOTOROLA MC14513BCL

SEMICONDUCTOR TECHNICAL DATA
L SUFFIX
CERAMIC
CASE 726
CMOS MSI (Low–Power Complementary MOS)
The MC14513B BCD–to–seven segment latch/decoder/driver is
constructed with complementary MOS (CMOS) enhancement mode devices
and NPN bipolar output drivers in a single monolithic structure. The circuit
provides the functions of a 4–bit storage latch, an 8421 BCD–to–seven
segment decoder, and has output drive capability. Lamp test (LT), blanking
(BI), and latch enable (LE) inputs are used to test the display, to turn–off or
pulse modulate the brightness of the display, and to store a BCD code,
respectively. The Ripple Blanking Input (RBI) and Ripple Blanking Output
(RBO) can be used to suppress either leading or trailing zeroes. It can be
used with seven–segment light emitting diodes (LED), incandescent,
fluorescent, gas discharge, or liquid crystal readouts either directly or
indirectly.
Applications include instrument (e.g., counter, DVM, etc.) display driver,
computer/calculator display driver, cockpit display driver, and various clock,
watch, and timer uses.
•
•
•
•
•
•
•
•
•
•
•
P SUFFIX
PLASTIC
CASE 707
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
TA = – 55° to 125°C for all packages.
PIN ASSIGNMENT
Low Logic Circuit Power Dissipation
High–current Sourcing Outputs (Up to 25 mA)
Latch Storage of Binary Input
Blanking Input
Lamp Test Provision
Readout Blanking on all Illegal Input Combinations
Lamp Intensity Modulation Capability
Time Share (Multiplexing) Capability
Adds Ripple Blanking In, Ripple Blanking Out to MC14511B
Supply Voltage Range = 3.0 V to 18 V
Capable of Driving Two Low–Power TTL Loads, One Low–power
Schottky TTL Load to Two HTL Loads Over the Rated Temperature
Range.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
B
1
18
VDD
C
2
17
f
LT
3
16
g
BI
4
15
a
LE
5
14
b
D
6
13
c
A
7
12
d
RBI
VSS
8
11
e
9
10
RBO
DC Supply Voltage
Symbol
Value
a
g
f
e
b
c
d
DISPLAY
0
1
2
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Rating
Plastic
Ceramic
3
4
5
6
7
8
9
TRUTH TABLE
Unit
Inputs
RBI LE BI LT
Outputs
D C B A RBO a b c d e f g Display
VDD
– 0.5 to + 18
V
X
X
X
0
X X X X
+
1 1 1 1 1 1 1
8
Vin
– 0.5 to VDD + 0.5
V
X
X
0
1
X X X X
+
0 0 0 0 0 0 0
Blank
DC Current Drain per Input Pin
I
10
mA
1
0
0
0
1
1
1
1
0 0 0 0
0 0 0 0
1
0
0 0 0 0 0 0 0
1 1 1 1 1 1 0
Blank
0
Operating Temperature Range
TA
– 55 to + 125
°C
Power Dissipation, per Package†
PD
500
mW
Storage Temperature Range
Tstg
– 65 to + 150
_C
X
X
X
X
X
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
0
0
0
0
0
1
1
0
1
1
1
1
1
0
1
0
1
1
1
0
1
1
0
1
0
1
0
0
0
0
0
0
1
1
0
1
1
1
1
1
2
3
4
5
Maximum Continuous Output Drive Current
(Source) per Output
IOHmax
25
mA
Maximum Continuous Output Power
(Source) per Output ‡
POHmax
50
mW
X
X
X
X
X
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
0
1
1
1
1
0
0
1
1
1
0
1
0
1
1
0
1
0
1
0
0
1
0
1
1
0
1
0
1
1
0
6
7
8
9
Blank
X
X
X
X
X
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Blank
Blank
Blank
Blank
Blank
X
1
1
1
X X X X
†
Input Voltage, All Inputs
‡POHmax = IOH (VDD – VOH)
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
*
*
X = Don’t Care
†RBO = RBI (D C B A), indicated by other rows of table
*Depends upon the BCD code previously applied when LE = 0
REV 3
1/94
MC14513B
Motorola, Inc. 1995
376
MOTOROLA CMOS LOGIC DATA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
– 55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
5.0
10
15
4.1
9.1
14.1
—
—
—
4.1
9.1
14.1
5.0
10
15
—
—
—
4.1
9.1
14.1
—
—
—
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
5.0
4.1
—
3.9
—
3.4
—
—
—
—
—
—
—
4.1
—
3.9
—
3.4
—
4.57
4.24
4.12
3.94
3.70
3.54
—
—
—
—
—
—
4.1
—
3.5
—
3.0
—
—
—
—
—
—
—
(IOH = 0 mA)
(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 15 mA)
(IOH = 20 mA)
(IOH = 25 mA)
10
9.1
—
9.0
—
8.6
—
—
—
—
—
—
—
9.1
—
9.0
—
8.6
—
9.58
9.26
9.17
9.04
8.90
8.75
—
—
—
—
—
—
9.1
—
8.6
—
8.2
—
—
—
—
—
—
—
Vdc
(IOH = 0 mA)
(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 15 mA)
(IOH = 20 mA)
(IOH = 25 mA)
15
14.1
—
14
—
13.6
—
—
—
—
—
—
—
14.1
—
14
—
13.6
—
14.59
14.27
14.18
14.07
13.95
13.80
—
—
—
—
—
—
14.1
—
13.6
—
13.2
—
—
—
—
—
—
—
Vdc
Characteristic
Symbol
Output Voltage — Segment Outputs
“0” Level
Vin = VDD or 0
VOL
“1” Level
VOH
Output Voltage — RBO Output
“0” Level
Vin = VDD or 0
VOL
“1” Level
VOH
Vin = 0 or VDD
Vin = 0 or VDD
Input Voltage #
“0” Level
(VO = 3.8 or 0.5 Vdc)
(VO = 8.8 or 1.0 Vdc)
(VO = 13.8 or 1.5 Vdc)
VIL
(VO = 0.5 or 3.8 Vdc) “1” Level
(VO = 1.0 or 8.8 Vdc)
(VO = 1.5 or 13.8 Vdc)
VIH
Output Drive Voltage — Segments
(IOH = 0 mA)
Source
(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 15 mA)
(IOH = 20 mA)
(IOH = 25 mA)
VOH
Unit
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
(continued)
This device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this
high-impedance circuit. A destructive high current mode may occur if Vin and Vout is not constrained to the range VSS ≤ (Vin or
Vout) ≤ VDD.
Due to the sourcing capability of this circuit, damage can occur to the device if VDD is applied, and the outputs are shorted to
VSS and are at a logical 1 (See Maximum Ratings).
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD).
MOTOROLA CMOS LOGIC DATA
MC14513B
377
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS — continued (Voltages Referenced to VSS)
Characteristic
Symbol
Output Drive Current — RBO Output
(VOH = 2.5 V)
Source
(VOH = 9.5 V)
(VOH = 13.5 V)
IOH
(VOL = 0.4 V)
(VOL = 0.5 V)
(VOL = 1.5 V)
– 55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
5.0
10
15
– 0.40
– 0.21
– 0.81
—
—
—
– 0.32
– 0.17
– 0.66
– 0.64
– 0.34
– 1.30
—
—
—
– 0.22
– 0.12
– 0.46
—
—
—
5.0
10
15
0.18
0.47
1.80
—
—
—
0.15
0.38
1.50
0.29
0.75
2.90
—
—
—
0.10
0.26
1.0
—
—
—
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
Unit
mAdc
Sink
IOL
Output Drive Current — Segments
(VOL = 0.4 V)
Sink
(VOL = 0.5 V)
(VOL = 1.5 V)
IOL
Input Current
Iin
15
—
± 0.1
—
± 0.00001
± 0.1
—
± 1.0
µAdc
Input Capacitance
Cin
—
—
—
—
5.0
7.5
—
—
pF
Quiescent Current
(Per Package) Vin = 0 or VDD,
Iout = 0 µA
IDD
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
IT
5.0
10
15
mAdc
mAdc
IT = (1.9 µA/kHz) f + IDD
IT = (3.8 µA/kHz) f + IDD
IT = (5.7 µA/kHz) f + IDD
µAdc
#Noise immunity specified for worst–case input combination.
Noise Margin for both “1” and “0” level =
1.0 Vdc min @ VDD = 5.0 Vdc
2.0 Vdc min @ VDD = 10 Vdc
2.5 Vdc min @ VDD = 15 Vdc
** The formulas given are for the typical characteristics only at 25_C.
ā
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + 3.5 x 10–3 (CL – 50) VDDf
where: IT is in µA (per package), CL in pF, VDD in Vdc, and f in kHz is input frequency.
Input LE and RBI low, and Inputs D, BI and LT high.
f in respect to a system clock.
All outputs connected to respective CL loads.
20 ns
20 ns
A, B, AND C
90%
50%
1
2f
VDD
10%
50% DUTY CYCLE
ANY OUTPUT
VSS
VOH
50%
VOL
Figure 1. Dynamic Power Dissipation Signal Waveforms
MC14513B
378
MOTOROLA CMOS LOGIC DATA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic
Output Rise Time — Segment Outputs
Output Rise Time — RBO Output
Symbol
Typ
Max
5.0
10
15
—
—
—
40
30
25
80
60
50
5.0
10
15
—
—
—
480
240
190
960
480
380
5.0
10
15
—
—
—
125
75
65
250
150
130
Output Fall Time — RBO Outputs
tTHL = (3.25 ns/pF) CL + 107.5 ns
tTHL = (1.35 ns/pF) CL + 67.5 ns
tTHL = (0.95 ns/pF) CL + 62.5 ns
tTHL
5.0
10
15
—
—
—
270
135
110
540
270
220
Propagation Delay Time — A, B, C, D Inputs*
tPLH = (0.40 ns/pF) CL + 620 ns
tPLH = (0.25 ns/pF) CL + 237.5 ns
tPLH = (0.20 ns/pF) CL + 165 ns
tPLH
5.0
10
15
—
—
—
640
250
175
1280
500
350
tPHL
5.0
10
15
—
—
—
720
290
200
1440
580
400
tPLH
5.0
10
15
—
—
—
600
200
150
750
300
220
5.0
10
15
—
—
—
485
200
160
970
400
320
5.0
10
15
—
—
—
313
125
90
625
250
180
Unit
ns
tTLH
tTHL
Propagation Delay Time — RBI and BI Inputs*
tPLH = (1.05 ns/pF) CL + 547.5 ns
tPLH = (0.45 ns/pF) CL + 177.5 ns
tPLH = (0.30 ns/pF) CL + 135 ns
Min
tTLH
Output Fall Time — Segment Outputs*
tTHL = (1.5 ns/pF) CL + 50 ns
tTHL = (0.75 ns/pF) CL + 37.5 ns
tTHL = (0.55 ns/pF) CL + 37.5 ns
tPHL = (1.3 ns/pF) CL + 655 ns
tPHL = (0.60 ns/pF) CL + 260 ns
tPHL = (0.35 ns/pF) CL + 182.5 ns
All Types
VDD
Vdc
ns
ns
ns
ns
ns
ns
tPHL = (0.85 ns/pF) CL + 442.5 ns
tPHL = (0.45 ns/pF) CL + 177.5 ns
tPHL = (0.35 ns/pF) CL + 142.5 ns
tPHL
Propagation Delay Time — LT Input*
tPLH = (0.45 ns/pF) CL + 290.5 ns
tPLH = (0.25 ns/pF) CL + 112.5 ns
tPLH = (0.20 ns/pF) CL + 80 ns
tPLH
tPHL = (1.3 ns/pF) CL + 248 ns
tPHL = (0.45 ns/pF) CL + 102.5 ns
tPHL = (0.35 ns/pF) CL + 72.5 ns
tPHL
5.0
10
15
—
—
—
313
125
90
625
250
180
ns
Setup Time
tsu
5.0
10
15
100
40
30
—
—
—
—
—
—
ns
Hold Time
th
5.0
10
15
60
40
30
—
—
—
—
—
—
ns
tWL(LE)
5.0
10
15
520
220
130
260
110
65
—
—
—
ns
Latch Enable Pulse Width
ns
ns
* The formulas given are for the typical characteristics only.
MOTOROLA CMOS LOGIC DATA
MC14513B
379
20 ns
VDD
20 ns
90%
50%
10%
INPUT C
VSS
tPHL
tPLH
VOH
OUTPUT g
VOL
tTHL
tTLH
a. Data Propagation Delay: Inputs RBI, D and LE low, and Inputs A, B, BI and LT high.
20 ns
20 ns
VDD
90%
50%
10%
INPUT C
tPLH
VSS
tPHL
VOH
90%
OUTPUT RBO
50%
10%
tTLH
VOL
tTHL
b. Inputs A, B, D and LE low, and Inputs RBI, BI and LT high.
20 ns
VDD
90%
50%
LE
10%
VSS
th
tsu
INPUT C
VDD
50%
VSS
VOH
OUTPUT g
VOL
c. Setup and Hold Times: Input RBI and D low, Inputs A, B, BI and LT high.
20 ns
20 ns
90%
50%
LE
VDD
10%
VSS
tWL(LE)
d. Pulse Width: Data DCBA strobed into latches.
Figure 2. Dynamic Signal Waveforms
MC14513B
380
MOTOROLA CMOS LOGIC DATA
CONNECTIONS TO VARIOUS DISPLAY READOUTS
LIGHT EMITTING DIODE (LED) READOUT
VDD
VDD
COMMON
ANODE LED
COMMON
CATHODE LED
≈ 1.7 V
≈ 1.7 V
VSS
VSS
INCANDESCENT READOUT
VDD
VDD
FLUORESCENT READOUT
VDD
**
DIRECT
(LOW BRIGHTNESS)
FILAMENT
(SUPPLY)
VSS
VSS
GAS DISCHARGE READOUT
VDD
APPROPRIATE
VOLTAGE
VSS OR APPROPRIATE
VOLTAGE BELOW VSS.
LIQUID CRYSTAL (LC) READOUT
EXCITATION
(SQUARE WAVE,
VSS TO VDD)
VDD
1/4 OF MC14070B
VSS
** A filament pre–warm resistor is recommended to reduce
filament thermal shock and increase the effective cold
resistance of the filament.
MOTOROLA CMOS LOGIC DATA
VSS
Direct dc drive of LC’s not recommended for life of LC readouts.
MC14513B
381
LOGIC DIAGRAM
BI 4
15 a
A 7
14 b
13 c
B 1
12 d
11 e
17 f
C 2
16 g
LT 30
10 RBO
RBI 8
D 6
LE 5
TYPICAL APPLICATIONS FOR RIPPLE BLANKING
LEADING EDGE ZERO SUPPRESSION
DISPLAYS
CONNECT TO
a –– – –– g
RBI
VDD (1) D C
RBO
1
B A
a–– – –– g
RBI
D C
MC14513B
382
0
0
0
(0)
0
B
A
1
RBI
D C
MC14513B
MC14513B
INPUT
CODE
a–– – –– g
RBO
0
0
0
(0)
0
a–– – –– g
RBO
B
A
0
D C
MC14513B
0
1
0
(5)
a–– – –– g
RBO
RBI
B
A
0
D C
MC14513B
1
0
0
0
(0)
a–– – – –g
RBO
RBI
B
A
0
D C
MC14513B
0
0
0
0
(1)
1
RBO
RBI
B
A
0
MC14513B
0
0
1
1
(3)
MOTOROLA CMOS LOGIC DATA
TYPICAL APPLICATIONS FOR RIPPLE BLANKING (Cont)
TRAILING EDGE ZERO SUPPRESSION
DISPLAYS
0
a–– – –– g
RBO
RBI
B A
D C
a –– – –– g
0
RBO
D C
1
0
(5)
1
B
A
0
RBO
D C
MC14513B
MC14513B
0
a –– – ––g
RBI
0
0
0
0
(0)
MOTOROLA CMOS LOGIC DATA
a–– – –– g
RBI
B
A
0
RBO
D C
MC14513B
0
0
0
(1)
a –– – ––g
RBO
RBI
B
A
1
D C
MC14513B
1
0
0
1
(3)
a –– – ––g
RBO
RBI
B
A
1
D C
MC14513B
1
0
0
0
(0)
0
CONNECT TO
RBI
B
A
VDD (1)
MC14513B
0
0
0
(0)
0
INPUT CODE
MC14513B
383
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 726–04
ISSUE G
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F FOR FULL LEADS. HALF
LEADS OPTIONAL AT LEAD POSITIONS 1, 9,
10, AND 18.
–A–
18
10
1
9
–B–
OPTIONAL LEAD
CONFIGURATION (1, 9, 10, 18)
DIM
A
B
C
D
F
G
J
K
L
M
N
L
C
N
–T–
K
SEATING
PLANE
F
M
G
D 18 PL
0.25 (0.010)
J
M
T A
18 PL
0.25 (0.010)
S
M
P SUFFIX
PLASTIC DIP PACKAGE
CASE 707–02
ISSUE C
18
10
B
1
9
T B
C
N
F
H
D
K
SEATING
PLANE
G
M
J
MILLIMETERS
MIN
MAX
22.35
23.11
6.10
7.49
–––
5.08
0.38
0.53
1.40
1.78
2.54 BSC
0.20
0.30
3.18
4.32
7.62 BSC
0_
15_
0.51
1.02
S
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
A
L
INCHES
MIN
MAX
0.880
0.910
0.240
0.295
–––
0.200
0.015
0.021
0.055
0.070
0.100 BSC
0.008
0.012
0.125
0.170
0.300 BSC
0_
15 _
0.020
0.040
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MILLIMETERS
MIN
MAX
22.22
23.24
6.10
6.60
3.56
4.57
0.36
0.56
1.27
1.78
2.54 BSC
1.02
1.52
0.20
0.30
2.92
3.43
7.62 BSC
0_
15_
0.51
1.02
INCHES
MIN
MAX
0.875
0.915
0.240
0.260
0.140
0.180
0.014
0.022
0.050
0.070
0.100 BSC
0.040
0.060
0.008
0.012
0.115
0.135
0.300 BSC
0_
15 _
0.020
0.040
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MC14513B
384
◊
*MC14513B/D*
MOTOROLA CMOS LOGIC
DATA
MC14513B/D