SEMICONDUCTOR TECHNICAL DATA The MC14566B industrial time base generator is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. This device consists of a divide–by–10 ripple counter and a divide–by–5 or divide–by–6 ripple counter to permit stable time generation from a 50 or 60 Hz line. By cascading this device as divide–by–60 counters, seconds and minutes can be counted and are available in BCD format at the circuit outputs. An internal monostable multivibrator is included whose output can be used as a reset or clock pulse providing additional frequency flexibility. Also a pin has been included to allow divide–by–5 counting for generating 1.0 Hz from European 50 Hz line. Pin 11 = VDD will cause ÷ 5. • • • • • • L SUFFIX CERAMIC CASE 620 P SUFFIX PLASTIC CASE 648 D SUFFIX SOIC CASE 751B Negative Edge Triggered Counters for Ease of Cascading Pulse Shapers on Counter Inputs Accept Slow Input Rise Times Monostable Multivibrator Positive or Negative Edge Triggered Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load Over the Rated Temperature Range ORDERING INFORMATION ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC TA = – 55° to 125°C for all packages. MAXIMUM RATINGS* (Voltages Referenced to VSS) Parameter Symbol VDD DC Supply Voltage Value Unit PIN ASSIGNMENT – 0.5 to + 18.0 V CA 1 16 VDD Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V RESET 2 15 Input or Output Current (DC or Transient), per Pin ± 10 CB Iin, Iout mA Q0A 3 14 Q2B Q1A 4 13 Q1B Q2A 5 12 Q0B Q3A 6 11 B5/B6 B 7 10 Qm VSS 8 9 PD Power Dissipation, per Package† Tstg Storage Temperature 500 – 65 to + 150 mW _C TL Lead Temperature (8–Second Soldering) 260 _C * Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C A BLOCK DIAGRAM CA ÷ 10 1 PULSE SHAPER Q0A Q1A C R RESET ÷ 5/÷ 6 CONTROL Q2A Q3A B A 5 6 BCD OUT 2 R 11 Q0B Q1B CB ÷ 5/÷ 6 3 4 15 PULSE SHAPER 7 9 C Q2B 12 13 14 BCD OUT MONO– STABLE MULTI– VIBRATOR 10 Qm REV 3 1/94 MOTOROLA Motorola, Inc. 1995 CMOS LOGIC DATA MC14566B 1 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Output Voltage Vin = VDD or 0 Symbol – 55_C 25_C 125_C VDD Vdc Min Max Min Typ # Max Min Max Unit “0” Level VOL 5.0 10 15 — — — 0.05 0.05 0.05 — — — 0 0 0 0.05 0.05 0.05 — — — 0.05 0.05 0.05 Vdc “1” Level VOH 5.0 10 15 4.95 9.95 14.95 — — — 4.95 9.95 14.95 5.0 10 15 — — — 4.95 9.95 14.95 — — — Vdc 5.0 10 15 — — — 1.5 3.0 4.0 — — — 2.25 4.50 6.75 1.5 3.0 4.0 — — — 1.5 3.0 4.0 5.0 10 15 3.5 7.0 11 — — — 3.5 7.0 11 2.75 5.50 8.25 — — — 3.5 7.0 11 — — — 5.0 5.0 10 15 – 3.0 – 0.64 – 1.6 – 4.2 — — — — – 2.4 – 0.51 – 1.3 – 3.4 – 4.2 – 0.88 – 2.25 – 8.8 — — — — – 1.7 – 0.36 – 0.9 – 2.4 — — — — IOL 5.0 10 15 0.64 1.6 4.2 — — — 0.51 1.3 3.4 0.88 2.25 8.8 — — — 0.36 0.9 2.4 — — — mAdc Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc Input Capacitance (Vin = 0) Cin — — — — 5.0 7.5 — — pF Quiescent Current (Per Package) IDD 5.0 10 15 — — — 5.0 10 20 — — — 0.005 0.010 0.015 5.0 10 20 — — — 150 300 600 µAdc IT 5.0 10 15 Vin = 0 or VDD Input Voltage “0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) VIL “1” Level VIH (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Vdc Vdc IOH Source Sink Total Supply Current**† (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) mAdc IT = (1.0 µA/kHz) f + IDD IT = (2.0 µA/kHz) f + IDD IT = (3.0 µA/kHz) f + IDD µAdc #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. ** The formulas given are for the typical characteristics only at 25_C. †To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. MC14566B 2 MOTOROLA CMOS LOGIC DATA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C) Characteristic Symbol Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns tTLH, tTHL Propagation Delay Time, Clock to Q3A tPLH, tPHL = (1.7 ns/pF) CL + 1365 ns tPLH, tPHL = (0.66 ns/pF) CL + 497 ns tPLH, tPHL = (0.5 ns/pF) CL + 295 ns tPLH, tPHL Propagation Delay Time, Reset to Q3A tPHL = (1.7 ns/pF) CL + 845 ns tPHL = (0.66 ns/pF) CL + 282 ns tPHL = (0.5 ns/pF) CL + 185 ns tPHL Clock Pulse Width VDD Min Typ # Max 5.0 10 15 — — — 100 50 40 200 100 80 5.0 10 15 — — 1450 530 320 4500 1500 1000 5.0 10 15 — — — 930 315 210 3000 1000 750 5.0 10 15 1200 400 270 400 125 90 — — — 5.0 10 15 1200 400 270 400 125 90 — — — 5.0 10 15 — — — 1.0 2.5 4.2 0.3 1.0 1.5 ns ns ns tWH(cl) Reset Pulse Width ns tWH(R) Clock Pulse Frequency ns fcl Clock Pulse Rise and Fall Time MHz tTLH, tTHL — 5.0 10 15 No Limit tWH(Qm) Monostable Multivibrator Pulse Width Unit ns 5.0 10 15 1200 400 300 2800 900 600 — — — * The formulas given are for the typical characteristics only at 25_C. #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. VDD 20 ns 20 ns VDD 90% 50% 10% 500 µF ID Vin VSS VARIABLE WIDTH Vin PULSE GENERATOR CA CB RESET ÷ 5/÷ 6 CONTROL B A Q0A Q1A Q2A Q3A Q0B Q1B Q2B Qm VSS CL CL CL CL CL CL CL CL Figure 1. Power Dissipation Test Circuit and Waveform MOTOROLA CMOS LOGIC DATA MC14566B 3 VDD CA PROGRAMMABLE PULSE GENERATOR CB RESET ÷ 5/÷ 6 CONTROL B A Q0A Q1A Q2A Q3A Q0B Q1B Q2B Qm CL VSS CL CL CL CL CL CL CL NOTE: Assume ÷ 10 Counter at “6” and ÷ 5/ ÷ 6 Counter at “2” at beginning of sequence. 20 ns ÷ 10 OR ÷ 5/÷ 6 90% CLOCK AND B tWH(cl) 50% 10% fcl 20 ns 90% RESET Q3A OR Q2B 10% tPLH tWH(R) tPHL 90% 10% tPLH 50% tTLH 50% Qm 50% tWH(Qm) tTHL 50% t WHQm Figure 2. Switching Time Test Circuit and Waveforms MC14566B 4 MOTOROLA CMOS LOGIC DATA TIMING DIAGRAM Divide–By–10 Counter 0 1 2 3 4 5 6 7 8 9 0 1 0 1 2 3 4 0 CLOCK RESET Q0 Q1 Q2 Q3 Divide–By–5/Divide–By–6 0 1 2 3 4 5 CLOCK RESET CONTROL ÷ 5/÷ 6 Q0 Q1 Q2 Monostable Multivibrator A B Qm = DON’T CARE MOTOROLA CMOS LOGIC DATA MC14566B 5 APPLICATION — 12 HOUR CLOCK ÷ 5/÷ 6 < 1.0 M* 60 Hz ÷ 10 Q0 Q1 Q2 Q3 Q0 C C Q1 > 1500 pF* Q2 ÷ 10 C A B Qm + VDD Q0 A Q1 B Qm Q2 SECONDS ÷ 10 ÷ 5/÷ 6 Q0 Q1 Q2 Q3 C TENTH SECONDS ÷ 5/÷ 6 Q0 Q1 Q2 Q3 C VDD C Q0 A Q1 B Qm Q2 MINUTES A B C MC14011B ÷ 10 Q0 C Q1 Q2 R Q3 ÷ 5/÷ 6 C HOURS Q0 A Q1 B Qm R Q2 D ÷ 5/ ÷ 6 Control not shown = VSS Reset pins not shown = VSS * Care must be taken in the indicated circuit to filter line transients which may cause “false” counting. MC14566B 6 MOTOROLA CMOS LOGIC DATA OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V –A– 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. –B– C L DIM A B C D E F G H K L M N –T– K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M S INCHES MIN MAX 0.750 0.785 0.240 0.295 ––– 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 ––– 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 S P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– 16 9 1 8 B F C L S –T– SEATING PLANE K H G D J 16 PL 0.25 (0.010) MOTOROLA CMOS LOGIC DATA M T A M M DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 MC14566B 7 OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J –A– 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 –B– 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C –T– SEATING PLANE M D 16 PL 0.25 (0.010) M T B S A S J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 Motorola reserves the right to make changes without further notice to any products herein. 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