Freescale Semiconductor, Inc. MOTOROLA Document order number: MC33790/D Rev 6.0, 02/2004 SEMICONDUCTOR TECHNICAL DATA Advance Information 33790 Freescale Semiconductor, Inc... Two-Channel Distributed System Interface (DSI) Physical Interface Device The 33790 is a two-channel physical layer interface IC for the Distributed System Interface (DSI) bus. It is designed to meet automotive requirements. It can also be used in nonautomotive applications. It supports bidirectional communication between slave and master ICs. Some slave devices derive a regulated 5.0 V from the bus, which can be used to power sensors, thereby eliminating the need for additional circuitry and wiring. TWO-CHANNEL DISTRIBUTED SYSTEM INTERFACE (DSI) PHYSICAL INTERFACE DEVICE Features • Two Independent DSI Compatible Busses • Pinout Matched to MC68HC55 (SPI to DSI Logic) • Wave-Shaped Bus Output Voltage • Independent Thermal Shutdown and Current Limit • Return Signalling Current Detection • Internal Logic Input Pull-Ups and Pull-Downs • On-Board Charge Pump • 2.0 kV ESD Capability • Communications Rate Up to 150 kbps • Motorola now offers Pb-free packages with sufix code EG EG (Pb free) SUFFIX DW SUFFIX CASE 751G ORDERING INFORMATION Device Temperature Range (TJ) Package MC33790DW/R2 -40°C to 150°C 16 SOICW MC33790EG/R2 -40°C to 150°C 16 SOICW 33790 Simplified Application Diagram 33790 MC68HC55 +5.0 V DSI0F VDD DSI0S GND DSI0R DSI0O DSI1F VSUP DSI1S DSI1O DSI1R GND 0.1 µF DSIBUS0 +25 V DSIBUS1 CPCAP 33793 33791 BUS_IN BUS_OUT BUS_IN BUS_OUT DSI Slave Device BUS_IN 33927 BUS_IN This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Motorola, Inc. 2003 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... + VSUP (IDLE Level) CPCAP VDD (+5.0 V) Internal Bias Charge Pump Bus Supply Voltage Bus Current Sense WaveShaper DSI0F DSI0S DSI0O DSI Bus Transmitter Driver DSI0R GND + DSI1F DSI1S Bus Current Sense WaveShaper DSI1O DSI Bus Transmitter Driver DSI1R Figure 1. 33790 Simplified Internal Block Diagram 33790 2 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. DSI0F 1 16 VDD DSI0S 2 15 GND DSI0R 3 14 DSI0O DSI1F 4 13 VSUP DSI1S 5 12 DSI10 DSI1R 6 11 GND NC 7 10 NC CPCAP 8 9 NC Freescale Semiconductor, Inc... PIN FUNCTION DESCRIPTION Pin Pin Name Description 1 DSI0F This logic input controls the frame output for DSI channel 0 in accordance with Table 1, page 8. 2 DSI0S This logic input controls the signalling output for DSI channel 0 in accordance with Table 1, page 8. 3 DSI0R This logic output provides the return data for DSI channel 0 in accordance with Table 1, page 8. 4 DSI1F This logic input controls the frame output for DSI channel 1 in accordance with Table 1, page 8. 5 DSI1S This logic input controls the signalling output for DSI channel 1 in accordance with Table 1, page 8. 6 DSI1R This logic output provides the return data for DSI channel 1 in accordance with Table 1, page 8. 7 NC 8 CPCAP 9 NC Unused. 10 NC Unused. 11 GND 12 DSI1O 13 VSUP 14 DSI0O 15 GND Circuit and bus ground return. 16 VDD 5.0 V logic supply input. Unused. Used to store and filter charge pump output. Circuit and bus ground return. DSI bus 1 input/output. Idle level supply input. The voltage supplied to this pin sets the idle level on the DSI bus. DSI bus 0 input/output. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33790 3 Freescale Semiconductor, Inc. MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted. Rating Symbol Value VSUP -0.5 to 25 VSUP (t) 40 V Supply Voltage Continuous Load Dump - t < 300 ms VDD -0.3 to 5.5 DSIxS, DSIxF (Note 1) -0.3 to VDD +0.3 DSIxO (Note 1) -0.3 to VSUP +0.3 TSTG -55 to 150 °C TJ -40 to 150 °C TSOLDER 230 °C VDD 0 to 10 mA DSIxR -2.5 to 5.0 VSUP 500 Thermal Resistance Junction to Ambient RθJA 45 °C/W Thermal Shutdown TSD 155 to 190 °C Human Body Model (Note 2) VESD1 ±2000 Machine Model (Note 3) VESD2 ±200 Maximum Voltage on Input/Output Pins Storage Temperature Operating Junction Temperature Freescale Semiconductor, Inc... Unit Lead Temperature (IR Reflow Soldering for >60 s @ >183°C), 10 s @ >215°C Continuous Current per Pin V V ESD Voltage (All Pins) Notes 1. R = 0 Ω. 2. ESD1 performed in accordance with the Human Body Model (CZAP =100pF, RZAP =1500 Ω). 3. 33790 4 ESD2 performed in accordance with the Machine Model (CZAP =200 pF, RZAP =0 Ω). MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, 8.0 V ≤ VSUP ≤ 25.0 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Characteristic Symbol Min Typ Max Unit SUPPLY mA ISUP Supply Current /Channel (Not Including IOUT) DSIx0 = Idle Voltage, -100 mA ≤ IOUT ≤ 0 mA ISUPI – 1.35 3.25 DSIx0 = Output High Voltage, IOUT = 12 mA ISUPH – 5.0 9.00 IDD – 0.5 1.0 – – 10 4.175 4.5 4.825 1.325 1.5 1.675 IDD Supply Current /Channel mA BUS TRANSMITTER Freescale Semiconductor, Inc... VSUP to DSIxO ON Resistance (During Idle) IOUT = -100 mA Output High Voltage Ω RDS(on) V DSIVOH DSIx0 (-15 mA ≤ IOUT ≤ 1.0 mA) V DSIVOL Output Low Voltage DSIx0 (-15 mA ≤ IOUT ≤ 1.0 mA) Output High-Side Current Limit (Note 4) ICLH -100 – -200 mA Output Low-Side Current Limit (Note 4) ICLL 110 – 220 mA -200 – 50 IRH -5.0 -6.0 -7.0 mA VIN(TH) 1.10 – 2.20 V 0.8 * VDD – VDD 0.0 – 0.2 * VDD Input Leakage µA DSIIB DSIxO When DSIxF Is High and DSIxS Is Low (0 V ≤ DSIxO ≤ Min (VSUP = 16.5 V)) BUS RECEIVER Return Current Threshold MICROCONTROLLER INTERFACE Logic Input Thresholds DSIxS, DSIxF Output High Voltage V VOH DSIxR Pin = -0.5 mA Output Low Voltage V VOL DSIxR Pin = 1.0 mA Internal Pull-Up for DSIxF IIL -100 – -10 µA Internal Pull-Down for DSIxS IIH 10 – 100 µA Notes 4. After 10 µs settling time (assured by design). MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33790 5 Freescale Semiconductor, Inc. DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, 8.0 V ≤ VSUP ≤ 25.0 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Characteristic Symbol Min Typ Max Unit Microcontroller Signal Cycle Time t cyc 6.6 – 1000 µs Microcontroller Signal Low Time t cycL 2.0 – 667 µs Microcontroller Signal High Time t cycH 2.0 – 667 µs Microcontroller Signal Duty Cycle for Logic Zero DCLo 30 33 36 % Microcontroller Signal Duty Cycle for Logic One DCHi 60.0 66.7 72.0 % Microcontroller Signal Slew Time (Note 5) t slew – – 500 ns Frame Start to Signal Delay Time t DLY1 t cyc -0.1 t cyc t cyc +0.1 µs Signal End to Frame End Delay Time t DLY2 1.0 – – µs Rise Time (Note 5) t RISE 0 – 100 ns Fall Time (Note 5) t FALL 0 – 100 ns Freescale Semiconductor, Inc... MICROCONTROLLER INTERFACE BUS TRANSMITTER Idle to Frame and Frame to Idle Slew Rate t slew (FRAME) C ≤ 5.0 nF Signal High to Low and Signal Low to High Slew Rate V/µs 3.0 6.0 10.0 3.0 4.5 8.0 t DVLD1 2.44 – 6.56 t DVLD2 0.25 – 1.3 tDVLD3 0.25 – 1.3 tDVLD4 0.25 – 1.3 t DRH – 400 750 t DRL – 400 750 t slew (SIGNAL) C ≤ 5.0 nF V/µs µs Data Valid (VSUPx = 25 V, CL ≤ 5.0 nF) DSIxF, VIN(TH) to DSIxO = 5.3 V DSIxS, VIN(TH) to DSIxO = 2.6 V DSIxS, VIN(TH) to DSIxO = 3.4 V DSIxF, VIN(TH) to DSIxO = 7.0 V BUS RECEIVER Receiver Delay Time I = 9.0 mA to DSIxR = 0.8 * VDD I = -1.0 mA to DSIxR = 0.2 * VDD ns Notes 5. Slew times and rise and fall times between 10% and 90% of output high and low levels. 33790 6 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. tcyc tcyc tDLY2 tcycH 5.0 V DSIxS VIN(TH) 0V tRISE tcycL tRISE tDLY1 tFALL 5.0 V DSIxF Freescale Semiconductor, Inc... VIN(TH) 0V tDVLD4 tslew(FRAME) tDVLD1 25 V 7.0 V tDVLD3 DSIxO 5.0 V tslew(SIGNAL) tDVLD2 4.5 V 1.5 V IOUT 6.0 mA 0 mA tDRH tDRL 5.0 V DSIxR 0V Figure 2. Timing Characteristics MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33790 7 Freescale Semiconductor, Inc. SYSTEM/APPLICATION INFORMATION INTRODUCTION The 33790 is designed to provide the interface between logic and the DSI bus. It accepts signals with a typical 0 V to 5.0 V logic level to control the state of the bus output (Idle Level, Logic High Level, Logic Low Level, and High Impedance). It detects the current drawn from the bus output during signaling and outputs a 0 V to 5.0 V logic level corresponding to the bus current being above (Logic [1] out) the bus return logic [1] current or below (Logic [0] out). The 33790 contains current limiting of the bus outputs as required by the DSI Bus specification and thermal shutdown to protect itself from damage. Two independent DSI bus outputs are provided by the IC. FUNCTIONAL DESCRIPTION Freescale Semiconductor, Inc... Bus Driver and Receiver The Wave-Shaper converts the 0 V to 5.0 V logic inputs from DSIxF (frame) and DSIxS (signal) to a wave-shaped signal on the DSIxO output, as shown in the timing diagrams in Figure 2, page 7, and the truth table in Table 1. The Bus Current Sense detects the current being drawn by the device(s) on the bus during signalling (DSIxF=0). If the current is above a set level, DSIxR will be high; otherwise, it is low. Table 1. DSI Bus Truth Table DSIxF DSIxS TLIM DSIR DSIxO 0 0 0 Return Data Low (1.5 V) 0 1 0 Return Data High (4.5 V) 1 0 0 0 High Impedance 1 1 0 0 Idle≥VSUP -0.5 V X X 1 1 High Impedance The current for the idle state is from the supply connected to VSUP and this supply should not be current limited below 250 mA per channel. During idle state, the voltage on the DSI bus will be very close to the VSUP voltage. Internal thermal shutdown circuitry and current limit individually protect the DSIxO outputs from shorts to battery and ground. Typically, the thermal shutdown occurs between 160°C and 170°C. If the junction temperature rises above this temperature, the output drivers for DSIxO are disabled by the thermal shutdown circuitry. The output drivers remain off until the junction temperature decreases below approximately 155°C, at which time the thermal shutdown circuitry turns off and the outputs are re-enabled. Each DSIxO output has a unique thermal sense and shutdown circuit, so a short on one channel does not affect the other channel. Charge Pump The charge pump uses on-board capacitors to step the input voltage up to the voltage needed to drive the on-board transmitter FETs. A filter/storage capacitor is connected to CPCAP to hold the stepped-up voltage. Input Pull-Ups and Pull-Downs Internal current pull-ups are used on the DSIxF pins and pulldowns on the DSIxS pins. If these pins are left unconnected, their associated DSI bus will go to the unused (high impedance) state. APPLICATIONS The 33790 is intended for use in a DSI system. This device supplies the interface between standard logic levels and the voltage and current required for the DSI bus. Two independent DSI busses are supported by this part. The 33790 does not form the timing for the DSI bus. This is done by logic either embedded in a microcontroller or by the MC68HC55, which uses SPI commands and forms DSI protocol for communications over the DSI bus. 33790 8 The pins from the MC68HC55 are made to line up with the pins connecting to the 33790. This includes all the DSIxF, DSIxS, and DSIxR pins. A capacitor attached to CPCAP serves as a charge reservoir for the gate drive charge pump. This circuit creates a voltage that is higher than the source of the N-channel output transistor. This allows turning on of the transistor enough to prevent any significant voltage drop across it. The rest of charge pump electronics are completely self-contained on the IC. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. PACKAGE DIMENSIONS EG (Pb free)SUFFIX DW SUFFIX 16-LEAD SOIC WIDE BODY PLASTIC PACKAGE CASE 751G-04 ISSUE D 0.25 8X PIN'S NUMBER M B 2.65 2.35 A 10.55 10.05 1 0.25 0.10 16 PIN 1 INDEX Freescale Semiconductor, Inc... 16X 4 A A 8 0.49 0.35 0.25 14X 10.45 10.15 1.27 9 7.6 7.4 T B SEATING PLANE 16X 0.1 T 5 0.75 0.25 X45 0.32 0.23 1.0 0.4 SECTION A-A MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 6 M T A B NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DATUMS A AND B TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15mm PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 5. THIS DIMENSION DOES NOT INCLUDE INTER-LEAD FLASH OR PROTRUSIONS. INTER-LEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25mm PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 6. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.62mm. 7 0 For More Information On This Product, Go to: www.freescale.com 33790 9 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... NOTES 33790 10 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... NOTES MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33790 11 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. 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Minato-ku, Tokyo 106-8573, Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 HOME PAGE: http://motorola.com/semiconductors For More Information On This Product, Go to: www.freescale.com MC33790/D