Freescale Semiconductor, Inc. MOTOROLA Document order number: MC33395/D Rev 2.0, 01/2004 SEMICONDUCTOR TECHNICAL DATA Advance Information 33395 33395T Three-Phase Gate Driver IC Freescale Semiconductor, Inc... The 33395 simplifies the design of high-power BLDC motor control design by combining the gate drive, charge pump, current sense, and protection circuitry necessary to drive a three-phase bridge configuration of six N-channel power MOSFETs. Mode logic is incorporated to route a pulse width modulation (PWM) signal to either the low-side MOSFETs or high-side MOSFETs of the bridge, or to provide complementary PWM outputs to both the low- and high-sides of the bridge. THREE-PHASE GATE DRIVER IC Detection and drive circuitry are also incorporated to control a reverse battery protection high-side MOSFET switch. PWM frequencies up to 28 kHz are possible. Built-in protection circuitry prevents damage to the MOSFET bridge as well as the drive IC and includes overvoltage shutdown, overtemperature shutdown, overcurrent shutdown, and undervoltage shutdown. The device is parametrically specified over an ambient temperature range of -40°C ≤ TA ≤ 125°C and 5.5 V ≤ VIGN ≤ 24 V supply. Features • Drives Six N-Channel Low RDS(ON) Power MOSFETs • Built-In Charge Pump Circuitry • Built-In Current Sense Comparator and Output Drive Current Limiting • Built-In PWM Mode Control Logic • Built-In Circuit Protection • Designed for Fractional to Integral HP BLDC Motors • 32-Terminal SOIC Wide Body Surface Mount Package • 33395 Incorporates a <5.0 µs Shoot-Through Suppression Timer • 33395T Incorporates a <1.0 µs Shoot-Through Suppression Timer DWB SUFFIX CASE 1324-02 32-TERMINAL SOICW ORDERING INFORMATION Device MC33395DWB/R2 MC33395TDWB/R2 Temperature Range (TA) Package -40°C to 125°C 32 SOICW 33395 Simplified Application Diagram VPWR 33395 VDD MCU 3 2 3 VIGNP GDH1 GDH2 GDH3 SRC1 SRC2 SRC3 HSE1–3 MODE0–1 GDL1 GDL2 PWM LSE1–3 GDL3 -ISENS AGND PGND N N +ISENS This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Motorola, Inc. 2004 S S VDD For More Information On This Product, Go to: www.freescale.com H H VGDH VIGN VDD CP1H CP1L CP2H CP2L CRES H Freescale Semiconductor, Inc. VIGN Osc. VDD Low Low Voltage Reset Reset Charge Charge Pump Overvoltage Overvoltage Shutdown CP1H CP1L CP2H CP2L Freescale Semiconductor, Inc... CPRES +ISENS + -ISENS - Drive Drive Limiting Limiting L MODE0 MODE1 PWM HSE1 HSE2 HSE3 LSE1 LSE2 LSE3 VGDH Control Control Logic Logic VIGNP Gate Drive Gate Circuits Drive Circuits PGND GDH1 GDH2 GDH3 SRC1 SRC2 SRC3 AGND TEST H Overtemperature Shutdown Shutdown GDL1 GDL2 GDL3 Figure 1. 33395 Simplified Internal Block Diagram 33395 2 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... CP2H CPRES VIGN VGDH VIGNP SRC1 GDH1 GDL1 SRC2 GDH2 GDL2 SRC3 GDH3 GDL3 PGND TEST 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 CP2L CP1H CP1L LSE1 LSE2 LSE3 HSE1 HSE2 HSE3 MODE0 MODE1 PWM VDD AGND +ISENS -ISENS TERMINAL FUNCTION DESCRIPTION Terminal Terminal Name Formal Name 1 CP2H Charge Pump Cap 2 CPRES Charge Pump Reserve Cap 3 VIGN Input Voltage 4 VGDH High-Side Gate Voltage Output full-time gate drive for auxiliary high-side power MOSFET switch 5 VIGNP Input Voltage Protected Input from protected ignition level supply for power functions 6 SRC1 High-Side Sense Sense for high-side source voltage, phase 1 7 GDH1 Gate Drive High Output for gate high-side, phase 1 8 GDL1 Output for Gate Output for gate drive low-side, phase 1 9 SRC2 High-Side Sense Sense for high-side source voltage, phase 2 10 GDH2 Gate Drive High Output for gate high-side, phase 2 11 GDL2 Output for Gate Output for gate drive low-side, phase 2 12 SRC3 High-Side Sense Sense for high-side source voltage, phase 3 13 GDH3 Gate Drive High Output for gate drive high-side, phase 3 14 GDL3 Gate Drive Low Output for gate drive low-side, phase 3 15 PGND Power Ground Ground terminals for power functions 16 Test Test Terminal This should be connected to ground or left open 17 -ISENS IS Minus 18 +ISENS IS Plus 19 AGND Analog Ground 20 VDD Logic Supply Voltage 21 PWM Pulse Width Modulator 22 MODE1 Mode Control Bit 1 Input for mode control selection 23 MODE0 Mode Control Bit 0 Input for mode control selection 24 HSE3 High-Side Enable Input for high-side enable logic, phase 3 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Definition High potential terminal connection for secondary charge pump capacitor Input from external reservoir capacitor for charge pump Input from ignition level supply voltage for power functions Inverting input for current limit comparator Non-inverting input for current limit comparator Ground terminal for logic functions Supply voltage for logic functions Input for pulse width modulated driver duty cycle For More Information On This Product, Go to: www.freescale.com 33395 3 Freescale Semiconductor, Inc. TERMINAL FUNCTION DESCRIPTION (continued) Terminal Name Formal Name 25 HSE2 High-Side Enable Input for high-side enable logic, phase 2 26 HSE1 High-Side Enable Input for high-side enable logic, phase 1 27 LSE3 Low-Side Enable Input for low-side enable logic, phase 3 28 LSE2 Low-Side Enable Input for low-side enable logic, phase 2 29 LSE1 Low-Side Enable Input for low-side enable logic, phase 1 30 CP1L External Pump Capacitor Input from external pump capacitor for charge pump and secondary terminals 31 CP1H External Pump Capacitor Input from external pump capacitor for charge pump and secondary terminals 32 CP2L Charge Pump Capacitor Input from external reservoir, external pump capacitors for charge pump, and secondary terminals Freescale Semiconductor, Inc... Terminal 33395 4 Definition MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted Rating Symbol Value Unit VIGN -15.5 to 40 VDC -0.3 to 65 VDC VIGN Supply Voltage VIGNP Load Dump Survival V IGNPLD VDD Logic Supply Voltage (Fail Safe) VDD -0.3 to 7.0 VDC Logic Input Voltage (LSEn, HSEn, PWM, and MODEn) VIN 0.3 to 7.0 VDC IVIGNStartUp 100 mA Human Body Model (Note 1) VESD1 ±500 Machine Model (Note 2) VESD2 ±200 TSTG -65 to 160 °C Operating Ambient Temperature TA -40 to 125 °C Operating Case Temperature TC -40 to 125 °C Maximum Junction Temperature TJ 150 °C Power Dissipation (TA = 25°C) PD 1.5 W TSOLDER 240 °C RθJA 65 °C/W Start Up Current VIGNP V Freescale Semiconductor, Inc... ESD Voltage Storage Temperature Terminal Soldering Temperature Thermal Resistance, Junction-to-Ambient Notes 1. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω). 2. ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω). MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33395 5 Freescale Semiconductor, Inc. STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions -40°C ≤ TA ≤ 125°C, 5.5 V ≤ VIGNP ≤ 24 V unless otherwise noted. Typical values reflect approximate parameter mean at TA = 25°C under normal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit VIGN Current @ 5.5 V–24 V, VDD = 5.5 V IIGN – 0.2 1.0 mA VIGNP Current @ 5.5 V–24 V, VDD = 5.5 V IIGNP – – 100 mA 25 33 36.5 V 5.5 – 24 V – 1.8 4.0 mA VDD(RESET) 2.5 3.2 4.0 V – 7.0 – – V 5.0 12 25 1.0 2.0 3.0 -0.3 VIGNP 24 VINP(OFFSET) 5.0 14 20 mV VINP(BIAS) -500 -170 500 nA Comparator Input Offset Current IINP(OFFSET) -300 -3.0 300 nA Common Mode Voltage (Note 4) VCMR 0 – VDD -2.0 VDC Comparator Differential Input Voltage (Note 4) VINPdiff -VDD – +VDD V POWER INPUT V Freescale Semiconductor, Inc... VIGNP Overvoltage Shutdown IGNPSD VIGNP Voltage VIGNP VDD Current @ 5.5 VDC, 5.5 V ≤ VIGNP ≤ 24 V IV VDD Low-Voltage Reset Level VDD One-Time Fuse (Logic Supply) DD INPUT/OUTPUT µA IIN Input Current at VDD = 5.5 V LSEn, HSEn, PWM, and MODEn = 3.0 V VTH Input Threshold at VDD = 5.5 V LSEn, HSEn, PWM, and MODEn (Note 3) V VSCRn VSCRn Source Sense Voltage SRC1, SRC2, SRC3 Comparator Input Offset Voltage Comparator Input Bias Current V VCRES -VIGNP Charge Pump Voltage VIGN (Note 5) V VIGNP = 5.5 V, ICRES = 1.0 mA 4.0 6.0 18 VIGNP = 9.0 V, ICRES = 1.0 mA 4.0 7.5 18 VIGNP = 12 V, ICRES = 5.0 mA 4.5 10 18 VIGNP = 24 V, ICRES = 1.0 mA 8.0 16 18 VIGNP = 24 V, ICRES = 5.0 mA 4.5 12 18 VGDHn(on) -V SRCn VGDH Output Voltage with GDHn in ON State V VIGNP = 5.5 V, IGDHn = 1.0 mA 4.0 5.2 18 VIGNP = 12 V, IGDHn = 5.0 mA 4.0 9.0 18 VIGNP = 24 V, IGDHn = 5.0 mA 4.5 11 18 -1.0 0.6 1.0 VGDH Output Voltage with GDHn in OFF State VIGNP = SRCn = 14 V, IGDHn = 1.0 mA V VGDHn(off) Notes 3. Logic inputs LSEn, HSEn, PWM, and MODEn have internal 20 µA internal sinks. 4. Guaranteed by design and characterization. Not production tested. 5. The Charge Pump has a positive temperature coefficient. Therefore the Min’s occur at -40°C, Typ’s at 25°C, and Max’s at 125°C. 33395 6 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions -40°C ≤ TA ≤ 125°C, 5.5 V ≤ VIGNP ≤ 24 V unless otherwise noted. Typical values reflect approximate parameter mean at TA = 25°C under normal conditions unless otherwise noted. Characteristic Symbol Min Typ Max VIGNP = 5.5 V, IGDLn = 1.0 mA 5.0 8.0 18 VIGNP = 12 V, IGDLn = 5.0 mA 8.0 14 18 VIGNP = 24 V, IGDLn = 0.0 mA 8.0 17 19 VIGNP = 24 V, IGDLn = 5.0 mA 8.0 16 19 -1.0 0.3 1.0 160 – 190 Unit INPUT/OUTPUT (continued) VGDL Low-Side Output Voltage GDHn in ON State Freescale Semiconductor, Inc... VGDL Output Voltage GDHn in OFF State VGDL(on) VGDL(off) VIGNP = 14 V, IGDLn = 1.0 mA TLIM Thermal Shutdown (Note 6) V V °C Notes 6. Guaranteed by design and characterization. Not production tested. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33395 7 Freescale Semiconductor, Inc. DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions -40°C ≤ TA ≤ 125°C, 5.5 V ≤ VIGNP ≤ 24 V unless otherwise noted. Typical values reflect approximate parameter mean at TA = 25°C under normal conditions unless otherwise noted. Characteristic Symbol Min Typ Max – 0.35 1.5 – 0.25 1.5 33395 1.0 3.0 5.5 33395T 0.2 0.65 1.0 1.5 2.8 5.0 High-Side (GDHn) and Low-Side Drivers (GDHn) Rise Time (25% to 75%), CISS Value = 2000 pF (Note 7) t RH High-Side (GDHn) and Low-Side Drivers (GDHn) Fall Time (75% to 25%), CISS Value = 2000 pF (Note 7) t FH Freescale Semiconductor, Inc... Shoot-Through Suppression Time Delay (33395) (Note 7), (Note 8) Current Limit Time Delay (Note 9) µs µs µs t D1, t D2 t ILIMDELAY Unit µs Notes 7. See Figure 2, page 9. 8. Shoot-Through Suppression Time Delay is provided to prevent directly connected high- and low-side MOSFETs from being on simultaneously. 9. Current Limit Time Delay: The internal comparator places the device in the current limit mode when the comparator output goes LOW and sets an internal logic bit. This takes a finite amount of time and is stated as the Current Limit Time Delay. 33395 8 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GDHn SRCn (%) Timing Diagram 100 75 25 0 tRH tFH GDLn, Gate V (%) Freescale Semiconductor, Inc... tD1 100 tD2 tFL tRL 75 25 0 TIME Figure 2. Shoot-Through Suppression MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33395 9 Freescale Semiconductor, Inc. SYSTEM /APPLICATION INFORMATION INTRODUCTION The 33395 and 33395T devices are designed to provide the necessary drive and control signal buffering and amplification to enable a DSP or MCU to control a three-phase array of power MOSFETs such as would be required to energize the windings of powerful brushless DC (BLDC) motors. It contains built-in charge pump circuitry so that the MOSFET array may consist entirely of N-Channel MOSFETs. It also contains feedback sensing circuitry and control circuitry to provide a robust overall motor control design. FUNCTIONAL DESCRIPTION Freescale Semiconductor, Inc... Gate Drive Circuits The gate drive outputs (GDH1, GDH2, etc.) supply the peak currents required to turn ON and hold ON the MOSFETs, as well as turn OFF and hold OFF the MOSFETs. By averaging these two values, the proper CPn value can be determined: 0.15 µF 20 = 0.075 µF, lower limit; and 0.15 µF 10 = .015 µF, upper limit Charge Pump The current capability of the charge pump is sufficient to supply the gate drive circuit’s demands when PWM’ing at up to 28 kHz. Two external charge pump capacitors and a reservoir capacitor are required to complete the charge pump’s circuitry. Charge reservoir capacitance is a function of the total MOSFET gate charge (QG) gate drive voltage level relative to the source (VGS) and the allowable sag of the drive level during the turn-on interval (VSAG). CRES can be expressed by the following formula: CRES = QG x VGS 2 x VGS x VSAG - VSAG2 For example, for QG = 60 nC, VGS = 14 V, VSAG = 0.2 V: (60 nC) x (14 V) CRES = = 0.15 µF 2 x (14 V) x (0.2 V) - (0.2)2 Proper charge pump capacitance is required to maintain, and provide for, adequate gate drive during high demand turnON intervals. Use the following formula to determine values for CP1 and CP2: For example, for the above determination of CRES = 0.15 µF: CRES 20 33395 10 < CP1 = CP2 < CRES 10 CP1 and CP2 =(0.0075 µF + 0.015 µF) ÷ 2 = 0.01 µF Thermal Shutdown Function The device has internal temperature sensing circuitry which activates a protective shutdown function should the die reach excessively elevated temperatures. This function effectively limits power dissipation and thus protects the device. Overvoltage Shutdown Function When the supply voltage (VIGN) exceeds the specified overvoltage shutdown level, the part will automatically shut down to protect both internal circuits as well as the load. Operation will resume upon return of VIGN to normal operating levels. Low Voltage Reset Function When the logic supply voltage (VDD) drops below the minimum voltage level or when the part is initially powered up, this function will turn OFF and hold OFF the external MOSFETs until the voltage increases above the minimum voltage level required for normal operation. Control Logic The control logic block controls when the low-side and highside drivers are enabled. The logic implements the Truth Table found in the specification and monitors the M0, M1, PWM, CL, OT, OV, LSE, and HSE terminals. Note that the drivers are enabled 3 µs after the PWM edge. During complimentary chop mode the high-side and low-side drives are alternatively enabled and disabled during the PWM cycle. To prevent shootthrough current, the high-side drive turn-on is delayed by tD1, and the low-side drive turn on is delayed by tD2 (see Figure 2, page 9). MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Note that the drivers are disabled during an overtemperature or overvoltage fault. A flip-flop keeps the drive off until the following PWM cycle. This prevents erratic operation during fault conditions. The current limit circuit also uses a flip-flop for latching the drive off until the following PWM cycle. Freescale Semiconductor, Inc... Note PWM must be toggled after POR, Thermal Limit, or overvoltage faults to re-enable the gate drivers. sense resistor placed in series with the ground return of the three-phase output bridge. When triggered by the comparator, the CL (current limit) bit of the internal error register is set, and the output gate drive pairs (i.e., GDH1 and GDL1, GDH2 and GDL2, GDH3 and GDL3), are controlled such that current will cease flowing through the load (refer to Table 1, Truth Table, page 12). VGDH Overtemperature and Overvoltage Shutdown Circuits The VGDH terminal is used to provide a gate drive signal to a reverse battery protection MOSFET. If reverse battery protection is desired, VIGN would be applied to the source of an external MOSFET, and the drain of the MOSFET would then deliver a "protected" supply voltage (VIGNP) to the three phase array of external MOSFETs as well as the supply voltage to the VIGNP terminal of the IC. Internal monitoring is provided for both over temperature conditions and over voltage conditions. When any of these conditions presents itself to the IC, the corresponding internally set bits of the error register are set, and the output gate drive pairs (i.e., GDH1 and GDL1, GDH2 and GDL2, GDH3 and GDL3), are controlled such that current will cease flowing through the load (refer to Table 1). In a reverse polarity event (e.g., an erroneous installation of the system battery), the VGDH signal will not be supplied to the external protection MOSFET, and the MOSFET will remain off and thus prevent reverse polarity from being applied to the load and the VIGNP supply terminal of the IC. LSE and HSE Input Circuits High-Side Gate Drive Circuits Outputs GDH1, GDH2, and GDH3 provide the elevated drive voltage to the high-side external MOSFETs (HS1, HS2, and HS3; see Figure 3, page 13). These gate drive outputs supply the peak currents required to turn ON and hold ON the highside MOSFETs, as well as turn OFF the MOSFETs. These gate drive circuits are powered from an internal charge pump, and therefore compensate for voltage dropped across the load that is reflected to the source-gate circuits of the high-side MOSFETs. The low-side enable input terminals (LSE1, LSE2, LSE3) and high-side enable input terminals (HSE1, HSE2, HSE3) form the input pairs (HSE1 and LSE1, HSE2 and LSE2, HSE3 and LSE3) which set the logic states of the output gate drive pairs (i.e., GDH1 and GDL1, GDH2 and GDL2, GDH3 and GDL3) in accordance with the logic set forth in the Truth Table (page 12). Typically these inputs are supplied from an MCU or DSP to provide the phasing of the currents applied to a brushless dc motor's stator coils via the output MOSFET pairs. PWM Input The pulse width modulation input provides a single input terminal to accomplish PWM modulation of the output pairs in accordance with the states of the Mode 0 and Mode 1 inputs as set forth in the Truth Table (page 12). Low-Side Gate Drive Circuits Mode Selection Inputs Outputs GDL1, GDL2, and GDL3 provide the drive voltage to the low-side external MOSFETs (LS1, LS2, and LS3; see Figure 3). These gate drive outputs supply the peak currents required to turn ON and hold ON the low-side MOSFETs, as well as turn OFF the MOSFETs. The mode selection inputs (Mode 0 and Mode 1) determine the PWM implementation of the output pairs in accordance with the logic set forth in the Truth Table (page 12). PWM'ing can thus be set to occur either on the high-side MOSFETs or the low-side MOSFETs, or can be set to occur on both the high-side and low-side MOSFETs as "complementary chopping". VDD Fuse The VDD supply of the 33395 IC has an internal fuse, which will blow and set all outputs of the device to OFF, if the VDD voltage exceeds that stated in the maximum rating section of the data sheet. When this fuse blows, the device is permanently disabled. ISENS Inputs Test Terminal This terminal should be grounded or left floating (i.e., do not connect it to the printed circuit board). It is used by the automated test equipment to verify proper operation of the internal overtemperature shut down circuitry. This terminal is susceptible to latch-up and therefore may cause erroneous operation or device failure if connected to external circuitry. The +Isens and -Isens terminals are inputs to the internal current sense comparator. In a typical application, these would receive a a low-pass filtered voltage derived from a current MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33395 11 Freescale Semiconductor, Inc. Table 1. Truth Table The logic state of each output pair, GDLn and GDHn (n = 1, 2, 3), is a function of its corresponding input pair, LSEn and HSEn (n = 1, 2, 3), along with the logic states of the MODEn and PWM inputs and the internally set overtemperature shutdown (OT), overvoltage (OV), and current limit (CL) bits provided in this table. NORMAL OPERATION Freescale Semiconductor, Inc... Switching Modes Internally Set Bits Input Pairs (e.g., LSE2 and HSE2) Output Pairs (e.g., GDL2 and GDH2) MODE1 MODE0 OT OV CL LSEn HSEn GDLn GDHn 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 PWM 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 1 0 0 0 1 0 PWM PWM 0 1 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 PWM 1 0 0 0 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 1 PWM PWM 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 1 0 0 FAULT MODE OPERATION Switching Modes 33395 12 Internally Set Bits Input Pairs (e.g., LSE2 and HSE2) Output Pairs (e.g., GDL2 and GDH2) MODE1 MODE0 OT OV CL LSEn HSEn GDLn GDHn 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 1 1 0 1 0 1 0 0 0 1 1 1 0 0 1 1 0 0 1 0 0 0 0 1 1 0 0 1 0 1 1 0 1 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 0 0 x x x 1 x x x 0 0 x x 1 x x x x 0 0 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 12 V SRC1 GDH1 GDL1 SRC2 GDH2 GDL2 SRC3 GDH3 GDL3 PGND TEST 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 HS2 HS3 LS1 LS2 LS3 CP2L CP1H CP1L LSE1 LSE2 LSE3 HSE1 HSE2 HSE3 MODE0 MODE1 PWM VDD + - TO MOTOR CP2H CPRES VIGN VGDH VIGNP HS1 MCU 5.0 V + AGND +ISENS -ISENS RSENSE Freescale Semiconductor, Inc... + Figure 3. Typical Application Diagram MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33395 13 Freescale Semiconductor, Inc. PACKAGE DIMENSIONS DWB SUFFIX 32-TERMINAL SOICW PLASTIC PACKAGE CASE 1324-02 ISSUE A NOTES: 1. 2. 10.3 3. 4. 7.6 7.4 C 5 Freescale Semiconductor, Inc... 1 B 2.65 2.35 9 5. 30X 32 0.65 6. PIN 1 ID 4 B 9 B 11.1 10.9 CL 7. 8. 9. 16 17 A 5.15 32X 2X 16 TIPS 0.3 SEATING PLANE ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. DATUMS B AND C TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. THIS DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.4 MM PER SIDE. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT LESS THAN 0.07 MM. EXACT SHAPE OF EACH CORNER IS OPTIONAL. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 MM AND 0.3 MM FROM THE LEAD TIP. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. THIS DIMENSION IS DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTER-LEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. A 0.10 A B C A (0.29) A BASE METAL 0.25 0.19 (0.203) 0.25 0.38 0.22 6 0.13 M C A PLATING M SECTION A-A B ROTATED 90 CLOCKWISE 33395 14 R0.08 MIN GAUGE PLANE 0 MIN 0.29 0.13 8 8 0 0.9 0.5 SECTION B-B MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... NOTES MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33395 15 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. 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All other product or service names are the property of their respective owners. © Motorola, Inc. 2004 HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1-800-521-6274 or 480-768-2130 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center 3-20-1 Minami-Azabu. Minato-ku, Tokyo 106-8573, Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 HOME PAGE: http://motorola.com/semiconductors For More Information On This Product, Go to: www.freescale.com MC33395/D