Ordering number : EN4845B Monolithic Digital IC LB1825 Three-Phase Brushless Motor Driver Overview Package Dimensions The LB1825 is a three-phase brushless motor driver IC optimal for LBP polygon mirror and magneto-optical disk spindle motor drive. unit: mm 3147A-DIP28H [LB1825] Functions and Features • • • • • • • • • • • • • • Three-phase full-wave current control drive PLL speed control Internal 24-mode clock divisor switching Phase lock detector output FG/Hall FG selection Current limiter circuit 7 V stabilized power supply output pin Reverse torque braking Crystal oscillator circuit Internal/external reference frequency selection Built-in FG amplifier and FG pulse output Forward/reverse rotation switching Low power supply voltage protection circuit Thermal protection circuit SANYO: DIP28H Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Symbol Maximum supply voltage VCC max Maximum output current IO max Allowable power dissipation Conditions Ratings Unit 30 t < 0.1 s Pd max1 Independent IC Pd max2 With an arbitrarily large heat sink V 2.0 A 3 W 20 W Operating temperature Topr –20 to +80 °C Storage temperature Tstg –55 to +150 °C SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 83097HA (OT)/N3095HA (OT)/91494TH (OT) No. 4845-1/9 LB1825 Allowable Operating Ranges at Ta = 25°C Parameter Symbol Supply voltage Conditions VCC Ratings Unit 10 to 28 V Electrical Characteristics at Ta = 25°C, VCC = 24 V Parameter Current drain Symbol min typ max Unit Braking stopped mode 35 47 mA ICC2 FGOUT1 stopped mode 35 47 mA ICC3 Output saturation voltage Conditions ICC1 External clock, braking stopped mode 28 40 mA Upper transistor (1) VO (sat)1 IO = 1.0 A 1.0 1.6 V Upper transistor (2) VO (sat)2 IO = 1.5 A 1.25 2.1 V Lower transistor (1) VO (sat)1 IO = 1.0 A 0.6 1.0 V Lower transistor (2) VO (sat)2 IO = 1.5 A 0.9 1.6 V 100 µA Output leakage current IO LEAK [Fixed voltage block] Output voltage VREG Output current IREG IREG = 20 mA 6.3 7.0 7.8 20 Load variation ∆VREG IREG = 0 to 20 mA Temperature coefficient αVREG Design target value V mA 0.25 –2.0 V mV/°C [Hall input block] Input bias current IB (HA) 1 Common-mode input range 1.5 4 VCC – 1.8 µA V Input sensitivity DVH 20 mV Input offset voltage VIOH 20 mV [Drive block] Dead zone width VDZ Output idling voltage VID 50 200 mV 6 mV Forward gain GDF+ 0.4 0.5 0.6 Reverse gain GDF– –0.6 –0.5 –0.4 Accelerate command voltage VSTA 6.0 Decelerate command voltage VSTO 6.3 V 0.8 1.5 V Forward limiter voltage VL+ Rf = 1.8 Ω 0.45 0.53 0.61 V Reverse limiter voltage VL– Rf = 1.8 Ω 0.45 0.53 0.61 V 0.4 V [Phase comparator block] Output high level voltage VPDH No external load Output low level voltage VPDL No external load Output source current IPD+ 0.4 mA Output sink current IPD– 2.5 mA VREG – 0.4 V [Error amplifier block] Input bias current Input offset voltage IB (ER) VIO (ER) –10 1 µA +10 mV Output high level voltage VERH No external load Output low level voltage VERL No external load 1.0 V ILD = 10 mA 0.4 V 5.5 V [Lock detector block] Output saturation voltage VLD (sat) [FG amplifier block] Input bias current Input offset voltage IB (FG) VIO (FG) –10 Output high level voltage VFGH No external load Output low level voltage VFGL No external load 1 µA +10 mV 5.0 V 2.0 V [FG Schmitt block] Input operating level VIS FGOUT1 generation signal 160 mVp-p Input hysteresis (high → low) VSHL External clock, braking stopped mode 0 Input hysteresis (low → high) VSLH External clock, braking stopped mode 36 Hysteresis VFGS Output saturation voltage VFG2 (sat) 18 IFG2 = 10 mA 36 mV mV 60 mV 0.4 V Continued on next page. No. 4845-2/9 LB1825 Continued from preceding page. Parameter Symbol Conditions min typ max Unit [FG switching setting] Single Hall FG operating level VFGIH FGIN pin voltage VREG – 0.1 VREG V Triple Hall FG operating level VFGIL FGIN pin voltage 0 0.1 V [Stop mode setting] FGOUT1 low level voltage VFG1L FGOUT1 low level current IFG1L 0.4 V 0.6 2.4 mA 0.58 0.65 V 3.0 V 90 mV 1 12 MHz 30 5000 FGOUT1 pin voltage = 0 V [Current limiter] Reference voltage External supply range VCS R = 47 kΩ VCS (EX) 0.7 VCSO R = 47 kΩ, Rf = 1.8 Ω Internal oscillator frequency fOSC Crystal oscillator mode External input frequency fREF External clock mode Offset voltage 0.51 25 50 [Signal block] Hz Low level pin voltage VOSCL 4.0 4.5 5.0 V High level pin current IOSCH 0.3 0.5 0.75 mA [Divisor switching] Input high level voltage VN1 to 3H 4.2 VREG V Input middle level voltage VN1 to 3M 2.1 2.9 V Input low level voltage VN1 to 3L 0 0.8 V [F/R switching] Input high level voltage VFRH 2.4 VREG V Input low level voltage VFRL 0 1.5 V High level input current IFRH 0.22 mA F/R pin voltage = VREG [S/B switching] Input high level voltage VSBH Input low level voltage VSBL Hysteresis (high → low) DVSB 2.4 0.15 0.25 VREG V 1.5 V 0.35 V [Stop detection] Count setting SCT1 FG mode SCT2 Triple Hall FG mode 8 SCT3 Single Hall FG mode 2 32 [Undervoltage protection] Operating voltage Hysteresis VSD 8.4 8.8 9.2 V DVSD 0.2 0.4 0.6 V [Thermal protection] Operating temperature TSD Design target value Recovery temperature TSDR Design target value LD pin ILD (LEAK) Pin voltage = 30 V 10 µA FGOUT2 pin IFG2 (LEAK) Pin voltage = 30 V 10 µA 30 Ω 150 180 °C 140 °C [Pin leakage currents] [GND pin-heat sink] Resistance Design target value. No. 4845-3/9 LB1825 Pin Assignment Pin Functions Pin No. Symbol 1 FC Function 2 to 7 IN1+ to IN3+, IN1– to IN3– 8 to 10 OUT1 to OUT3 11 Rf 12 VREG 13 LD Notes Frequency characteristics correction A capacitor must be inserted between pin 1 and ground. Hall element inputs Taken as high when IN+ > IN–, and as low otherwise. Outputs Output current detector A capacitor must be inserted between pin 11 and ground. Stabilized power supply output On when the phase is locked. This pin is an open-collector output. Phase lock detector output Power supply 14 VCC 15 ERROUT 16 ERRIN 17 PD Phase comparator output 18 VCS Current limiter reference voltage generation 19 GND Ground 20 FGIN FG amplifier input Also functions as the Hall FG switching pin. 21 FGOUT1 FG amplifier output The LB1825 goes to stop mode when pin 21 is set low. 22 FGOUT2 FG/Hall FG output This pin is an open-collector output. 23 S/B 24 to 26 N1 to N3 27 OSC Crystal oscillator/external clock input 28 F/R Forward/reverse switching Error amplifier output Error amplifier input Brake command input Braking is applied when pin 23 is set high. Reference frequency divisor switching The clock divisor is set by the states of pins 24 to 26. Clock Divisor Switching Pin N1 Pin N2 Divisor (1)*I Pin N3 Divisor (2)*I L L *II L 5 L M 128 M 4 L H 256 H 3 M L 512 M M 1024 M H 2048 H L 4096 H M 8192 H H 16384 Note: I. Total divisor = (divisor (1) × divisor (2)) PLL servo frequency = (crystal oscillator frequency)/(total divisor) II. External clock mode The PLL servo frequency = external input frequency No. 4845-4/9 LB1825 Figure 1 Pin Circuit for Internal Clock Mode Table 1: External Component Values (reference values) Crystal (MHz) C1 (pF) C2 (pF) R (kΩ) 3 to 4 39 82 0.82 4 to 5 39 82 1.0 5 to 7 39 47 1.5 7 to 10 39 27 2.0 Use a crystal that has a ratio of at least 1:5 between the fundamental f0 impedance and the 3f0 impedance. Figure 2 Pin Circuit for External Clock Mode F/R Switching and Phase Selection F/R L H IN1 IN2 IN3 OUT1 OUT2 H H L M H OUT3 L H L L H M L H L H H L M L L H M L H L H H L M H L H L L H M H H L M L H H L L L M H H L H L H M L L H M H L L H H H M L L H L H L M Columns OUT1 to OUT3 H: Source L: Sink No. 4845-5/9 LB1825 Equivalent Circuit Block Diagram No. 4845-6/9 LB1825 Sample Application Circuit (Polygon Mirror Motor) No. 4845-7/9 LB1825 Sample Application Circuit (Optical Disk Spindle Motor) Usage Notes 1. Position detector circuit (Hall element input circuit) The position detection circuit consists of a differential amplifier, and will operate if a differential input of 40 mVp-p (minimum) is provided. However, an input of 100 mVp-p is desirable from the standpoint of noise and other problems. The input DC level must be within the common mode input voltage range (1.5 to (VCC – 1.8) V). 2. Current limiter circuit The output current limiter operates by holding the sink side output transistor in an unsaturated state. The current limit value can be calculated from the following formula. I = VCS/Rf Where: VCS = 0.58 V typical, Rf = The value of the resistor between pin 11 and ground. 3. FG input The following three methods can be used to input the speed signal FG from the motor. • The signal can be input to FGIN through an amplifier. (FG mode) • The Hall input IN1 can be used as the FG input. (single Hall FG mode) This is set up by connecting FGIN to VREG. • The composite signal from the IN1, IN2 and IN3 Hall inputs can be used as the FG input. (triple Hall FG mode) This is set up by connecting FGIN to ground. No. 4845-8/9 LB1825 4. Reference signal input circuit • Internal clock mode (crystal oscillator) The values of the external components associated with the crystal oscillator must be set up according to the frequency of the oscillator. (See Table 1.) To avoid trouble with the oscillator circuit, confirm the component values used with the oscillator’s manufacturer. • External clock mode Use the external circuit shown in Figure 2 to input the clock signal when controlling the motor speed using a reference signal with the same frequency as FG. 5. Start/stop When driving motors such as polygon mirror motors, the motor is normally stopped by turning off motor drive and putting the motor in the free-running state. For this type of motor, set the S/B pin low and attach an external transistor at FGOUT1 as shown in the Sample Application Circuit (Optical Disk Spindle Motor) figure to start and stop the drive. (Motor drive is turned off when FGOUT1 is low.) 6. Start/brake When driving motors such as optical disk spindle motors, stopping is performed by applying some form of braking. In these applications it is necessary for the motor to decelerate briefly and come to a complete stop. See the Sample Application Circuit (Optical Disk Spindle Motor) figure for a sample circuit for this case. (The difference between this circuit and the circuit shown in the Sample Application Circuit (Optical Disk Spindle Motor) figure is the addition of the capacitor C5 to the S/B pin start/brake circuit.) Braking Operation This braking circuit applies full torque reverse rotation braking (in the current limited state) directly after the S/B pin is set low while the motor is turning. After that, the reverse torque is gradually decreased (according to the time constant determined by R4 and C5) at the points where the speed falls below the values listed below. This operation brings the disk to a full stop. f3H = fFG/32 (FG mode) f3H = fFG/8 (Triple Hall FG mode) f3H = fFG/2 (Single Hall FG mode) f3H: Triple Hall input composite frequency. fFG: The FG frequency when locked Depending on the size of the disk and the motor torque the following adjustments may be required to improve the disk stopping characteristics. 1. Increase the time constant if the motor continues to rotate in the forward direction after the braking torque has gone to zero. 2. Decrease the time constant if the motor is observed to rotate in the reverse direction due to the braking operation. 3. A value of about 51 kΩ is recommended for R4. In particular, it should be under 100 kΩ. ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of August, 1997. Specifications and information herein are subject to change without notice. No. 4845-9/9