MC54/74F175 QUAD D FLIP-FLOP The MC54/74F175 is a high-speed quad D flip-flop. The device is useful for general flip-flop requirements where both true and complementary outputs are required and clock and clear inputs are common to all flip-flops. The information on the D inputs is stored during the LOW-to-HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D inputs when LOW. • Four Edge-triggered D-type Inputs • Buffered Positive Edge-triggered Common Clock • Buffered Asynchronous Common Reset • True and Complementary Outputs • ESD > 4000 Volts QUAD D FLIP-FLOP FAST SCHOTTKY TTL J SUFFIX CERAMIC CASE 620-09 16 1 CONNECTION DIAGRAM DIP (TOP VIEW) VCC Q3 Q3 D3 D2 Q2 Q2 CP 16 15 14 13 12 11 10 9 N SUFFIX PLASTIC CASE 648-08 16 1 1 2 MR Q0 3 Q0 4 D0 5 D1 6 7 Q1 Q1 D SUFFIX SOIC CASE 751B-03 8 GND 16 1 ORDERING INFORMATION FUNCTION TABLE Inputs Outputs @ tn, MR = H @ tn + 1 Dn Qn Qn L L H H H L MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC LOGIC SYMBOL tn = Bit time before clock positive-going transition tn + 1 = Bit time after clock positive-going transition H = HIGH Voltage Level L = LOW Voltage Level 3 2 6 7 11 10 14 15 1 9 MR Q0 Q0 Q1 Q1 Q2 CP Q2 Q3 Q3 D0 4 D1 5 D2 12 D3 13 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 4-89 MC54/74F175 LOGIC DIAGRAM MR CP D3 D2 D CP D1 Q D Q CP Q CD CD Q3 Q3 Q D0 D Q D CP Q CD Q2 Q2 Q CP Q CD Q1 Q1 Q0 Q0 NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. FUNCTIONAL DESCRIPTION Q outputs to follow. A LOW input on the Master Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock or Data inputs. The F175 is useful for general logic applications where a common Master Reset and Clock are acceptable. The F175 consists of four edge-triggered D flop-flops with individual D inputs and Q and Q outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their individual D inputs, one setup time before, on the LOW-to-HIGH clock (CP) transition, causing individual Q and GUARANTEED OPERATING RANGES Symbol Parameter VCC Supply Voltage TA Operating Ambient Temperature Range Min Typ Max Unit 54, 74 4.5 5.0 5.5 V 54 –55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 –1.0 mA IOL Output Current — Low 54, 74 20 mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIH Input HIGH Current Min Typ Max 2.0 54, 74 2.5 74 2.7 IIL Input LOW Current IOS Output Short Circuit Current (Note 2) ICC Power Supply Current Guaranteed Input HIGH Voltage 0.8 V Guaranteed Input LOW Voltage –1.2 V IIN = –18 mA VCC = MIN V IOH = – 1.0 mA VCC = 4.50 V 3.4 –60 22.5 Test Conditions V 3.4 0.35 Unit V IOH = – 1.0 mA VCC = 4.75 V 0.5 V IOL = 20 mA VCC = MIN 20 µA VIN = 2.7 V VCC = MAX 100 µA VIN = 7.0 V VCC = MAX –0.6 mA VIN = 0.5 V VCC = MAX –150 mA VOUT = 0 V VCC = MAX 34 mA Dn = MR = 4.5 V CP = VCC = MAX NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under guaranteed operating ranges. 2. Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 4-90 MC54/74F175 AC CHARACTERISTICS Symbol Parameter 54/74F 54F 74F TA = +25°C TA = –55°C to +125°C TA = 0°C to +70°C VCC = +5.0 V VCC = 5.0 V ± 10% VCC = 5.0 V ± 10% CL = 50 pF CL = 50 pF CL = 50 pF Min Typ Max Min Max 100 Min Max 100 Unit fmax Maximum Clock Frequency 100 140 MHz tPLH Propagation Delay 3.5 5.0 6.5 3.5 8.5 3.5 7.5 tPHL CP to Qn or Qn 4.0 6.5 8.5 4.0 10.5 4.0 9.5 tPHL Propagation Delay 4.5 9.0 11.5 4.5 15 4.5 13 ns 4.0 6.5 8.5 4.0 10 4.0 9.0 ns ns MR to Qn tPLH Propagation Delay MR to Qn AC OPERATING REQUIREMENTS Symbol Parameter Min 54/74F 54F 74F TA = +25°C TA = –55°C to +125°C TA = 0°C to +70°C VCC = +5.0 V VCC = 5.0 V ± 10% VCC = 5.0 V ± 10% Typ Max Min Max Min ts(H) Setup Time, HIGH or LOW 3.0 3.0 3.0 ts(L) Dn to CP 3.0 3.0 3.0 th(H) Hold Time, HIGH or LOW 1.0 1.0 1.0 th(L) Dn to CP 1.0 1.0 1.0 tw(H) CP Pulse Width, HIGH 4.0 4.0 4.0 5.0 5.0 5.0 tw(L) or LOW Max Unit ns ns tw(L) MR Pulse Width, LOW 5.0 5.0 5.0 ns trec Recovery Time, MR to CP 5.0 5.0 5.0 ns FAST AND LS TTL DATA 4-91