SN54/74LS73A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54LS / 74LS73A offers individual J, K, clear, and clock inputs. These dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum set-up times are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse. DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY LOGIC DIAGRAM (Each Flip-Flop) J SUFFIX CERAMIC CASE 632-08 14 Q 13 (8) 1 Q 12 (9) N SUFFIX PLASTIC CASE 646-06 CLEAR 2 (6) K 3 (10) 14 J 14 (7) 1 1 (15) CLOCK (CP) D SUFFIX SOIC CASE 751A-02 14 1 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD MODE SELECT — TRUTH TABLE INPUTS Ceramic Plastic SOIC OUTPUTS OPERATING MODE Reset (Clear) Toggle Load “0” (Reset) Load “1” (Set) Hold CD J K Q Q L H H H H X h l h l X h h l l L q L H q H q H L q H, h = HIGH Voltage Level L, I = LOW Voltage Level X = Don’t Care l, h (q) = Lower case letters indicate the state of the referenced input (or output) one set-up time l, h (q) = prior to the HIGH to LOW clock transition. LOGIC SYMBOL 14 J Q 1 CP 3 K C Q D 12 13 5-68 9 K C Q D 8 J 5 CP 10 2 6 VCC = PIN 4 GND = PIN 11 FAST AND LS TTL DATA Q 7 SN54/74LS73A GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 74 4.5 4.75 5.0 5.0 5.5 5.25 V TA Operating Ambient Temperature Range 54 74 – 55 0 25 25 125 70 °C IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 74 4.0 8.0 mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIH Min Parameter Typ Max 2.0 54 0.7 74 0.8 – 0.65 – 1.5 Unit Test Conditions V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN, IIN = – 18 mA 54 2.5 3.5 V 74 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table 54, 74 0.25 0.4 V IOL = 4.0 mA 74 0.35 0.5 V IOL = 8.0 mA J, K Clear Clock 20 60 80 µA VCC = MAX, VIN = 2.7 V J, K Clear Clock 0.1 0.3 0.4 mA VCC = MAX, VIN = 7.0 V – 0.4 – 0.8 mA VCC = MAX, VIN = 0.4 V –100 mA VCC = MAX 6.0 mA VCC = MAX Max Unit Input HIGH Current IIL Input LOW Current IOS Short Circuit Current (Note 1) ICC Power Supply Current J, K Clear, Clock – 20 Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits Symbol Parameter fMAX Maximum Clock Frequency tPLH tPHL Propagation Delay, Clock to Output Min Typ 30 45 15 MHz 20 Test Conditions Figure 1 ns Figure 1 15 20 ns Max Unit VCC = 5.0 V CL = 15 pF AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol Parameter Min Typ Test Conditions tW Clock Pulse Width High 20 ns Figure 1 tW Clear Pulse Width 25 ns Figure 2 ts Setup Time 20 ns th Hold Time VCC = 5.0 V Figure 1 0 FAST AND LS TTL DATA 5-69 ns SN54/74LS73A AC WAVEFORMS J or K * 1.3 V th(L) = 0 ts(L) CP th(H) = 0 ts(H) tW(L) 1.3 V 1.3 V 1.3 V tW(H) tPHL Q 1 fMAX tPLH 1.3 V 1.3 V tPHL tPLH 1.3 V Q 1.3 V *The shaded areas indicate when the input is permitted to change for predictable output performance. Figure 1. Clock to Output Delays, Data Set-Up and Hold Times, Clock Pulse Width tW SET 1.3 V 1.3 V tW CLEAR Q 1.3 V tPLH tPHL 1.3 V 1.3 V tPHL Q 1.3 V tPLH 1.3 V 1.3 V Figure 2. Set and Clear to Output Delays, Set and Clear Pulse Widths FAST AND LS TTL DATA 5-70