MOTOROLA Order this document by MCM69C232/D SEMICONDUCTOR TECHNICAL DATA MCM69C232 Advance Information 4K x 64 CAM The MCM69C232 is a flexible content–addressable memory (CAM) that can contain 4096 entries of 64 bits each. The widths of the match field and the output field are programmable, and the match time is designed to be 160 ns. As a result, the MCM69C232 is well suited for datacom applications such as Virtual Path Identifier/Virtual Circuit Identifier (VPI/VCI) translation in ATM switches up to OC12 (622 Mbps) data rates and Media Access Control (MAC) address lookup in Ethernet/Fast Ethernet bridges. The match duty cycle of the MCM69C232 is user defined, with a trade–off between the time between matches and the number of new entries added to the CAM per second. • • • • • • • • • • • • • TQ PACKAGE TQFP CASE 983A–01 4096 Entries 160 ns Match Time Mask Register to “Don’t Care” Selected Bits Depth Expansion by Cascading Multiple Devices 50 MHz Maximum Clock Rate Programmable Match and Output Field Widths Concurrent Matching of Virtual Path Circuits and Virtual Connection Circuits in ATM Mode Separate Ports for Control and Match Operations 200 ns Insertion Time if One of Twelve Entry Queue Locations is Empty 12 ms Initialization Time After Fast Insertion (at Power–Up Only) Single 3.3 V ± 5% Supply 100 Pin TQFP Package IEEE Standard 1149.1 Test Port (JTAG) Related Products — MCM69D536, MCM69D618 (Dual I/O, Dual Address RAMs) — MCM67Q709A, MCM67Q909 (Separate I/O RAMs) — MCM69C432 (CAM) CONTROL PORT MATCH PORT 12 x 64 ENTRY QUEUE MQ31 – MQ0 A2 – A0 DQ15 – DQ0 SEL STATUS/ CONTROL LOGIC 4K x 64 CAM TABLE WE IRQ DTACK RESET K G LH/SM LL INPUT REG MC MS VPC This document contains information on a new product. Specifications and information herein are subject to change without notice. REV 3 1/15/98 Motorola, Inc. 1998 MOTOROLA FAST SRAM MCM69C232 1 MQ10 MQ11 VSS VDD MQ12 MQ13 MQ14 MQ15 LL VDD VSS LH/SM MQ16 MQ17 MQ18 MQ19 VDD VSS MQ20 MQ21 PIN ASSIGNMENT 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MQ22 MQ23 VSS VDD MQ24 MQ25 MQ26 MQ27 VSS VDD MQ28 MQ29 MQ30 MQ31 VSS VDD MC VPC MS G VSS VDD DTACK IRQ RESET TDO VDD VSS TCK TMS DQ5 DQ4 VDD VSS DQ3 DQ2 DQ1 DQ0 K VSS VDD A2 A1 A0 WE SEL VDD VDD TRST TDI MQ9 MQ8 VSS VDD MQ7 MQ6 MQ5 MQ4 VSS VDD MQ3 MQ2 MQ1 MQ0 VSS VDD DQ15 DQ14 DQ13 DQ12 VSS VDD DQ11 DQ10 DQ9 DQ8 VDD VSS DQ7 DQ6 MCM69C232 2 MOTOROLA FAST SRAM PIN DESCRIPTIONS Pin Locations Symbol Type 42 – 44 A2 – A0 Input 58 DTACK Output 17 – 20, 23 – 26, 29 – 32, 35 – 38 DQ15 – DQ0 I/O Description 3–bit control port address bus. Control port data transfer acknowledge (Open Drain). 16–bit bidirectional control port data bus. 61 G Input 57 IRQ Output Asynchronous Output Enable control of MQ31 – MQ0. 39 K Input Interface Clock, max frequency of 50 MHz. 89 LH/SM Input Latch High/Start Match. Initiates match sequence on match data present on MQ31 – MQ0. Latch Low. Latches low order bits if match width is > 32 bits. Control port interrupt (Open Drain). 92 LL Input 64 MC Output Match Complete (Open Drain). 62 MS Output Match Successful (Open Drain). 67 – 70, 73 – 76, 79 – 82, 85 – 88, 93 – 96, 99, 100, 1, 2, 5 – 8, 11 – 14 MQ31 – MQ0 I/O 56 RESET Input Resets chip to a known state. 46 SEL Input Control port chip select, active low. 52 TCK Input Test Clock, part of JTAG interface. 50 TDI Input Test Data In, part of JTAG interface. 55 TDO Output 51 TMS Input Test Mode Select, part of JTAG interface. 49 TRST Input TAP Reset part of JTAG interface. 63 VPC Output 32–bit common I/O CAM data. Used for input of match RAM and data RAM values. Test Data Out, part of JTAG interface. Virtual Path Circuit. Used in ATM mode to indicate a virtual path circuit match has occurred (Open Drain). 45 WE Input Control port Write Enable. 4, 10, 16, 22, 27, 33, 41, 47, 48, 54, 59, 65, 71, 77, 84, 91, 97 VDD Supply Power Supply: 3.3 V ± 5%. 3, 9, 15, 21, 28, 34, 40, 53, 60, 66, 72, 78, 83, 90, 98 VSS Supply Ground. MOTOROLA FAST SRAM MCM69C232 3 ABSOLUTE MAXIMUM RATINGS (See Note 1) Rating Symbol Value Unit VDD 4.6 V Voltage Relative to VSS (see Note 2) Vin – 0.5 to VDD + 0.5 V V Output Current per Pin Iout ± 20 mA Package Power Dissipation (see Note 3) PD — W Tbias – 10 to 85 °C TA 0 to 70 °C Tstg – 55 to 125 °C Supply Voltage (see Note 2) Temperature Under Bias (see Note 3) Operating Temperature (see Note 4) Storage Temperature This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit. NOTES: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. 2. All voltages are referenced to VSS. 3. Power dissipation capability will be dependent upon package characteristics and use environment. See Package Thermal Characteristics. 4. Consult Junction to Ambient Thermal Characteristics table for details and conditions. DC OPERATING CONDITIONS AND CHARACTERISTICS (VDD = 3.3 V ± 5%, TJ = 20 to 120°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS = 0 V) Symbol Min Typ Max Unit VDD 3.1 3.3 3.5 V Operating Temperature (Junction) TJ 20 — 120 °C Input Low Voltage VIL – 0.5* 0 0.8 V VIH 2.0 3 5.5 V Symbol Min Max Unit Active Power Supply Current @ 20°C TJ IDD1 — 575 mA Active Power Supply Current @ 120°C TJ IDD2 — 460 mA Parameter Power Supply Voltage Input High Voltage * VIL (min) = – 3.0 V ac (pulse width v 20 ns). DC CHARACTERISTICS AND SUPPLY CURRENTS Parameter v Vin v VDD) v Vin v VDD) Ilkg(I) — TBD µA Ilkg(O) — TBD µA Output Low Voltage (IOL = 8 mA) VOL — 0.4 V Output High Voltage (IOH = – 4 mA) VOH 2.4 — V Symbol Max Unit Thermal Resistance Junction to Ambient (200 lfpm, 4 Layer Board) (Note 2) RθJA 27.1 °C/W Thermal Resistance Junction to Board (Bottom) (Note 3) RθJB 17 °C/W Thermal Resistance Junction to Case (Top) (Note 4) RθJC 9 °C/W Input Leakage Current (0 V Output Leakage Current (0 V PACKAGE THERMAL CHARACTERISTICS Rating NOTES: 1. RAM junction temperature is a function of on–chip power dissipation, package thermal impedance, mounting site temperature, and mounting site thermal impedance. 2. Per SEMI G38–87. 3. Indicates the average thermal impedance between the die and the mounting surface. 4. Indicates the average thermal impedance between the die and the case top surface. Measured via the cold plate method (MIL SPEC–883 Method 1012.1). MCM69C232 4 MOTOROLA FAST SRAM CAPACITANCE (Periodically Sampled Rather Than 100% Tested) Symbol Min Max Unit Input Capacitance Parameter Cin — 5 pF I/O Capacitance CI/O — 8 pF JUNCTION TO AMBIENT THERMAL CHARACTERISTICS Board Air (LFPM) θJA (°C/W) Maximum Ambient Temperature (°C) 1 Layer 0 40.1 55.8 1 Layer 200 34.7 64.4 1 Layer 400 32.1 68.7 4 Layer 0 30.5 71.1 4 Layer 200 27.1 76.6 4 Layer 400 25.6 79.0 AC OPERATING CONDITIONS AND CHARACTERISTICS (VDD = 3.3 V ± 5%, TJ = 20 to 120°C, Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . . Figure 1 Unless Otherwise Noted CONTROL PORT AND MATCH PORT TIMINGS (Voltages Referenced to VSS = 0 V, Max’s are tKHKH Dependent and Listed Values are for tKHKH = 20 ns) Parameter Symbol Min Max Unit tAVSL 0 — ns tDTLAX 0 — ns tDVSL 0 — ns DTACK Low to Data Invalid tDTLDX 0 — ns Output Valid to DTACK Low tQVDTL 2 — ns WE Valid to Select Low tWVSL 0 — ns DTACK Low to WE High tDTLWH 0 — ns WE High to Output Active tWHQX TBD — ns Select Low to DTACK Low* tSLDTL 10 — ns Select High to DTACK High tSHDTH 10 30 ns tDTLIL TBD — ns tILIH 20 — ns DTACK Low to Select High tDTLSH 0 — ns DTACK High to Select Low tDTHSL 0 — ns Address Valid to Output Valid tAVQV — 8 ns Select High to Output Three–State tSHQZ — 8 ns CONTROL PORT TIMING Address Valid to SEL Low DTACK Low to Address Invalid Data Valid to Select Low DTACK Low to IRQ Low IRQ Low to IRQ High * DTACK is delayed when a write is attempted during certain operations. See Functional Description. MOTOROLA FAST SRAM MCM69C232 5 CONTROL PORT AND MATCH PORT TIMINGS (Voltages Referenced to VSS = 0 V, Max’s are tKHKH Dependent and Listed Values are for tKHKH = 20 ns) Parameter Symbol Min Max Unit Clock Cycle Time tKHKH 20 250 ns Clock High Time tKHKL 8 242 ns Clock Low Time tKLKH 8 242 ns Clock High to LHSM or LL Low tKHLL — 7 ns Clock High to LHSM or LL High tKHLH — 7 ns MQ Input Data Setup Time to Clock High tMQVKH 8 — ns Clock High to Match Data Hold Time tKHMQX 2 — ns Clock High to MQ Valid tKHMQV — 12 ns Clock High to MC High tKHMCH — 5 ns Clock High to MC Low tKHMCL — 5 ns Clock High to MS Low tKHMSL — 12 ns Clock High to MS High tKHMSH — 5 ns Clock High to VPC Low tKHVPL — 12 ns Clock High to VPC High tKHVPH — 5 ns G Low to MQ Active tGLMQX 3.8 — ns G High to MQ High–Z tGHMQZ — 4 ns tSMSM 10 — cycles MATCH PORT TIMING LH/SM Low to LH/SM Low RL = 50 Ω OUTPUT Z0 = 50 Ω VL = 1.5 V Figure 1. AC Test Loads 3.3 V RH MCM69C232 OUTPUT PIN FANOUT TO LOAD DEVICES NOTES: 1. For IRQ, DTACK, MS, MC, and VPC, RH = 200 Ω . 2. If multiple MCM69C232s are used, RH should be placed as close to the load devices as possible. Figure 2. Pullup for Open Drain Outputs MCM69C232 6 MOTOROLA FAST SRAM FUNCTIONAL DESCRIPTION The MCM69C232 is a flexible content–addressable memory (CAM) that can contain 4096 entries of 64 bits each. The widths of the match field and the output field are programmable, and the match time is designed to be 160 ns. As a result, the MCM69C232 is well suited for datacom applications such as Virtual Path Identifier/Virtual Circuit Identifier (VPI/VCI) translation in ATM switches up to OC12 (622 Mbps) data rates and Media Access Control (MAC) address lookup in Ethernet/Fast Ethernet bridges. The match duty cycle of the MCM69C232 is determined by the user, with a trade–off between the match cycle time and the number of entries added to/deleted from the CAM. With the minimum required 40 ns of idle time between matches, a typical value of 2440 insertions or deletions per second can be made. See Figure 3 for a graph of the relationship between insertion/deletion pairs and match cycle time. In its basic operating mode, the MCM69C232 reads a data input word and compares it to all the entries in its CAM table. Whether a match is found or not, the MC pin is asserted after the comparisons have been made. If a match is found, the MS pin is asserted, and the data associated with the matching entry is output on the MQ bus. If no match is found, the MQ bus remains in a high impedance state to facilitate depth expansion via the cascading of multiple CAMs. Before the basic operating mode can be entered, however, several start–up functions must be performed. First, the output width and match width must be designated by setting the global–mask register. Second, a choice must be made between buffered entry mode and fast entry mode. Next, the match/output data pairs must be loaded into the table. Depending on the entry mode of choice, the table may have to be initialized. Optionally, the “almost full” point may be set to provide warning of impending table overflow. The input bits to be compared are defined by the global– mask register. The mask bits that are 0 correspond to the bits that are used in the match operation.Typically, the bits that are used in matching are the high order bits in the 64 bit CAM table entries, and the bits that are used as outputs are the low order bits. While any of the bits can be defined as match bits, the low order 32 bits of an entry are always driven on the MQ bus as output data. The choice of entry mode is a trade–off between speed of entry and latency before matching operations can begin. In a typical application, the fast entry mode will be used to load the initial values into the CAM table. Subsequently, the initialize–table operation, which takes 12 ms, must be executed to establish the required linkages and relationships among the entries. After match operations have begun, the buffered entry mode should be used to enter new values dynamically; even one addition in fast entry mode will disable matching until the table is reinitialized. Table insertions using the buffered entry mode and the fast entry mode actually take the same amount of time unless the entry queue is full. The capacity of the queue is 12 entries. MOTOROLA FAST SRAM After the entry mode choice is made, the table can be loaded. Each 64 bit entry is constructed by writing a 16 bit value to each of the four I/O registers in the MCM69C232. The insertion can then be processed. After all the start–up entries have been loaded into the CAM table, the initialization operation is run if required. Normal matching operations can then begin. A delete operation is provided to remove stale data from the CAM table. Several error codes are defined in the details of the instruction set. When an error occurs, its corresponding code is written into the error register and the error bit in the flag register is set. The error bit is cleared and the error register is set to FFFF16 by the next write to the operation register. PROGRAMMING MODEL Three types of registers are accessible through the MCM69C232’s control port: I/O registers, an operation register, and result/condition code registers. Each register is sixteen bits in length. REGISTER NAME ADDRESS OFFSET BIT NUMBER 15 0 I/O REGISTER 0 0 I/O REGISTER 1 1 I/O REGISTER 2 2 I/O REGISTER 3 3 OPERATION REGISTER 4 FLAG REGISTER 5 ERROR CODE REGISTER 6 INTERRUPT REGISTER 7 FLAG BIT DEFINITIONS Bit 0: 1 = At least one Interrupt enabled, 0 = No interrupts generated Bit 1: 1 = Last control port match successful, 0 = Last match unsuccessful Bit 2: 1 = Table initialized, 0 = Table not initialized Bit 3: 1 = Buffered entry mode, 0 = Fast entry mode Bit 4: 1 = Entry queue empty, 0 = Entry queue not empty Bit 5: 1 = Entry queue full, 0 = Entry queue not full Bit 6: 1 = CAM table full, 0 = CAM table not full Bit 7: 1 = Error condition set, 0 = No error Bit 8: 1 = Table almost full, 0 = Table not almost full Bit 9: 1 = ATM mode, 0 = Standard mode Bit 10: 1 = Last operation complete, 0 = Not yet complete MCM69C232 7 INTERRUPT BIT DEFINITIONS Bit 0: Bit 1: Bit 2: Bit 3: Bit 4: Bit 5: Bit 6: Bit 7: INSTRUCTION SET DETAILS 1 = Enable interrupt on insert with full entry queue 1 = Enable interrupt on insert with full table 1 = Enable interrupt on completion of CHECK–FOR–VALUE instruction 1 = Enable interrupt on completion of INITIALIZE–TABLE instruction 1 = Enable interrupt on failed attempt to enter fast entry mode 1 = Enable interrupt on CAM table reaching almost–full point 1 = Enable interrupt on fast read with non–empty queue 1 = Enable interrupt on illegal instruction The MCM69C232 is prepared for match operations by writing to data and instruction registers via the control port. In the general case, required data is loaded into I/O registers 0 – 3, then an instruction is issued by writing an operation code to the instruction register. As a result of running an instruction, the CAM table can be modified, bit(s) can be set in the flag register, error codes can be returned in the error code register, and an interrupt can be generated if enabled. For a particular condition to generate an interrupt, the interrupt register bit specific to that condition must be set. The user should verify that the operation–complete bit of the flag register is set before executing the next instruction, if the instruction just executed is one that modifies I/O registers. Table 1. MCM69C232 Operation Summary Operation Description OP Code (Base 16) INSERT VALUE Loads a new entry into the CAM table 0000 or 000F DELETE VALUE Removes an entry from the CAM table 0001 or 000E CHECK FOR VALUE Runs a match cycle via the control port 0006 INITIALIZE TABLE Prepares CAM table for matching 000B FAST ENTRY MODE Selects entry mode suited for initial CAM table load 0004 BUFFERED ENTRY MODE Selects entry mode suited for simultaneous loading and matching 0005 SET ATM MODE Enter mode that provides concurrent VPC/VCC search 0008 RETURN ENTRY COUNT Determines number of entries in CAM 0003 SET GLOBAL MASK REGISTER Determines match bits to be checked in a match operation SET ALMOST–FULL POINT Defines CAM almost full condition 0007 SET FAST–READ REGISTER Defines table entry that is output by the fast read operation 0009 FAST READ Outputs one CAM table entry 000A INSERT VALUE This instruction is used to load a new match/output value into the CAM. The contents of I/O registers 0 – 3 are concatenated, with bit 15 of register 3 as the most significant bit, and bit 0 of register 0 as the least significant bit. If the MCM69C232 is running in buffered entry mode, the resulting 64 bit value is written to the first available location in the entry queue, and is immediately available for matching. If a buffered insert–value instruction is attempted when the entry queue is full (indicated by bit 5 of the flag register = 1), no value is written, an error code of FFF816 is returned in the error code register, and the error–condition flag (bit 7) is set in the flag register. An interrupt is generated, if enabled by bit 0 of the interrupt register being set. If the MCM69C232 is running in fast entry mode, the concatenated 64 bit value is written directly to the CAM array. If an insert–value instruction is attempted when in fast entry mode and the table is full, no value is written, an error code of FFF916 is returned in the error code register, and the error– condition flag (bit 7) is set in the flag register. (The table–full MCM69C232 8 0002 or 000D condition is indicated by bit 6 of the flag register being set.) An interrupt is generated, if enabled by bit 1 of the interrupt register being set. Only one entry is allowed for a given match pattern. If an entry is made in the table that duplicates an existing match pattern, it will overwrite the entry already in the CAM table, if the CAM is in buffered entry mode. The user must ensure that no entries with the same match pattern are inserted in fast entry mode. DELETE VALUE This instruction is used to remove a match/output value from the CAM. The contents of I/O registers 0 – 3 are concatenated, with bit 15 of register 3 as the most significant bit, and bit 0 of register 0 as the least significant bit. The bits that have a 0 in the corresponding bit of the global–mask register are used to find a matching entry in the CAM table. If such an entry is found, it is invalidated. Note that any bit that is not a match bit as defined by the mask register is ignored for this operation. The operation of the MCM69C232 guarantees that no more than one matching entry can exist in the table, MOTOROLA FAST SRAM unless they were accidently loaded using fast entry mode. This must be avoided by the user, as the results of subsequent matches and deletes will be undefined. Example: I/O Register 0 = I/O Register 1 = I/O Register 2 = I/O Register 3 = Concatenated value = Global Mask Register = 302016 000016 543A16 FE5516 FE55543A0000302016 C0000000FFFFFFFF16 Of the high–order 32 bits, the rightmost 30 bits are cared by the global–mask register. Therefore, the MCM69C232 will delete an entry, if it exists, which has a value of 3E55543A16 in bits 61 – 32. CHECK FOR VALUE This instruction checks for a matching value in the CAM table. The contents of I/O registers 0 – 3 are concatenated, with bit 15 of register 3 as the most significant bit, and bit 0 of register 0 as the least significant bit. The bits that have a 0 in the corresponding bit of the global–mask register are used to find a matching entry in the CAM table. If such an entry is found, the last–match–successful bit of the flag register is set. In addition, the matching entry is written to I/O registers 0 – 3, with bit 15 of register 3 as the most significant bit, and bit 0 of register 0 as the least significant bit If no match is found, the last–match–successful bit is cleared. An interrupt is generated regardless of the result, if enabled by bit 2 of the interrupt register, when the operation has been completed. The operation of the MCM69C232 guarantees that no more than one matching entry can exist in the table. If uninterrupted by match port activity, the check for value instruction will finish in 8 clock cycles. INITIALIZE TABLE If fast entry mode has been used to load the CAM table, the initialize–table operation must be used to establish the needed relationships and linkages between the entries in the table before matching can proceed. Upon completion, this operation sets the table–initialized bit in the flag register, and generates an interrupt if enabled by bit 3 of the interrupt register. It also sets the buffered entry mode bit in the flag register. This operation makes the programming model’s registers read–only for up to 12 ms after the acknowledgment of the op code write cycle. FAST ENTRY MODE This instruction is used to enter the fast–entry mode. When the MCM69C232 is in this mode, insert–value operations bypass the entry queue and write new table entries directly to the CAM table. The fast–entry mode can only be entered while the entry queue is empty, as reflected by the queue–empty flag being set (bit 4 of the flag register.) If this operation is attempted while the entry queue is not empty, the value FFFA16 is written to the error code register, the error–condition flag (bit 7) is set in the flag register, and an interrupt is generated if enabled by bit 4 of the interrupt register. MOTOROLA FAST SRAM If this mode is used to enter data, the initialize–table operation must be executed before matching operations can begin. The entry–mode bit and the table–initialized bit of the flag register (bit 3) are cleared by this operation. BUFFERED ENTRY MODE This instruction is used to enter the buffered–entry mode. When the MCM69C232 is in this mode, insert–value and delete–value operations utilize the entry queue. This mode can be entered at any time. Table entries are available for match operations immediately, without running the initialize– table operation, if all entries are made in this mode. Note that if both modes have been used to input data, none of the entries are available for matching until the initialize–table operation is executed. Conflicting table and queue values are resolved in favor of the latest entry in the queue. For example, if there is an entry in the CAM, a corresponding delete–entry in the queue, and a later insert–entry in the queue (all with the same match data), the queued insert– entry will return a match value. RETURN ENTRY COUNT This operation is used to determine the number of valid entries in the MCM69C232. The value is returned in I/O register 0, and reflects the sum of the number of valid entries in the CAM table and the inserts in the entry queue. SET GLOBAL MASK REGISTER This operation is used to indicate the bits to be used in performing matches. A 1 indicates that a bit should be ignored in the match operation, while a 0 indicates that a bit should be used in the match operation. When this operation is executed, the contents of I/O registers 0 – 3 are concatenated, with bit 15 of register 3 as the most significant bit, and bit 0 of register 0 as the least significant bit. The resulting 64 bit value is written to the global– mask register. This operation should be executed before entering required values into the CAM table. Otherwise, the initialize– table instruction must be executed if the global mask register is changed after data is loaded into the CAM. SET ALMOST–FULL POINT This operation is used to define the “almost–full” condition in the CAM table. The 12 low–order bits of I/O register 0 are copied to the almost–full–point register. If an entry is added to the MCM69C232 (via the insert–value operation) that causes the valid–entry count to equal the almost–full–point, then bit 8 of the flag register is set, and an interrupt is generated if enabled by bit 5 of the interrupt register. The value of the almost–full register can be changed dynamically during match operations. For example, it could first be set to 2048 to generate an interrupt when the table is half full. When that point is reached, the register could be reprogrammed to 3072 to provide warning that the table has become three– quarters full. The almost–full interrupt is generated, if enabled, based on the number of entries in the CAM table. Entries in the queue are not included in the count. MCM69C232 9 SET FAST–READ REGISTER VALUE This operation defines the table address that is output by the fast read operation. The least significant 12 bits of I/O register 0 are copied to the register. The queue must be empty when this instruction is executed. FAST READ This operation is used to output the contents of one entry in the CAM table. The fast–read register is used to specify the appropriate entry, and is then auto–incremented. As a result, successive execution of multiple fast–read operations will provide access to contiguous entries in the CAM table. The CAM entry is copied to I/O registers 0 – 3, with bit 15 of register 3 as the most significant bit, and bit 0 of register 0 as the least significant bit. The fast–read instruction can only be executed while the entry queue is empty, as reflected by the queue–empty flag being set (bit 4 of the flag register.) If this operation is attempted while the entry queue is not empty, the value FFFC16 is written to the error code register, the error–condition flag (bit 7) is set in the flag register, and an interrupt is generated if enabled by bit 7 of the interrupt register. SET ATM MODE When the MCM69C232 is placed in ATM mode, it provides simultaneous searching for virtual path circuits (VPCs) and virtual connection circuits (VCCs). A VCC is detected when both the virtual path identifier (VPI) and the virtual circuit identifier (VCI) of an incoming cell match an entry in the CAM. A VPC match occurs when the VPI of an incoming cell matches the VPI field of a CAM entry that has all 1s as its VCI. A VPC match is signalled by the assertion of the VPC pin along with the MS pin. At 50 MHz, a match is completed in 160 ns, whether the applied VPI/VCI belongs to a VCC or a VPC. The VCI match field must be defined as bits 32 – 47 of each entry, and the VPI match data must occupy bits 48 – 59. The VPI can be limited to bits 48 – 55, if the switch handles only User–Network Interface (UNI) protocols. The mask register should be used to “don’t care” any unused bits beyond the VPI field. Entering ATM mode will set bit 9 of the flag register. To load a VPC into the CAM table, the desired VPI value is written (right justified) to I/O register 3, FFFF16 is written to I/O register 2 as the VCI field, the upper half of the desired output word is written to I/O register 1, and the lower half of the desired output word is written to I/O register 0. Then, the “INSERT VALUE” instruction is written to the operation register. When performing a match operation, the VCI must be placed in bits 0 – 15 of the MQ port. The VPI is expected on bits 16 – 27, or bits 16 – 23 in the UNI case. Buffered entry mode insertions and deletions are modified in the following way when the MCM69C232 is in ATM mode. If you try to add a VCC with the same VPI as an existing VPC, you overwrite the VPC. If you try to delete a VCC when the VCC is not in the table, but a VPC with that VPI is in the table, the VPC will be deleted. MCM69C232 10 MATCH CYCLE TIME At 50 MHz, the MCM69C232 completes a match 160 ns after assertion of the SM signal. If minimal entries need to be added to or deleted from the CAM, the part can be cycled at 200 ns. In other words, SM can be asserted again immediately after the completion of a match operation and data output. However, idle time is required between matches to allow insertions or deletions. The worst case occurs if an entry with a match data value smaller than any other entry in the CAM is continually added and dropped from the table. The number of insertion/deletion pairs per second in this scenario is shown versus match cycle time as the curve labeled “Worst Case” in Figure 3. As shown, a match cycle time of 200 ns allows for 610 insertion/deletion pairs per second. Note that this analysis is based on a 50 MHz input clock. Values should be derated in proportion to any decrease in clock speed. For example, at 25 MHz, twice as much idle time is required to achieve the same number of insertion/deletion pairs per second. A more typical case would consist of either randomly placed insertions and deletions in the CAM table (as determined by the magnitude of the match field), or when insertions occur at one end of the table and deletions occur at the other end. The number of insertion/deletion pairs per second in this scenario is shown versus match cycle time as the curve labeled “Typical” in Figure 3. As shown, a match cycle time of 200 ns allows for 1220 insertion/deletion pairs per second. For any match cycle time 200 ns and evenly divisible by 20 ns (200 ns, 220 ns, 240 ns, ...), the time to perform a worst–case insertion or deletion is equal to 81,920*MCT / (MCT–180) ns at 50 MHz, where MCT is the match cycle time in nanoseconds. In general, the time for an insertion or deletion is proportional to its distance from the end of the CAM table. That is, entries with the largest match values take the least time to insert or delete, while entries with the smallest values take the most time. Therefore, the effective rate of insertion and deletion is maximized if the longest–lived entries are placed near the beginning of the table and the shortest–lived entries are placed near the end of the table. For an ATM application, this would correspond to the assignment of small VPI values to permanent virtual circuits and large VPI values to switched virtual circuits. Note that at start–up, when entries are loaded into the CAM via the fast–entry mode, the process is dominated by the time it takes to execute the initialization instruction that follows. The resulting effective rate of loading the CAM at start–up is approximately 270,000 entries per second. w RESET Asserting RESET removes all entries from the CAM table and entry queue. The flag register is set to 1C16 (setting the queue empty, buffered entry mode, and table initialized bits). The error register is set to FFFF16, indicating no errors. Finally, the almost full register is set to FFF16. MOTOROLA FAST SRAM INSERTION – DELETION PARTS / SEC 12,000 10,000 TYPICAL 8,000 6,000 WORST CASE 4,000 2,000 0 180 280 380 480 580 680 780 MATCH CYCLE TIME AT 50 MHz INPUT CLOCK 880 980 Figure 3. Connections per Second vs Match Cycle Time TIMING OVERVIEW CONTROL PORT The control port of the MCM69C232 is asynchronous. Data transfers, both read and write, are initiated by the assertion of the SEL signal. Address values should be valid, and WE should be high, when SEL is asserted to begin a read cycle. All values (address, WE, and SEL) should be held until the MCM69C232 asserts DTACK to signal the end of the read cycle. Address and data values should be valid, and WE should be low, when SEL is asserted to begin a write cycle. Address, data, WE, and SEL values should be held until the MCM69C232 asserts DTACK to signal the end of the write cycle. MATCH PORT The MCM69C232’s match port is synchronous in operation. When the match width is 32 bits, a match cycle can be initiated by presenting the match data on MQ31 – MQ0 and asserting the LH/SM signal with the appropriate setup time relative to the rising edge of the clock. The assertion of the MC output signifies the completion of the match cycle. If v MOTOROLA FAST SRAM a match has been found, the MS output is also asserted. If the match is a virtual path circuit match in ATM mode, the VPC output will be asserted with the MS output. Output data, if any, is enabled by the assertion of the G input. If the match width is greater than 32 bits, the lower bits are first latched into the MCM69C232 by the LL input. The match cycle is then initiated as specified in the previous paragraph. DEPTH EXPANSION Multiple CAMs can be cascaded to increase the depth of the match table. The hardware requirements are very straightforward, as the following pins on each device are simply wired in parallel: A2 – A0, DQ15 – DQ0, WE, IRQ, DTACK, MQ31 – MQ0, K, G, LH/SM, MC, MS, and VPC. Four CAMs can be easily cascaded. Simulations show that eight devices can be cascaded if care is taken to minimize the length of the PC board traces connecting the CAMs. The buffered entry mode prevents multiple matching entries in a single CAM. The check for value instruction should be used to verify that multiple matching entries will not result from a potential new entry. If a match is found in CAM 1, for example, the new value should be placed in CAM 1, where it will replace the existing entry. MCM69C232 11 DEPTH EXPANSION EXAMPLE CASCADING FOUR MCM69C232s FOR A 16K WORD TABLE CONTROL PORT MATCH PORT CAM 0 A2 – A0 DQ31 – DQ0 A0 – A2 MQ0 – MQ31 DQ0 – DQ31 SEL0 WE IRQ DTACK WE MQ31 – MQ0 K K G LM/SM G LH/SM MC MC MS MS VPC VPC IRQ DTACK CAM 1 A0 – A2 MQ0 – MQ31 K DQ0 – DQ31 SEL1 G LM/SM WE MC IRQ MS DTACK VPC CAM 2 A0 – A2 MQ0 – MQ31 K DQ0 – DQ31 SEL2 G LM/SM WE MC IRQ MS DTACK VPC CAM 3 A0 – A2 DQ0 – DQ31 MQ0 – MQ31 K G LM/SM SEL3 WE MC IRQ MS DTACK VPC MCM69C232 12 MOTOROLA FAST SRAM MOTOROLA FAST SRAM MCM69C232 13 LOW 32 BITS IN t KHMQX t KHLL HIGH 32 BITS IN REFERENCE DATA INPUT t GHMQZ t KHLL 0 t MQVKH t KHLH t KHLH 1 2 4 t SMSM t GLMQX 3 5 t KHVPL t KHMSL t KHMCL t KHMQV 6 DATA OUT 8 9 MATCH DATA OUTPUT 7 DATA IN t KHKL t KHVPH t KHMSH t KHMCH t KHLH t KLKH NOTE: In normal operation, all matches would be the same size, i.e., LL would either be used in every match cycle or in none. This diagram shows a 64 bit match followed by a 32 bit match in order to illustrate all the key specs. VPC MS MC MQ31 – MQ0 G LH/SM LL K t KHKH MATCH PORT TIMING MCM69C232 14 MOTOROLA FAST SRAM IRQ DTACK WE DQ15 – DQ0 SEL A2 – A0 t DVSL t SLDTL t WVSL t AVSL t DTLTL A DATA – IN t ILIH t DTLWH t DTLDX t DTLSH t DTLAX t SHDTH t DVDTL t SLDTL t AVQV t WHQX t DTHSL CONTROL PORT TIMING t AVSL B DATA – OUT t DTLSH t SHDTH t SHQZ JTAG AC OPERATING CONDITIONS AND CHARACTERISTICS FOR THE TEST ACCESS PORT (IEEE 1149.1) (TJ = 20 to + 120°C, Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Measurement Timing Level . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . . . . . . . . 50 Ω Termination to 1.5 V TAP CONTROLLER TIMING MCM69C232 P Parameter S b l Symbol Min Max U i Unit tCK 30 — ns Clock High Time tCKH 12 — ns Clock Low Time tCKL 12 — ns Cycle Time Clock Low to Output Valid N Notes tA 5 9 ns Clock Low to Output High–Z tCKZ 0 9 ns 1 Clock Low to Output Active tCKX 0 9 ns 2, 3 Setup Times: TMS TDI TRST tS tSD tSR 2 2 2 — ns Hold Times: TMS TDI TRST tH tHD tHR 2 2 10 — ns NOTES: 1. TDO will High–Z from a clock low edge depending on the current state of the TAP state machine. 2. TDO is active only in the SHIFT–IR and SHIFT–DR state of the TAP state machine. 3. Transition is measured ± 500 mV from steady–state voltage. This parameter is sampled and not 100% tested. tCKH tCK tCKL TCK TEST CLOCK tS tH TMS TEST MODE SELECT tSD tHD TDI TEST DATA IN tA tCKZ tCKX TDO TEST DATA OUT tHR tSR TRST Figure 4. TAP Controller Timing MOTOROLA FAST SRAM MCM69C232 15 TEST ACCESS PORT DESCRIPTION INSTRUCTION SET A five pin IEEE Standard 1149.1 Test Port (JTAG) is included on this device. When the TAP (Test Access Port) controller is in the SHIFT–IR state, the instruction register is placed between TDI and TDO. In this state, the desired instruction would be serially loaded through the TDI input. TRST resets the TAP controller to the test–logic reset state. The TAP instruction set for this device are as follows. STANDARD INSTRUCTIONS Instruction Code (Binary) BYPASS 1111* Bypass instruction SAMPLE/PRELOAD 0010 Sample and/or preload instruction EXTEST 0000 Extest instruction HIGHZ 1001 High–Z all output pins while bypass register is between TDI and TDO CLAMP 1100 Description Clamp output pins while bypass register is between TDI and TDO * Default state at power–up. SAMPLE/PRELOAD TAP INSTRUCTION The SAMPLE/PRELOAD TAP instruction is used to allow scanning of the boundary–scan register without causing interference to the normal operation of the chip logic. The 62–bit boundary–scan register contains bits for all device signal and clock pins and associated control signals. This register is accessible when the SAMPLE/PRELOAD TAP instruction is loaded into the TAP instruction register in the SHIFT–IR state. When the TAP controller is then moved to the SHIFT–DR state, the boundary–scan register is placed between TDI and TDO. This scan register can then be used prior to the EXTEST instruction to preload the output pins with desired values so that these pins will drive the desired state when the EXTEST instruction is loaded. As data is written into TDI, data also streams out TDO which can be used to pre–sample the inputs and outputs. SAMPLE/PRELOAD would also be used prior to the CLAMP instruction to preload the values on the output pins that will be driven out when the CLAMP instruction is loaded. EXTEST TAP INSTRUCTION The EXTEST instruction is intended to be used in conjunction with the SAMPLE/PRELOAD instruction to assist in testing board level connectivity. Normally, the SAMPLE/ PRELOAD instruction would be used to preload all output pins. The EXTEST instruction would then be loaded. During EXTEST, the boundary–scan register is placed between TDI and TDO in the SHIFT–DR state of the TAP controller. Once the EXTEST instruction is loaded, the TAP controller would then be moved to the run–test/idle state. In this state, one cycle of TCK would cause the preloaded data on the output pins to be driven while the values on the input pins would be sampled. Note the TCK, not the clock pin (CLK), is used as the clock input while CLK is only sampled during EXTEST. MCM69C232 16 After one clock cycle of TCK, the TAP controller would then be moved to the SHIFT–DR state where the sampled values would be shifted out of TDO (and new values would be shifted in TDI). These values would normally be compared to expected values to test for board connectivity. CLAMP TAP INSTRUCTION The CLAMP instruction is provided to allow the state of the signals driven from the output pins to be determined from the boundary–scan register while the bypass register is selected as the serial path between TDI and TDO. The signals driven from the output pins will not change while the CLAMP instruction is selected. EXTEST could also be used for this purpose, but CLAMP shortens the board scan path by inserting only the bypass register between TDI and TDO. To use CLAMP, the SAMPLE/PRELOAD instruction would be used first to scan in the values that will be driven on the output pins when the CLAMP instruction is active. HIGHZ TAP INSTRUCTION The HIGH–Z instruction is provided to allow all the outputs to be placed in an inactive drive state (high–Z). During the HIGH–Z instruction the bypass register is connected between TDI and TDO. BYPASS TAP INSTRUCTION The BYPASS instruction is the default instruction loaded at power up. This instruction will place a single shift register between TDI and TDO during the SHIFT–DR state of the TAP controller. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. BOUNDARY SCAN REGISTER The boundary scan register is identical in length to the number of active input, output, and I/O connections on the device (not counting the TAP pins). The boundary scan register, under the control of the TAP controller, is loaded with the contents of the RAM I/O ring when the controller is in capture_DR state and then is placed between the TDI and TDO pins when the controller is moved to shift_DR state. Several TAP instructions can be used to activate the boundary scan register. The Bit Scan Order table (Table 2) describes which device pin connects to each boundary scan register location. The first column defines the bit’s position in the boundary scan register. The shift register bit at G (i.e., first to be shifted out) is defined as bit 1. The second column is the name of the pin, third column is the pin number and the fourth column is the pin type (input, output, or I/O). DISABLING THE TEST ACCESS PORT AND BOUNDARY SCAN It is possible to use this device without utilizing the four pins used for the test access port. To circuit disable the device, TCK must be tied to VSS to preclude mid level inputs. Although TDI and TMS are designed in such a way that an undriven input will produce a response equivalent to the application of a logic 1, it is still advisable to tie these inputs to VDD through a 1K resistor. TDO should remain unconnected. MOTOROLA FAST SRAM Table 2. Sample/Preload Boundary Scan Register Bit Definitions Bit Number Bit Pin Name Bit Pin Number Pin Type Bit Number Bit Pin Name Bit Pin Number Pin Type 1 G 61 Input 32 MQ6 6 I/O 2 MS 62 Output 33 MQ5 7 I/O 3 VPC 63 Output 34 MQ4 8 I/O 4 MC 64 Output 35 MQ3 11 I/O 5 MQ31 67 I/O 36 MQ2 12 I/O 6 MQ30 68 I/O 37 MQ1 13 I/O 7 MQ29 69 I/O 38 MQ0 14 I/O 8 MQ28 70 I/O 39 DQ15 17 I/O 9 MQ27 73 I/O 40 DQ14 18 I/O 10 MQ26 74 I/O 41 DQ13 19 I/O 11 MQ25 75 I/O 42 DQ12 20 I/O 12 MQ24 76 I/O 43 DQ11 23 I/O 13 MQ23 79 I/O 44 DQ10 24 I/O 14 MQ22 80 I/O 45 DQ9 25 I/O 15 MQ21 81 I/O 46 DQ8 26 I/O 16 MQ20 82 I/O 47 DQ7 29 I/O 17 MQ19 85 I/O 48 DQ6 30 I/O 18 MQ18 86 I/O 49 DQ5 31 I/O 19 MQ17 87 I/O 50 DQ4 32 I/O 20 MQ16 88 I/O 51 DQ3 35 I/O 21 LH/SM 89 Input 52 DQ2 36 I/O 22 LL 92 Input 53 DQ1 37 I/O 23 MQ15 93 I/O 54 DQ0 38 I/O 24 MQ14 94 I/O 55 A2 42 Input 25 MQ13 95 I/O 56 A1 43 Input 26 MQ12 96 I/O 57 A0 44 Input 27 MQ11 99 I/O 58 WE 45 Input 28 MQ10 100 I/O 59 SEL 46 Input 29 MQ9 1 I/O 60 RESET 56 Input 30 MQ8 2 I/O 61 IRQ 57 Output 31 MQ7 5 I/O 62 DTACK 58 Output MOTOROLA FAST SRAM MCM69C232 17 the instruction that is currently loaded in the TAP instruction register (see Figure 5). An undriven TDI pin will produce the same result as a logic one input level. TEST ACCESS PORT PINS TCK — TEST CLOCK (INPUT) Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TDO — TEST DATA OUT (OUTPUT) Output that is active depending on the state of the TAP state machine (see Figure 5). Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. TMS — TEST MODE SELECT (INPUT) The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. TRST — TAP RESET This device has a TRST pin. TRST is optional in IEEE 1149.1. Asserting the asynchronous TRST places the TAP controller in test–logic reset state. Test–logic reset state can also be entered by holding TMS high for five rising edges of TCK. This type of reset does not affect the operation of the system logic. TDI — TEST DATA IN (INPUT) The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and TEST–LOGIC RESET 1 0 RUN–TEST/ IDLE 0 1 SELECT DR–SCAN SELECT IR–SCAN 1 0 1 0 1 CAPTURE–DR CAPTURE–IR 0 0 SHIFT–IR 0 SHIFT–DR 1 1 1 EXIT1–IR 0 0 PAUSE–IR 0 PAUSE 1–DR 1 0 1 0 EXIT2–DR EXIT2–IR 1 1 PAUSE 2–DR 1 0 1 EXIT1–DR 0 1 UPDATE–IR 0 1 0 NOTE: The value adjacent to each state transition represents the signal present at TMS at the rising edge of TCK. Figure 5. TAP Controller State Diagram MCM69C232 18 MOTOROLA FAST SRAM ORDERING INFORMATION (Order by Full Part Number) MCM 69C232 XX XX X Motorola Memory Prefix Blank = Trays, R = Tape and Reel Part Number Speed (20 = 20 ns) Package (TQ = TQFP) Full Part Numbers — MCM69C232TQ20 MCM69C232TQ20R Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. 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MOTOROLA FAST SRAM MCM69C232 19 PACKAGE DIMENSIONS TQ PACKAGE TQFP CASE 983A–01 4X e 0.20 (0.008) H A–B D 2X 30 TIPS e/2 0.20 (0.008) C A–B D –D– 80 51 50 81 B E/2 –A– –X– X=A, B, OR D B –B– VIEW Y E1 E E1/2 BASE METAL PLATING ÉÉÉÉ ÇÇÇÇ ÇÇÇÇ ÉÉÉÉ b1 31 100 1 30 D1/2 c D/2 b D1 D 0.13 (0.005) 2X 20 TIPS A q 2 0.10 (0.004) C –H– –C– SEATING PLANE q 3 VIEW AB S S q 1 R2 A1 L2 L L1 R1 C A–B S D S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 3. DATUMS –A–, –B– AND –D– TO BE DETERMINED AT DATUM PLANE –H–. 4. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE –C–. 5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS D1 AND B1 DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE –H–. 6. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE b DIMENSION TO EXCEED 0.45 (0.018). 0.25 (0.010) A2 M SECTION B–B 0.20 (0.008) C A–B D 0.05 (0.002) c1 GAGE PLANE q VIEW AB DIM A A1 A2 b b1 c c1 D D1 E E1 e L L1 L2 S R1 R2 q 1 2 q3 q q MILLIMETERS MIN MAX ––– 1.60 0.05 0.15 1.35 1.45 0.22 0.38 0.22 0.33 0.09 0.20 0.09 0.16 22.00 BSC 20.00 BSC 16.00 BSC 14.00 BSC 0.65 BSC 0.45 0.75 1.00 REF 0.50 REF 0.20 ––– 0.08 ––– 0.08 0.20 0_ 7_ 0_ ––– 11 _ 13 _ 11 _ 13 _ Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado, 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shagawa-ku, Tokyo, Japan. 03-5487-8488 Mfax : [email protected] – TOUCHTONE 1-602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, Motorola Fax Back System – US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 – http://sps.motorola.com /mfax / HOME PAGE : http://motorola.com/sps / CUSTOMER FOCUS CENTER: 1-800-521-6274 MCM69C232 20 ◊ MCM69C232/D MOTOROLA FAST SRAM