MOTOROLA Order this document by MCM69D618/D SEMICONDUCTOR TECHNICAL DATA MCM69D618 64K x 18 Bit Synchronous Dual I/O, Dual Address SRAM The MCM69D618 is a 1M–bit static random access memory, organized as 64K words of 18 bits. It features common data input and data output buffers and incorporates input and output registers on–board with high speed SRAM. The MCM69D618 allows the user to concurrently perform reads, writes, or pass–through cycles in combination on the two data ports. The two address ports (AX, AY) determine the read or write locations for their respective data ports (DQX, DQY). The synchronous design allows for precise cycle control with the use of an external single clock (K). All signal pins except output enables (GX, GY) are registered on the rising edge of clock (K). The pass–through feature allows data to be passed from one port to the other, in either direction. The PTX input must be asserted to pass data from port X to port Y. The PTY will likewise pass data from port Y to port X. A pass–through operation takes precedence over a read operation. For the case when AX and AY are the same, certain protocols are followed. If both ports are read, the reads occur normally. If one port is written and the other is read, the read from the array will occur before the data is written. If both ports are written, only the data on DQY will be written to the array. • • • • • • • • • • • • • • TQ PACKAGE 100 LEAD TQFP CASE 983A–01 Single 3.3 V ± 5% Power Supply Fast Access Times: 6/8 ns Max Throughput of 1.49 Gigabits/Second Single Clock Operation Address, Data Input, E1, E2, PTX, PTY, WX, WY, and Data Output Registers On–Chip 83 MHz Maximum Clock Frequency Self Timed Write Two Bi–Directional Data Buses Can be Configured as Separate I/O Pass–Through Feature Asynchronous Output Enables (GX, GY) LVTTL Compatible I/O Concurrent Reads and Writes 100–Pin TQFP Package Suggested Applications — ATM — Ethernet Switches — Cell/Frame Buffers — SNA Switches — Routers — Shared Memory Product Family Configurations Part Number MCM69D536 MCM69D618 Dual Address n n MCM67Q709A MCM67Q909 Single Address Note 1 Note 1 n n Dual I/O n n Separate I/O Configuration Note 2 32K x 36 VDD 3.3 V Note 2 64K x 18 3.3 V 128K x 9 5.0 V 512K x 9 5.0 V n n NOTES: 1. Tie AX and AY address ports together for the part to function as a single address part. 2. Tie GX high for DQX to be inputs and tie WY high and GY low for DQY to be outputs. REV 5 1/16/98 Motorola, Inc. 1998 MOTOROLA FAST SRAM MCM69D618 1 BLOCK DIAGRAM AX 16 ADDRESS REGISTER WX WRITE X REGISTER PTX PTX REGISTER E1 E2 WRITE DRIVER SENSE AMPS SENSE AMPS WRITE DRIVER PASS–THROUGH DATA IN REGISTER K ADDRESS REGISTER 64K x 18 ARRAY OUTPUT REGISTER OUTPUT REGISTER DQX DQY DATA IN REGISTER 16 AY WRITE Y REGISTER WY PTY REGISTER PTY K ENABLE REG 1 ENABLE REG 2 GX GY MCM69D618 2 MOTOROLA FAST SRAM AX6 AY6 AX7 AY7 K VDD VSS GY GX E2 E1 WY WX PTY PTX AX8 AY8 AX9 AY9 AX15 PIN ASSIGNMENT VDD VSS AY15 VSS VDD DQX8 DQY8 DQX7 DQY7 VSS VDD DQX6 DQY6 DQX5 DQY5 VSS VDD DQY4 DQX4 DQY3 DQX3 VSS VDD DQY2 DQX2 DQY1 DQX1 VSS VDD DQY0 DQX0 AY14 AY4 AX4 AY3 AX3 AY2 AX2 AY1 AX1 AY0 AX0 VDD AX10 AY10 AX11 AY11 AX12 AY12 AX13 AY13 AX14 DQX9 DQY9 DQX10 DQY10 VDD VSS DQX11 DQY11 DQX12 DQY12 VDD VSS DQY13 DQX13 DQY14 DQX14 VDD VSS DQY15 DQX15 DQY16 DQX16 VDD VSS DQY17 DQX17 AY5 AX5 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MOTOROLA FAST SRAM MCM69D618 3 PIN DESCRIPTIONS Pin Locations Symbol Type Description 40, 38, 36, 34, 32, 30, 100, 98, 85, 83, 42, 44, 46, 48, 50, 81 AX0 – AX15 Input Address Port X. Never allow floating addresses for inputs AX0 – AX15. A pullup resistor is needed. 39, 37, 35, 33, 31, 29, 99, 97, 84, 82, 43, 45, 47, 49, 51, 80 AY0 – AY15 Input Address Port Y. Never allow floating addresses for inputs AY0 – AY15. A pullup resistor is needed. 52, 56, 58, 62, 64, 69, 71, 75, 77, 3, 5, 9, 11, 16, 18, 22, 24, 28 DQX0 – DQX17 I/O Data Input/Output Port X. 53, 57, 59, 63, 65, 68, 70, 74, 76, 4, 6, 10, 12, 15, 17, 21, 23, 27 DQY0 – DQY17 I/O Data Input/Output Port Y. 90 E1 Input Synchronous Chip Enable: Active low. 91 E2 Input Synchronous Chip Enable: Active high. 92 GX Input Asynchronous Output Enable Port X Input: Low — enables output buffers (DQXx pins). High — DQXx pins are high impedance. 93 GY Input Asynchronous Output Enable Port Y Input: Low — enables output buffers (DQYx pins). High — DQYx pins are high impedance. 96 K Input Clock: This signal registers the address, data in, and all control signals except G. 86 PTX Input Pass–Through Port X. 87 PTY Input Pass–Through Port Y. 88 WX Input Synchronous Write Enable Port X. 89 WY Input Synchronous Write Enable Port Y. 1, 7, 13, 19, 25, 41, 54, 60, 66, 72, 78, 95 VDD Supply + 3.3 V Power Supply. 2, 8, 14, 20, 26, 55, 61, 67, 73, 79, 94 VSS Supply Ground. MCM69D618 4 MOTOROLA FAST SRAM TRUTH TABLE (See Notes 1 through 5) Input at tn Clock O Operation i N Number b E1 E2 WX WY PTX PTY Operation 1 H X X X X X Deselected 2 X L X X X X Deselected 3 L H 0 X X X Write X Port 4 L H X 0 X X Write Y Port 5 L H X X 0 X Pass–Through X to Y 6 L H X X X 0 Pass–Through Y to X 7 L H 1 X 1 1 Read X 8 L H X 1 1 1 Read Y NOTES: 1. GX/GY must be controlled to avoid bus contention issues during write and pass–through cycles. 2. Operation numbers 3 – 6 can be used in any combination. 3. Operation numbers 4 and 7, 3 and 8, 7 and 8 can be combined. 4. Operation number 5 can not be combined with operation number 7 or 8 because pass–through takes precedence over a read operation. 5. Operation number 6 can not be combined with operation number 7 or 8 because pass–through takes precedence over a read operation. tn tn + 1 K ADDRESS & CONTROL VALID PIPELINED READ ACCESS DATA INPUT D VALID PASS–THROUGH DATA OUTPUT Q VALID ABSOLUTE MAXIMUM RATINGS (See Note) Symbol Value Unit VDD – 0.5 to + 4.6 V Vin, Vout – 0.5 to VDD + 0.5 V Output Current Iout ± 20 mA Power Dissipation PD TBD W Temperature Under Bias Tbias – 10 to + 85 °C Operating Temperature TA 0 to + 70 °C Tstg – 55 to + 125 °C Rating Power Supply Voltage Voltage Relative to VSS for Any Pin Except VDD Storage Temperature — Plastic This is a synchronous device. All synchronous inputs must meet specified setup and hold times with stable logic levels for ALL rising edges of clock (K) while the device is selected. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high–impedance circuits. NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. MOTOROLA FAST SRAM MCM69D618 5 PACKAGE THERMAL CHARACTERISTICS (See Note 1) Symbol TQFP Unit Notes RθJA 40 25 °C/W 2 Junction to Board (Bottom) RθJB 17 °C/W 3 Junction to Case (Top) RθJC 9 °C/W 4 Rating Junction to Ambient (@ 200 lfm) Single–Layer Board Four–Layer Board NOTES: 1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, board population, and board thermal resistance. 2. Per SEMI G38–87. 3. Indicates the average thermal resistance between the die and the printed circuit board. 4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1). DC OPERATING CONDITIONS AND CHARACTERISTICS (VDD = 3.3 V ± 5%, TA = 0 to 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS AND SUPPLY CURRENTS Parameter Symbol Min Max Unit Supply Voltage (Operating Voltage Range) VDD 3.135 3.465 V Input High Voltage VIH 2.0 VDD + 0.5** V Input Low Voltage VIL – 0.5* 0.8 V Ilkg(I) — ± 1.0 µA Input Leakage Current (All Inputs, Vin = 0 to VDD) Ilkg(O) — ± 1.0 µA AC Supply Current (Iout = 0 mA) (VDD = max, f = fmax) MCM69D618–6 ns MCM69D618–8 ns IDDA — — 300 300 mA CMOS Standby Supply Current (Deselected, Clock (K) Cycle Time ≥ tKHKH, All Inputs Toggling at CMOS Levels Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V) MCM69D618–6 ns MCM69D618–8 ns ISB1 — — 100 100 mA Output Low Voltage (IOL = + 8.0 mA) VOL — 0.4 V Output High Voltage (IOH = – 4.0 mA) VOH 2.4 VDD V Symbol Max Unit Address and Data Input Capacitance Cin 6 pF Control Pin Input Capacitance Cin 6 pF Cout 8 pF Output Leakage Current (E = VIH, Vout = 0 to VDD) * VIL ≥ –1.5 V for t ≤ tKHKH/2. ** VIH ≤ VDD + 1.0 V for t ≤ tKHKH/2. CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 0 to + 70°C, Periodically Sampled Rather Than 100% Tested) Parameter Output Capacitance MCM69D618 6 MOTOROLA FAST SRAM AC OPERATING CONDITIONS AND CHARACTERISTICS (VDD = 3.3 V ± 5%, TA = 0 to 70°C, Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . . Figure 1 Unless Otherwise Noted READ/WRITE CYCLE TIMING MCM69D618–6 MCM69D618–8 S b l Symbol Min Max Min Max U i Unit N Notes Cycle Time tKHKH 12 — 15 — ns 1 Clock Access Time tKHQV — 6 — 8 ns Clock Low Pulse Width tKLKH 4 — 6 — ns P Parameter Clock High Pulse Width tKHKL 4 — 6 — ns Clock High to Data Output Active tKHQX1 0 — 0 — ns Clock High to Data Output Invalid tKHQX2 2 — 2 — ns Clock High to Data Output High–Z tKHQZ — 5 — 5 ns Output Enable Low to Data Output Valid tGLQV — 6 — 8 ns 0 — ns 2 Output Enable Low to Data Output Low–Z tGLQX 0 — Output Enable High to Data Output High–Z tGHQZ — 5 — 8 ns 2 Setup Times: AWR0 – AWR14 ARD0 – ARD14 W PT E1, E2 D0 – D35 tAVKH tAVKH tWVKH tPTVKH tEVKH tDVKH 2.5 — 3 — ns 3 Hold Times: AWR0 – AWR14 ARD0 – ARD14 W PT E1, E2 D0 – D35 tKHAX tKHAX tKHWX tKHPTX tKHEX tKHDX 0.5 — 1 — ns 3 3 3 3 3 3, 4 NOTES: 1. All read and write cycles are referenced from K. 2. This parameter is sampled and not 100% tested. 3. This is a synchronous device. All synchronous inputs must meet the specified setup and hold times with stable logic levels for ALL rising edges of clock (K) while the device is selected. 4. tKHDX minimum for Port Y only extends to 4.0 ns only for the special case when the Y– and X–address are identical on the same rising clock edge. RL = 50 Ω OUTPUT Z0 = 50 Ω VL = 1.5 V Figure 1. AC Test Load MOTOROLA FAST SRAM MCM69D618 7 READ CYCLE TIMING FROM BOTH PORTS (WX, WY, PTX, PTY HIGH) tKHKH tKLKH tKHKL K tAVKH AX PORT X 1 tKHAX 2 3 4 5 6 7 8 9 GX tGLQV tKHQV tGHQZ tKHQX1 Q(1) DQX Q(2) Q(3) Q(5) Q(6) Q(7) tGLQX tEVKH E tKHEX AY PORT Y 12 13 14 15 16 6 7 19 20 Q(16) Q(6) Q(7) GY tKHQZ DQY Q(12) Q(13) Q(14) tKHQV NOTE: E Low = E1 Low and E2 High. E High = E1 High or E2 Low. MCM69D618 8 MOTOROLA FAST SRAM WRITE CYCLE TIMING TO BOTH PORTS (PTX, PTY HIGH) tKHKH tKLKH tKHKL K AX 1 2 3 4 5 6 7 8 9 D(8) D(9) 19 20 tKHWX tWVKH WX PORT X GX tDVKH DQX tKHDX D(2) D(3) D(4) 13 14 15 5 6 18 D(14) D(15) D(5) D(6) D(18) E AY 12 WY PORT Y GY DQY D(19) PORT Y TAKES PRECEDENCE OVER PORT X WHEN AX = AY AND WRITING BOTH PORTS. NOTE: E Low = E1 Low and E2 High. E High = E1 High or E2 Low. MOTOROLA FAST SRAM MCM69D618 9 WRITE TO PORT X AND PASS–THROUGH TO PORT Y (See Note) tKHKH tKLKH tKHKL K AX 1 2 3 4 5 6 7 8 9 18 19 20 WX PORT X GX tKHPTX tPTVKH PTX tDVKH DQX tKHDX D(2) D(3) D(X) D(Y) D(6) 13 14 15 16 17 E AY 12 WY PORT Y GY PTY tKHQV tKHQX2 DQY tKHQZ D(3) D(X) D(Y) D(17) E Low = E1 Low and E2 High. E High = E1 High or E2 Low. NOTE: The timing diagram is valid for the opposite case as well, i.e., writing to Port Y and passing through to Port X. MCM69D618 10 MOTOROLA FAST SRAM COMBINATION READ/WRITE WITH SAME ADDRESS ON EACH PORT tKHKH tKLKH tKHKL K AX TRY TO WRITE TRY TO WRITE READ 1 2 1 READ READ READ READ 2 READ 3 WX PORT X GX DQX AY D(ABC) D(DEF) Q(PQR) WRITE WRITE READ READ READ WRITE 1 2 1 2 3 2 Q(XYZ) READ Q(JKL) READ 3 WY PORT Y GY DQY D(PQR) D(XYZ) Q(PQR) D(JKL) Q3 Q(JKL) PORT Y TAKES PRECEDENCE OVER PORT X WHEN AX = AY AND WRITING BOTH PORTS. PTX = PTY = high. D(Value) = Value is the input to the data port. Q(Value) = Value is the output from the data port. MOTOROLA FAST SRAM MCM69D618 11 ORDERING INFORMATION (Order by Full Part Number) MCM 69D618 XX XX Motorola Memory Prefix X Shipping Method (R = Tape and Reel, Blank = Rails) Part Number Speed (6 = 6ns, 8 = 8 ns) Package (TQ = TQFP) Full Part Numbers — MCM69D618TQ6 MCM69D618TQ6R MCM69D618 12 MCM69D618TQ8 MCM69D618TQ8R MOTOROLA FAST SRAM PACKAGE DIMENSIONS TQFP PACKAGE 100 PIN CASE 983A–01 4X e 0.20 (0.008) H A–B D 2X 30 TIPS e/2 0.20 (0.008) C A–B D –D– 80 51 50 81 B E/2 –A– –X– B X=A, B, OR D –B– VIEW Y E1 E E1/2 BASE METAL PLATING ÉÉÉÉ ÇÇÇÇ ÇÇÇÇ ÉÉÉÉ b1 31 100 1 30 D1/2 c D/2 b D1 D 0.13 (0.005) 2X 20 TIPS A q 2 0.10 (0.004) C –H– –C– SEATING PLANE q 3 VIEW AB S S q 1 0.25 (0.010) R2 A2 A1 R1 L2 L L1 VIEW AB C A–B S D S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS –A–, –B– AND –D– TO BE DETERMINED AT DATUM PLANE –H–. 5. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE –C–. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS D1 AND B1 DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE –H–. 7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE b DIMENSION TO EXCEED 0.45 (0.018). GAGE PLANE q DIM A A1 A2 b b1 c c1 D D1 E E1 e L L1 L2 S R1 R2 q q q q MOTOROLA FAST SRAM M SECTION B–B 0.20 (0.008) C A–B D 0.05 (0.002) c1 1 2 3 MILLIMETERS MIN MAX ––– 1.60 0.05 0.15 1.35 1.45 0.22 0.38 0.22 0.33 0.09 0.20 0.09 0.16 22.00 BSC 20.00 BSC 16.00 BSC 14.00 BSC 0.65 BSC 0.45 0.75 1.00 REF 0.50 REF 0.20 ––– 0.08 ––– 0.08 0.20 0_ 7_ 0_ ––– 11 _ 13 _ 11 _ 13 _ INCHES MIN MAX ––– 0.063 0.002 0.006 0.053 0.057 0.009 0.015 0.009 0.013 0.004 0.008 0.004 0.006 0.866 BSC 0.787 BSC 0.630 BSC 0.551 BSC 0.026 BSC 0.018 0.030 0.039 REF 0.020 REF 0.008 ––– 0.003 ––– 0.003 0.008 0_ 7_ 0_ ––– 11 _ 13 _ 11 _ 13 _ MCM69D618 13 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado, 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shagawa-ku, Tokyo, Japan. 03-5487-8488 Mfax : [email protected] – TOUCHTONE 1-602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, Motorola Fax Back System – US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 – http://sps.motorola.com /mfax / HOME PAGE : http://motorola.com/sps / CUSTOMER FOCUS CENTER: 1-800-521-6274 MCM69D618 14 ◊ MCM69D618/D MOTOROLA FAST SRAM