MOTOROLA MCM69T618

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
64K x 18 Bit Synchronous
Pipelined Cache Tag RAM
The MCM69T618 is a 1M–bit synchronous fast static RAM with integrated tag
compare function. It is designed to address tag RAM for 512KB, 1MB, or 2MB
secondary cache as well as to be used as a data RAM for 512KB caches. This
device is organized as 64K words of 18 bits each. It integrates input registers,
output registers, tag comparators, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache tag RAM applications. Synchronous
design allows precise cycle control with the use of an external clock (K). BiCMOS
circuitry reduces the overall power consumption of the integrated functions for
greater reliability.
Addresses (SA), data inputs (DQ), write enable (SW), and chip enable (SE0
and SE1) are all controlled through positive–edge–triggered noninverting registers. Data enable (DE) is sampled on the rising clock edge while output enable
(G) and match output enable (MG) are asynchronous.
Write cycles are internally self–timed and initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, pipelined SRAM output data is temporarily stored by an
edge–triggered output register and then released to the output buffers at the next
rising edge of clock (K).
Compare cycles begin as read cycles with output disabled, so compare data
can be loaded into the input register. The comparator compares the read data
with the registered input data, and a match signal is generated. The match output
is also stored by an output register and released to the match output buffer at the
next rising edge of clock (K).
The MCM69T618 operates from a single 3.3 V power supply and all inputs and
outputs are LVTTL compatible.
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Order this document
by MCM69T618/D
MCM69T618
TQ PACKAGE
TQFP
CASE 983A–01
MCM69T618–5 = 5 ns Clock–to–Match / 10 ns cycle
Single 3.3 V + 10%, – 5% Power Supply
Pipelined Data Comparator
Pipelined Chip Enable and Write Enable for Data (DQ) Output Enable Path
64K x 18 Organization Supports Up to 2MB Cache
Synchronous Data Input Register Load Enable (DE)
Internally Self–Timed Write Cycle
Asynchronous Data I/O Output Enable (G)
Asynchronous Match Output Enable (MG)
100–Pin TQFP Package
REV 5
12/23/97

Motorola, Inc. 1997
MOTOROLA
FAST SRAM
MCM69T618
1
FUNCTIONAL BLOCK DIAGRAM
SA
REGISTER
16
64K x 18 ARRAY
WRITE
DRIVER
MATCH
REGISTER
COMPARE
18
18
MG
DE
DATA–IN
REGISTER
LATCH
DATA–OUT
REGISTER
K
K
SW
REGISTER
REGISTER
18
SE0
SE1
G
MCM69T618
2
LATCH
18
REGISTER
DQ1–DQ18
MOTOROLA FAST SRAM
SA
SA
SE1
SE0
NC
NC
NC
NC
NC
VCC
VSS
K
NC
SW
G
NC
NC
NC
SA
SA
PIN ASSIGNMENT
100 99 98 97 9695 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 3738 39 40 41 42 43 44 4546 47 48 49 50
SA
NC
NC
VCC
VSS
NC
DQ9
DQ8
DQ7
VSS
VCC
DQ6
DQ5
VSS
NC
VCC
NC
DQ4
DQ3
VCC
VSS
DQ2
DQ1
NC
NC
VSS
VCC
NC
NC
NC
NC
SA
SA
SA
SA
SA
SA
VSS
MATCH
VSS
VCC
DE
MG
SA
SA
SA
SA
SA
NC
NC
NC
NC
NC
VCC
VSS
NC
NC
DQ10
DQ11
VSS
VCC
DQ12
DQ13
NC
VCC
NC
VSS
DQ14
DQ15
VCC
VSS
DQ16
DQ17
DQ18
NC
VSS
VCC
NC
NC
NC
Not to Scale
TOP VIEW
100–PIN TQFP
MOTOROLA FAST SRAM
MCM69T618
3
PIN DESCRIPTIONS
Pin Locations
Symbol
Type
Description
42
DE
Input
Data Enable Input: Latched on the rising clock edge, active low. The data input
register is only updated when DE is low.
8, 9, 12, 13, 18, 19, 22,
23, 24, 58, 59, 62, 63,
68, 69, 72, 73, 74
DQ1 – DQ18
I/O
Synchronous Data I/O: For write cycles, registered on the rising clock edge.
Two cycles after a read command, the read data is output on the DQ pins
provided that G is low. On the same cycle of a write command, the write data
is input on the DQ signals.
86
G
Input
Output Enable: Asynchronous pin, active low. G must be low for read data to
be output two cycles after a read command. If G is high, the data output DQ
will remain in high impedance even if a read command occurs internally.
Clock: All the signals except G and MG are controlled by the clock.
89
K
Input
39
MATCH
Output
43
MG
Input
Match Output Enable: Asynchronous pin, active low. When MG is low, the
MATCH output driver is on, otherwise the MATCH output driver is in high
impedance.
32, 33, 34, 35, 36, 37,
44, 45, 46, 47, 48, 80,
81, 82, 99, 100
SA
Input
Synchronous Address Inputs: Registered on the rising clock edge. The
address pins select one of the 64K tag entries.
97
SE0
Input
Synchronous Chip Enable: Registered on the rising clock edge, active high.
98
SE1
Input
Synchronous Chip Enable: Registered on the rising clock edge, active low.
87
SW
Input
Synchronous Write: Registered on the rising clock edge, active low. The SW
input specifies whether a read or write cycle is to occur when the chip is
enabled. A write command should not be issued within three cycles of a read
command unless G is high or output drive contention may occur.
4, 11, 15, 20, 27, 41, 54,
61, 65, 70, 77, 91
VCC
Supply
Power Supply: 3.3 V + 10%, – 5%.
5, 10, 17, 21, 26, 38, 40,
55, 60, 67, 71, 76, 90
VSS
Supply
Ground.
1, 2, 3, 6, 7, 14, 16, 25,
28, 29, 30, 31, 49, 50, 51,
52, 53, 56, 57, 64, 66, 75,
78, 79, 83, 84, 85, 88, 92,
93, 94, 95, 96
NC
—
MCM69T618
4
Two cycles after a compare cycle and if MG is low, MATCH will be high if the
data presented to the DQ inputs matches the data stored in the RAM. MATCH
will be low if the data does not match.
No Connection: There is no connection to the chip.
MOTOROLA FAST SRAM
TRUTH TABLE (See Notes 1 through 4)
SE
SW
DE
MG
G
Match
DQ
Read
0
1
X
X
0
—
Data Out
Write
0
0
0
X
1
—
Data In
Compare
0
1
0
0
1
Data Out
Data In
Fill Write
0
0
1
X
1
—
High–Z
Deselected (Match Out)
1
X
X
0
X
Data High
High–Z
Deselected
1
X
X
1
X
High–Z
High–Z
Next Cycle
NOTES:
1. X = Don’t Care. 1 = logic high. 0 = logic low.
2. SE low is defined as SE1 = 0 and SE0 = 1. SE high is defined as SE1 = 1 or SE0 = 0.
3. G and MG are asynchronous signals and are not sampled by the clock K. G drives the bus immediately (tGLQX) when G goes low.
4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must
also remain negated at the completion of the write cycle to ensure proper write data hold times.
ABSOLUTE MAXIMUM RATINGS (See Note)
Symbol
Value
Unit
VCC
– 0.5 to + 4.6
V
Vin, Vout
VCC + 0.5
V
Output Current (per I/O)
Iout
± 20
mA
Package Power Dissipation
PD
1.6
W
Tbias
– 10 to + 85
°C
Tstg
– 55 to + 125
°C
Rating
Power Supply Voltage
Voltage Relative to VSS for Any
Pin Except VCC
Temperature Under Bias
Storage Temperature
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high–impedance
circuit.
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (See Note 1)
Symbol
Max
Unit
Notes
RθJA
40
25
°C/W
2
Junction to Board (Bottom)
RθJB
17
°C/W
3
Junction to Case (Top)
RθJC
9
°C/W
4
Rating
Junction to Ambient (@ 200 lfm)
Single–Layer Board
Four–Layer Board
NOTES:
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, board population, and board thermal resistance.
2. Per SEMI G38–87.
3. Indicates the average thermal resistance between the die and the printed circuit board.
4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1).
MOTOROLA FAST SRAM
MCM69T618
5
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 3.3 V + 10%, – 5%, TJ = 20 to 110°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS = 0 V)
Symbol
Min
Typ
Max
Unit
VCC
3.135
3.3
3.6
V
TJ
20
—
110
°C
Input Low Voltage
VIL
– 0.5*
—
0.8
V
Input High Voltage
VIH
2.0
—
VCC + 0.5**
V
Parameter
Supply Voltage
Operating Temperature
* VIL ≥ – 1.5 V for t ≤ tKHKH/2.
** VIH ≤ VCC + 1.0 V for t ≤ tKHKH/2.
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Input Leakage Current (0 V ≤ Vin ≤ VCC)
Ilkg(I)
—
—
±1
µA
Output Leakage Current (0 V ≤ Vin ≤ VCC)
Ilkg(O)
—
—
±1
µA
AC Supply Current (Device Selected, All Outputs Open,
All Inputs Toggling at Vin ≤ VIL or ≥ VIH
Cycle Time ≥ tKHKH min)
ICCA
—
—
240
mA
CMOS Standby Supply Current (Deselected,
Clock (K) Cycle Time ≥ tKHKH, All Inputs Toggling at CMOS
Levels Vin ≤ VSS + 0.2 V or ≥ VCC – 0.2 V)
ISB1
—
—
130
mA
1
Clock Running Supply Current (Deselected,
Clock (K) Cycle Time ≥ tKHKH,
All Other Inputs Held to Static CMOS Levels
Vin ≤ VSS + 0.2 V or ≥ VCC – 0.2 V)
ISB2
—
—
45
mA
1
Output Low Voltage (IOL = 8 mA)
VOL
—
—
0.4
V
Output High Voltage (IOH = – 4 mA)
VOH
2.4
—
—
V
NOTE:
1. Device in deselected mode as defined by the Truth Table.
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Symbol
Min
Typ
Max
Unit
Input Capacitance
Cin
—
3
5
pF
Input/Output Capacitance
CI/O
—
6
8
pF
Parameter
MCM69T618
6
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 3.3 V + 10%, – 5%, TJ = 20 to 110°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . See Figure 1 Unless Otherwise Noted
READ/WRITE CYCLE TIMING (See Notes 1, 2, and 3)
MCM69T618–5
Parameter
Symbol
Min
Max
Unit
Cycle Time
tKHKH
10
—
ns
Clock High Pulse Width
tKHKL
3.5
—
ns
Clock Low Pulse Width
tKLKH
3.5
—
ns
Clock High to Match Valid
tKHMV
—
5
ns
Clock Access Time
tKHQV
—
5
ns
4
Output Enable to Output Valid
tGLQV
—
5
ns
4
Match Output Enable to Match Valid
tMGLMV
—
5
ns
4
Clock High to Output Active
tKHQX1
0
—
ns
4, 5
Clock High to Output Change
tKHQX2
1.5
—
ns
4
Clock High to Match Output Change
tKHMX
1.5
—
ns
Output Enable to Output Active
tGLQX
0
—
ns
4, 5
tMGLMX
0
—
ns
4, 5
tGHQZ
—
5
ns
5, 6
tMGHMZ
—
5
ns
5
tKHQZ
1.5
5
ns
5, 6
Match Output Enable to Match Active
Output Disable to Q High–Z
Match Output Disable to Match High–Z
Clock High to Q High–Z
Setup Times:
Address
Data In
Write
Enable
tAVKH
tDVKH
tWVKH
tEVKH
2.5
—
ns
Hold Times:
Address
Data In
Write
Enable
tKHAX
tKHDX
tKHWX
tKHEX
0.5
—
ns
Notes
NOTES:
1. “Write” applies to the SW signal. “Enable” applies to SE0, SE1, and DE signals.
2. All read and write cycle timings are referenced from K or G.
3. G is a don’t care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle.
4. Tested per AC Test Load (See Figure 1).
5. This parameter is sampled and not 100% tested.
6. Measured at ± 200 mV from steady state.
OUTPUT
Z0 = 50 Ω
RL = 50 Ω
VT = 1.5 V
Figure 1. AC Test Loads
MOTOROLA FAST SRAM
MCM69T618
7
COMPARE/FILL WRITE CYCLES
t KHKH
tKHKL
tKLKH
K
tEVKH
tKHEX
tAVKH
tKHAX
SE*
SW
G
A
SA
B
B
tKHDX
tDVKH
DQ
D(A)
D(B)
tKHDEX
tDEVKH
DE
tMGLMV
MG
tKHMV
tMGLMX
tKHMX
MATCH HIGH WHEN CHIP DESELECTED
MATCH
HIT
MISS
FILL WRITE**
* SE low = SE0 high and SE1 low.
** During fill write sequence, tag entry is written with tag value retained in the data input register from the previous compare cycle.
MCM69T618
8
MOTOROLA FAST SRAM
READ/WRITE CYCLES
t KHKH
t KLKH
K
t KHKL
SA
t KHAX
tAVKH
A
B
C
D
E
F
G
H
SE*
tWVKH
tKHWX
SW
t KHQV
DQ
t KHDX
tDVKH
tKHQZ
Q(A)
t KHQX1
Q(C)
Q(B)
Q(D)
D(E)
D(F)
D(G)
D(H)
tKHQX2
DE
t GLQV
tGHQZ
G
READS
WRITES
* SE low = SE0 high and SE1 low.
ORDERING INFORMATION
(Order by Full Part Number)
MCM
69T618
XX
X
X
Motorola Memory Prefix
R = Tape and Reel, Blank = Tray
Part Number
Speed (5 = 5 ns)
Package (TQ = TQFP)
Full Part Numbers — MCM69T618TQ5
MCM69T618TQ5R
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
MOTOROLA FAST SRAM
MCM69T618
9
PACKAGE DIMENSIONS
TQ PACKAGE
TQFP
CASE 983A–01
4X
e
0.20 (0.008) H A–B D
2X 30 TIPS
e/2
0.20 (0.008) C A–B D
–D–
80
51
50
81
B
E/2
–A–
–X–
B
–B–
E1 E
X=A, B, OR D
VIEW Y
BASE
METAL
PLATING
31
100
1
c
30
D1/2
ÉÉÉÉ
ÇÇÇÇ
ÇÇÇÇ
ÉÉÉÉ
b1
E1/2
c1
b
D/2
D1
D
0.13 (0.005)
M
C A–B
S
D
S
SECTION B–B
2X 20 TIPS
0.20 (0.008) C A–B D
A
q
2
0.10 (0.004) C
–H–
–C–
SEATING
PLANE
q
3
VIEW AB
0.05 (0.002)
S
S
q
1
0.25 (0.010)
R2
A2
A1
L2
L
L1
R1
GAGE PLANE
q
VIEW AB
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –A–, –B– AND –D– TO BE DETERMINED
AT DATUM PLANE –H–.
5. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE –C–.
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS D1 AND B1 DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –H–.
7. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE b DIMENSION TO EXCEED 0.45
(0.018).
DIM
A
A1
A2
b
b1
c
c1
D
D1
E
E1
e
L
L1
L2
S
R1
R2
q
q
q
q
1
2
3
MILLIMETERS
MIN
MAX
–––
1.60
0.05
0.15
1.35
1.45
0.22
0.38
0.22
0.33
0.09
0.20
0.09
0.16
22.00 BSC
20.00 BSC
16.00 BSC
14.00 BSC
0.65 BSC
0.45
0.75
1.00 REF
0.50 REF
0.20
–––
0.08
–––
0.08
0.20
0_
7_
0_
–––
11 _
13 _
11 _
13 _
INCHES
MIN
MAX
–––
0.063
0.002
0.006
0.053
0.057
0.009
0.015
0.009
0.013
0.004
0.008
0.004
0.006
0.866 BSC
0.787 BSC
0.630 BSC
0.551 BSC
0.026 BSC
0.018
0.030
0.039 REF
0.020 REF
0.008
–––
0.003
–––
0.003
0.008
0_
7_
0_
–––
11 _
13 _
11 _
13 _
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MCM69T618
10
◊
MCM69T618/D
MOTOROLA FAST
SRAM