Freescale Semiconductor, Inc. MOTOROLA Document order number: MC33996 Rev 1.0, 01/2004 SEMICONDUCTOR TECHNICAL DATA Preliminary Information 33996 16-Output Switch with SPI Control Freescale Semiconductor, Inc... The 33996 is a 16-output low-side switch with a 24-bit serial input control. It is designed for a variety of applications including inductive, incandescent, and LED loads. The Serial Peripheral Interface (SPI) provides both input control and diagnostic readout. A Pulse Width Modulation (PWM) control input is provided for pulse width modulation of multiple outputs at the same duty cycle. A dedicated reset input provides the ability to clear all internal registers and turn all outputs off. DUAL OCTAL SERIAL SWITCH WITH SERIAL PERIPHERAL INTERFACE I/O The 33996 directly interfaces with microcontrollers and is compatible with both 3.3 V and 5.0 V CMOS logic levels. The 33996, in effect, serves as a bus expander and buffer with fault management features that reduce the MCU’s fault management burden. Features • Designed to Operate 5.0 V < VPWR < 27 V • 24-Bit SPI for Control and Fault Reporting, 3.3 V/5.0 V Compatible • Outputs Are Current Limited (0.9 A to 2.5 A) to Drive Incandescent Lamps • Output Voltage Clamp of +50 V During Inductive Switching • On/Off Control of Open Load Detect Current (LED Application) • VPWR Standby Current < 10 µA EK (Pb-FREE) SUFFIX CASE 1454-01 32-LEAD SOICW EXPOSED PAD ORDERING INFORMATION • RDS(ON) of 0.55 Ω at 25°C Typical • • • • • Independent Overtemperature Protection Output Selectable for PWM Control Output ON Short-to-VBAT and OFF Short-to-Ground/Open Detection 32-Pin Exposed Pad Package for Thermal Performance Pb-Free Packaging Designated by Suffix Code EK Device Temperature Range (TA) Package PC33996EK/R2 -40°C to 125°C 32 SOICW-EP Simplified Application Diagram 33996 Simplified Application Diagram VPWR 3.3 V/5.0 V VBAT 33996 VDD SOPWR VPWR SCLK CS SI SO PWM RST OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 OUT15 MCU SCLK CS MISO MOSI PWM RST Solenoid/Relay LED Lamp GND This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. © Motorola, Inc. 2004 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. VPWR VDD Freescale Semiconductor, Inc... PWM 30 10 µA RST 27 25 µA CS 14 10 µA SCLK 11 SI 19 SO 22 SOPWR 3 Input Buffers 10 µA 10 µA Serial D/O Line Driver Overvoltage Detect 6 Voltage Regulator GE OT SF OF OVD VDD RB SFPDB SFL SCLK CSB SI SO CSI CSBI Open Load Detect Enable SPI Interface Logic OUT0 1 VDD Bias 50 V Gate Control OUT1–OUT15: 2, 4, 5, 12, 13, 15, 16, 17, 18, 20, 21, 28, 29, 31, 32 To Gates 1to15 VRef ILimit 50 µA Short and Open Load Detect RS GND Pins: 7–10 23– 26 Overtemperature Detect From Detectors 1to15 Figure 1. 33996 Simplified Internal Block Diagram 33996 2 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 1 32 2 31 3 30 4 29 5 28 OUT15 OUT14 PWM OUT13 OUT12 6 27 RST 7 26 8 25 9 24 10 23 11 22 12 21 13 20 CS 14 19 OUT6 OUT7 15 18 16 17 GND GND GND GND SO OUT11 OUT10 SI OUT9 OUT8 Freescale Semiconductor, Inc... OUT0 OUT1 SOPWR OUT2 OUT3 VPWR GND GND GND GND SCLK OUT4 OUT5 PIN FUNCTION DESCRIPTION Pin Pin Name Formal Name 1, 2, 4, 5, 12, 13, 15–18, 20, 21, 28, 29, 31, 32 OUT0–OUT15 Output 0–Output 15 Open drain output pin. 3 SOPWR SOPWR Supply Pin Power supply pin to the SO output driver. 6 VPWR Battery Input 7–10, 23–26 GND Ground Ground for logic, analog, and power output devices. 11 SCLK System Clock System Clock for internal shift registers of the 33996. 14 CS Chip Select SPI control chip select input pin from the MCU to the 33996. 19 SI Serial Input Serial data input pin to the 33996. 22 SO Serial Output 27 RST Reset 30 PWM PWM Control MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Definition Battery supply input pin. Serial data output pin. Active low reset input pin. PWM control input pin. Supports PWM on any combination of outputs. For More Information On This Product, Go to: www.freescale.com 33996 3 Freescale Semiconductor, Inc. MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted. Rating Symbol Value Unit VPWR -1.5 to 50 V SOPWR -0.3 to 7.0 V SPI Interface Logic Input Voltage (CS, PWM, SI, SO, SCLK, RST) (Note 1) VIN -0.3 to 7.0 V Output Drain Voltage VD -0.3 to 45 V Frequency of SPI Operation (Note 2) fSPI 6.0 MHz ECLAMP 50 mJ VESD1 VESD2 ±2000 ±200 TSTG -50 to 150 °C Operating Case Temperature TC -40 to 125 °C Operating Junction Temperature TJ -40 to 150 °C Power Dissipation (TA = 25°C) (Note 7) PD 1.5 W TSOLDER 260 °C Junction-to-Ambient (Note 9) RθJA 75 Junction- to-Lead (Note 10) RθJL 8.0 Junction-to-Flag RθJC 1.2 VPWR Supply Voltage (Note 1) SO Output Driver Power Supply Voltage (Note 1) Output Clamp Energy (Note 3) V Freescale Semiconductor, Inc... ESD Voltage (Note 4) Human Body Model (Note 5) Machine Model (Note 6) Storage Temperature Lead Soldering Temperature (Note 8) °C/W Thermal Resistance Notes 1. 2. 3. 4. 5. Exceeding these limits may cause malfunction or permanent damage to the device. This parameter is guaranteed by design but not production tested. Maximum output clamp energy capability at 150°C junction temperature using single nonrepetitive pulse method. ESD data available upon request. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω). 6. ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω). 7. 8. Maximum power dissipation with no heat sink used. Lead soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Tested per JEDEC test JESD52-2 (single-layer PWB). Tested per JEDEC test JESD51-8 (two-layer PWB). 9. 10. 33996 4 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 3.1 V ≤ SOPWR ≤ 5.5 V, 5.0 V ≤ VPWR ≤ 18 V, -40°C ≤ TC ≤ 125°C unless otherwise noted. Where applicable, typical values noted reflect the parameter ‘s approximate value with VPWR = 13 V, TA = 25°C. Characteristic Symbol Min Typ Max Unit 5.0 – 27 – 4.0 8.0 IPWR(SS) -10 1.0 10 µA VOV 27.5 31.5 35 V Overvoltage Shutdown Hysteresis VOV(HYS) 0.8 1.4 2.3 V VPWR Undervoltage Shutdown VPWR(UV) – 3.2 3.5 V SOPWR 3.1 – 5.5 V SPI Interface Logic Supply Current (RST Pin High) ISOPWR(RSTH) 100 – 500 µA SPI Interface Logic Supply Current (RST Pin Low) ISOPWR(RSTL) -10 – 10 µA SOPWR(UNVOL) 2.0 2.5 3.0 V POWER SUPPLY VPWR(FO) Supply Voltage Range Fully Operational mA IPWR(ON) Supply Current All Outputs ON, IOUT = 0.3 A Sleep State Supply Current at RST ≤ 0.2 SOPWR and/or SOPWR ≤ 0.5 V Freescale Semiconductor, Inc... V Overvoltage Shutdown SPI Interface Logic Supply Voltage SPI Interface Logic Supply Undervoltage Lockout Threshold POWER OUTPUT Drain-to-Source ON Resistance (IOUT = 0.35 A, VPWR = 13 V) Ω RDS(ON) TJ = 125°C – 0.75 1.2 TJ = 25°C – 0.55 1.2 TJ = -40°C – 0.45 1.2 Output Self-Limiting Current A I OUT(lim) 0.9 Outputs Programmed ON Output Fault Detect Threshold (Note 11) 1.2 2.5 V VOUTth(F) 2.5 3.0 3.5 I OCO(5) 25 50 100 I OCO(13,18) 30 50 100 45 50 55 -10 2.0 10 TLIM 155 165 180 °C TLIM(hys) 5.0 10 20 °C Outputs Programmed OFF µA Output Off Open Load Detect Current (Note 12) Outputs Programmed OFF (VPWR = 5.0 V) Outputs Programmed OFF (VPWR = 13 V, 18 V) Output Clamp Voltage V VCL IOUT = 20 ≤ mA Output Leakage Current µA IOUT(lkg) SOPWR ≤ 2.0 V Overtemperature Shutdown (Outputs OFF) (Note 13) Overtemperature Shutdown Hysteresis (Note 13) Notes 11. Output Fault Detect Thresholds with outputs programmed OFF. Output Fault Detect Thresholds are the same for output open and shorts. 12. Output OFF Open Load Detect Current is the current required to flow through the load for the purpose of detecting the existence of an open load condition when the specific output is commanded to be OFF. 13. This parameter is guaranteed by design but not production tested. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33996 5 Freescale Semiconductor, Inc. STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 3.1 V ≤ SOPWR ≤ 5.5 V, 5.0 V ≤ VPWR ≤ 18 V, -40°C ≤ TC ≤ 125°C unless otherwise noted. Where applicable, typical values noted reflect the parameter ‘s approximate value with VPWR = 13 V, TA = 25°C. Characteristic Symbol Min Typ Max Unit VINLOGIC 0.8 – 2.2 V VINRST SOPWR / 2 -0.7 SOPWR /2 SOPWR / 2+0.7 V 2.0 10 30 -30 -10 -2.0 2.0 10 30 DIGITAL INTERFACE Input Logic Voltage Thresholds (Note 14) Input Logic Voltage Thresholds for RST SI Pull-Down Current µA I SI SI = 5.0 V µA I CS CS Pull-Up Current Freescale Semiconductor, Inc... CS = 0 V SCLK Pull-Down Current µA I SCLK SCLK = 5.0 V RST Pull-Down Current µA I RST 5.0 25 50 2.0 10 30 SOPWR - 0.4 SOPWR - 0.2 – – – 0.4 – – 20 RST = 5.0 V PWM Pull-Down Current I PWM SO High State Output Voltage VSOH ISO-high = -1.6 mA SO Low State Output Voltage V V VSOL ISO-low = 1.6 mA Input Capacitance on SCLK, SI, Tri-State SO, RST (Note 15) µA CIN pF Notes 14. Upper and lower logic threshold voltage levels apply to SI, CS, SCLK, and PWM. 15. This parameter is guaranteed by design but not production tested. 33996 6 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions of 3.1 V ≤ SOPWR ≤ 5.5 V, 5.0 V ≤ VPWR ≤ 18 V, -40°C ≤ TC ≤ 125°C unless otherwise noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C. Characteristic Symbol Min Typ Max 1.0 2.0 10 Unit POWER OUTPUT TIMING Output Slew Rate SR Freescale Semiconductor, Inc... RL = 56 Ω (Note 16) V/µs Output Turn ON Delay Time (Note 17) tDLY (on) 1.0 15 50 µs Output Turn OFF Delay Time (Note 17) t DLY(off) 1.0 15 50 µs Output ON Short Fault Disable Report Delay (Note 18) tDLY (short) 100 – 450 µs Output OFF Open Fault Delay Time (Note 18) t DLY(open) 100 – 450 µs t FREQ – – 2.0 kHz – – 10 100 – – 50 – – 16 – – Output PWM Frequency DIGITAL INTERFACE TIMING Required Low State Duration on VPWR for Reset Falling Edge of CS to Rising Edge of SCLK ns t LAG Required Setup Time SI to Falling Edge of SCLK ns t LEAD Required Setup Time Falling Edge of SCLK to Rising Edge of CS µs t RST VPWR ≤ 0.2 V (Note 19) t SI (su) Required Setup Time Falling Edge of SCLK to SI ns t SI (hold) Required Hold Time ns 20 – – SI, CS, SCLK Signal Rise Time (Note 20) t R (SI) – 5.0 – ns SI, CS, SCLK Signal Fall Time (Note 20) t F (SI) – 5.0 – ns Time from Falling Edge of CS to SO Low Impedance (Note 21) t SO (en) – – 50 ns Time from Rising Edge of CS to SO High Impedance (Note 22) t SO (dis) – – 50 ns Time from Rising Edge of SCLK to SO Data Valid (Note 23) t VALID – 25 80 ns Notes 16. 17. 18. 19. 20. 21. 22. 23. Output slew rate measured across a 56 Ω resistive load. Output turn ON and OFF delay time measured from 50% rising edge of CS to 90% and 10% of initial voltage. Duration of fault before fault bit is set. Duration between access times must be greater than 450 µs to read faults. This parameter is guaranteed by design; however, it is not production tested. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. Time required for valid output status data to be available on SO pin. Time required for output states data to be terminated at SO pin. Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33996 7 Freescale Semiconductor, Inc. Timing Diagram CS 0.2 VDD t LAG t LEAD 0.7 VDD SCLK 0.2 VDD tSI(su) 0.7 VDD 0.2 VDD SI tSI(hold) MSB IN Freescale Semiconductor, Inc... tSO(en) SO t SO(dis) t VALID 0.7 VDD Don't 0.2 VDD Care MSB OUT LSB OUT VTri-State Figure 2. SPI Timing Characteristics 33996 8 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. SYSTEM/APPLICATION INFORMATION INTRODUCTION The 33996 is designed and developed for automotive and industrial applications. It is a 16-output power switch having 24-bit serial control. The 33996 incorporates SMARTMOS technology having CMOS logic, bipolar/MOS analog circuitry, and independent DMOS power output transistors. Many benefits are realized as a direct result of using this mixed technology. A simplified internal block diagram of the 33996 is shown in Figure 1, page 2. Freescale Semiconductor, Inc... MCU INTERFACE DESCRIPTION In operation the 33996 functions as a 16-output serial switch serving as a microcontroller (MCU) bus expander and buffer with fault management and fault reporting features. In doing so, the device directly relieves the MCU of the fault management functions. The 33996 directly interfaces to an MCU and operates at system clock serial frequencies up to 6.0 MHz using a Serial Peripheral Interface (SPI) for control and diagnostic readout. Figure 3 shows the basic SPI configuration between an MCU and one 33996. MC68HCXX Microcontroller 33996 MOSI Shift Register MISO SI SO 24-Bit Shift Register The 33996 may be controlled and provide diagnostics using a daisy chain configuration or in parallel mode. Figure 4 shows the daisy chain configuration using the 33996. Data from the MCU is clocked daisy chain through each device while the Chip Select bit (CS) is commanded low by the MCU. During each clock cycle, output status from the daisy-chained 33996s is being transferred back to the MCU via the Master In Slave Out (MISO) line. On rising edge of CS, data stored in the input register is transferred to the output driver. Daisy chain control of the 33996 requires 24 bits per device. Multiple 33996 devices can be controlled in a parallel input fashion using the SPI. Figure 5, page 10, illustrates potentially 32 loads being controlled by two dedicated parallel MCU ports used for chip select. MC68HCXX Microcontroller 33996 MOSI Shift Register SCLK MISO Receive Buffer SCLK To Logic RST Parallel Ports CS PWM Parallel Ports PWM1 PWM2 SI SO SCLK CS PWM RST 33996 Figure 3. 33996 SPI Interface with Microcontroller All inputs are compatible with 3.3 V/5.0 V CMOS logic levels and incorporate positive logic. An input that is programmed to a logic low state (< 0.8 V) will have the corresponding output OFF. Conversely, an input programmed to a logic high state (> 2.2 V) will have the output being controlled ON. Diagnostics is treated in a similar manner—outputs with a fault will feedback (via SO) to the MCU a logic [1], while normal operating outputs will provide a logic [0]. SI SO SCLK CS PWM RST Figure 4. 33996 SPI System Daisy Chain MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33996 9 Freescale Semiconductor, Inc. MC68HCXX Microcontroller 33996 MOSI Shift Register MISO SCLK Parallel Ports PWM1 SI SO SCLK CS PWM PWM2 Freescale Semiconductor, Inc... RST 33996 SI SO SCLK CS PWM RST Figure 5. Parallel Inputs SPI Control FUNCTIONAL PIN DESCRIPTION Chip Select (CS) Pin The system MCU selects the 33996 to be communicated with through the use of the Chip Select (CS) pin. When the CS pin is in a logic low state, data can be transferred from the MCU to the 33996 and vise versa. Clocked-in data from the MCU is transferred from the 33996 Shift register and latched into the power outputs on the rising edge of the CS signal. On the falling edge of the CS signal, output fault status information is transferred from the Power Outputs Status register into the device’s SO Shift register. The SO pin output driver is enabled when CS is low, allowing information to be transferred from the 33996 to the MCU. To avoid any spurious data, it is essential the high-to-low transition of the CS signal occur only when SCLK is in a logic low state. System Clock (SCLK) Pin The System Clock (SCLK) pin clocks the Internal Shift registers of the 33996. The Serial Input (SI) pin accepts data into the Input Shift register on the falling edge of the SCLK signal, while the Serial Output (SO) pin shifts data information out of the Shift register on the rising edge of the SCLK signal. False clocking of the Shift register must be avoided, ensuring validity of data. It is essential that the SCLK pin be in a logic low state whenever the CS pin makes any transition. For this reason, it is recommended, though not necessary, that the SCLK pin is commanded to a low logic state as long as the 33996 10 device is not accessed (CS in logic high state). When the CS is in a logic high state, any signal at the SCLK and SI pins is ignored and the SO is tri-stated (high impedance). Serial Input (SI) Pin The Serial Input (SI) pin is used to enter one of seven serial instructions into the 33996. SI SPI bits are latched into the Input Shift register on each falling edge of SCLK. The Shift register is full after 24 bits of information are entered. The 33996 operates on the command word on the rising edge of CS. To preserve data integrity, exercise care not to transition SI as SCLK transitions from high to low state (see Figure 2, page 8). Serial Output (SO) Pin The Serial Output (SO) pin transfers fault status data from the 33996 to the MCU. The SO pin remains tri-state until the CS pin transitions to a logic low state. All faults on the 33996 are reported to the MCU as logic [1]. Conversely, normal operating outputs with nonfaulted loads are reported as logic [0]. On the falling edge of the CS signal, output fault status information is transferred from the Power Outputs Status register into the device’s SO Shift register. The first eight positive transitions of SCLK will provide Any Fault (bit 23), Overvoltage Fault (bit 22), followed by six logic [0]s (bits 21 to 16). The next 16 successive positive transitions of SCLK provides fault status for output 15 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Battery Input (VPWR) Pin to output 0. Refer to the LOGIC OPERATION section (below) for more information. The SI/SO shifting of data follows a firstin, first-out protocol, with both input and output words transferring the Most Significant Bit (MSB) first. The VPWR pin is used as the input power source for the 33996. The voltage on VPWR is monitored for overvoltage protection and shutdown. An overvoltage condition (> 50 µs) on the VPWR pin will cause the 33996 to shut down all outputs until the overvoltage condition is removed. Upon return to normal input voltage, the outputs will respond as programmed by the overvoltage bit in the Global Shutdown/Retry Control register. The overvoltage threshold on the VPWR pin is specified as 27.5 V to 35 V with 1.4 V typical hysteresis. Following an overvoltage shutdown of output drivers, the Overvoltage Fault and the Any Fault bits in the SO bit stream will be logic [1]. SO Output Driver Power Supply (SOPWR) Pin The SOPWR pin is used to supply power to the 33996 SO output driver and Power-ON Reset (POR) circuit. To achieve low standby current on VPWR supply, power must be removed from the SOPWR pin. The 33996 will be in reset with all drivers OFF when SOPWR is below 2.5 V. The 33996 does not detect overvoltage on the SOPWR supply pin. Freescale Semiconductor, Inc... Output/Input (OUT0–OUT15) Pins PWM Pin These pins are low-side output switches controlling the load. The PWM Control pin is provided to support PWM of any combination of outputs. The LOGIC OPERATION section describes the logic for PWM control. Reset (RST) Pin The Reset (RST) pin is the active low reset input pin used to turn OFF all outputs, thereby clearing all internal registers. LOGIC OPERATION Introduction The 33996 message set consists of seven messages as shown in Table 1. Bits 23 through18 determine the specific command and bits 15 through 0 determine how a specific output will operate. The 33996 operates on the command word on the rising edge of CS. The 33996 provides flexible control of 16 low-side driver outputs. The device allows PWM and ON/OFF control through the use of several 24-bit input command words. This section describes the logic operation and command registers of the 33996. Note Upon Power-ON Reset all bits are defined as shown in Table 1. Table 1. SPI Control Commands Bits MSB Commands LSB 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ON/OFF Control 0=off, 1=on 0 0 0 0 0 0 X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Open Load Current Enable 0=disable, 1=enable 0 0 0 0 0 1 X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Global Shutdown/Retry Control 0=shutdown, 1=retry 0 0 0 0 1 0 Thermal Bit 0 Overvoltage X X X X X X X X X X X X X X X X SFPD Control 1=therm only, 0=VDS 0 0 0 0 1 1 X X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PWM Enable 0=SPI only, 1=PWM 0 0 0 1 0 0 X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AND/OR Control 0=PWM pin AND with SPI 1=PWM pin OR with SPI 0 0 0 1 0 1 X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 X X X X X X X X X X X X X X X X X X Reset SO Response 0=No Fault, 1=Fault Any OverFault voltage 0 0 0 0 0 0 0 ON/Off Control Register To program the 16 outputs of the 33996 ON or OFF, a 24-bit serial stream of data is entered into the SI pin. The first 8 bits of the control word are used to identify the on/off command and MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 the remaining 16 bits are used to turn ON or OFF the specific output driver. For More Information On This Product, Go to: www.freescale.com 33996 11 Freescale Semiconductor, Inc. Open Load Current Enable Control Register AND/OR Control Register The Open Load Current Enable Control register is provided to enable or disable the 50 µA open load detect pull-down current. This feature allows the device to be used in LED applications. Power-ON Reset (POR) or the RST pin or the RESET command disables the 50 µA pull-down current. No open load fault will be reported with the pull-down current disabled. For open load to be active, the user must program the Open Load Current Enable Control register with logic [1]. The AND/OR Control register describes the condition by which the PWM pin controls the output driver. A logic [0] in the AND/OR Control register will AND the PWM input pin with the ON/OFF Control register bit. Likewise, a logic [1] in the AND/ OR Control register will OR the PWM input pin with the ON/OFF Control register bit (see Figure 6). For the AND/OR control to occur, the PWM Enable bit must be set to logic [1]. On/Off Control Bit Freescale Semiconductor, Inc... Global Shutdown/Retry Control Register The Global Shutdown/Retry Control register allows the user to select the global fault strategy for the outputs. The overvoltage control bit (bit 16) sets the operation of the outputs when returning from overvoltage. Setting the overvoltage bit to logic [0] will force all outputs to remain off when VPWR returns to normal level. Setting the overvoltage bit to logic [1] will command outputs to resume their previous state when VPWR returns to normal level. Bit 17 is the global thermal bit. When bit 17 is set to logic [0], all outputs will shut down when thermal limit is reached and remain off even after cooled. With bit 17 set to logic [1], all outputs will shut down when thermal limit is reached and will retry when cooled. Short Fault Protect Disable (SFPD) Control Register All outputs contain current limit and thermal shutdown with programmable retry. The SFPD control bits are used for fast shutdown of the output when overcurrent condition is detected but thermal shutdown has not been achieved. The SFPD Control register allows the user to select specific outputs for incandescent lamp loads and specific outputs for inductive loads. By programming the specific SFPD bit as logic [1], output will rely on overtemperature shutdown only. Programming the specific SFPD bit as logic [0] will shut down the output after 100 µs to 450 µs during turn on into short circuit. The decision for shutdown is based on output drain-tosource voltage (VDS ) > 2.7 V. This feature is designed to provide protection to loads that experience more than expected currents and require fast shutdown. The 33996 is designed to operate in both modes with full device protection. On/Off Control Bit PWM Enable Bit PWM IN To Gate Control AND/OR Control Bit On/Off control Bit PWM IN Figure 6. PWM Control Logic Diagram Serial Output (SO) Response Register Fault reporting is accomplished through the SPI interface. All logic [1s] received by the MCU via the SO pin indicate fault. All logic [0s] received by the MCU via the SO pin indicate no fault. All fault bits are cleared on the positive edge of CS. SO bits 15 to 0 represent the fault status of outputs 15 to 0. SO bits 21 to 16 will always return logic [0]. Bit 22 provides overvoltage condition status and bit 23 is set when any fault is present in the IC. The timing between two write words must be greater than 450 µs to allow adequate time to sense and report the proper fault status. RESET Command The RESET command turns all outputs OFF and sets all internal registers to their Power-ON Reset state (refer to Table 1). PWM Enable Register The PWM Enable register determines the outputs that are PWM controlled. The first 8 bits of the 24 bit SPI message word are used to identify the PWM enable command, and the remaining 16 bits are used to enable and disable the PWM of the output drivers. A logic [0] in the PWM Enable register will disable the outputs as PWM. A logic [1] in the PWM Enable register will set the specific output as a PWM. Power-ON Reset or the RST pin or the RESET command will set the PWM Enable register to logic [0]. 33996 12 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. FAULT OPERATION On each SPI communication, a 24-bit command word is sent to the 33996 and 24-bit fault word is received from the 33996. The Most Significant Bit (MSB) is sent and received first. Command Register Definition: 0 = Output Command Off 1 = Output Command On SO Definition: 0 = No fault 1 = Fault Table 2. Fault Operation Freescale Semiconductor, Inc... Serial Output (SO) Pins Reports Overtemperature Fault reported by Serial Output (SO) pin. Overcurrent SO pin reports short to battery/supply or overcurrent condition. Output “ON’ Open Load Fault Not reported. Output “OFF’” Open Load Fault SO pin reports output “OFF’” open load condition. Device Shutdowns Overvoltage Total device shutdown at VPWR = 27.5 V to 35 V. Resumes normal operation with proper voltage. Upon recovery all outputs assume previous state or OFF based on the Overvoltage bit in the Global Shutdown/ Retry Control Register. Overtemperature Only the output experiencing an overtemperature fault shuts down. Output may auto-retry or remain off according to the control bits in the Global Shutdown/Retry Control Register. Overcurrent Output will remain in current limit 0.9 A to 2.5 A until thermal limit is reached. When thermal limit is reached, device will enter overtemperature shutdown. Output will operate as programmed in the Global Shutdown/ Retry Control Register. Fault flag in SO Response word will be set. APPLICATIONS Power Consumption The 33996 has been designed with one Sleep mode and one Operational mode. In Sleep mode (SOPWR ≤ 2.0 V) the current consumed by the VPWR pin is less than 10 µA. To place the 33996 in Sleep mode, turn all outputs OFF and remove power from the SOPWR pin. During normal operation, 500 µA is drawn from the SOPWR supply and 8.0 mA from the VPWR supply. Paralleling of Outputs Using MOSFETs as output switches allows the connection of any combination of outputs together. The RDS(ON) of MOSFETs has an inherent positive temperature coefficient, providing balanced current sharing between outputs without destructive operation. This mode of operation may be desirable in the event the application requires lower power dissipation or the added capability of switching higher currents. Performance of parallel operation results in a corresponding decrease in RDS(ON), while the Output Current Limit increases correspondingly. Output OFF Open Load Detect current may increase based on how the Output OFF Open Load Detect is programmed. Paralleling outputs from two or more different IC devices is possible but not recommended. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Care must be taken when paralleling outputs for inductive loads. The Output Voltage Clamp of the output drivers may not match. One MOSFET output must be capable of the inductive energy from the load turn OFF. SPI Integrity Check Checking the integrity of the SPI communication is recommended upon initial power-up of the SOPWR pin. After initial system start-up or reset, the MCU writes one 48-bit pattern to the 33996. The first 24 bits read by the MCU is the fault status of the outputs, while the second 24 bits is the first bit pattern sent. By the MCU receiving the same bit pattern it sent, bus integrity is confirmed. Please note the second 24 bits the MCU sends to the 33996 are the command bits and will program registers or activate outputs on the rising edge of CS. Output OFF Open Load Fault An Output OFF Open Load Fault is the detection and reporting of an open load when the corresponding output is disabled (input bit programmed to a logic low state). The Output OFF Open Load Fault is detected by comparing the drain-to- For More Information On This Product, Go to: www.freescale.com 33996 13 Freescale Semiconductor, Inc. source voltage of the specific MOSFET output to an internally generated reference. Each output has one dedicated comparator for this purpose. Freescale Semiconductor, Inc... Each 33996 output has an internal 50 µA pull-down current source. The pull-down current is disabled on power-up and must be enabled for Open Load Detect to function. Once enabled, the 33996 will only shut down the pull-down current in Sleep mode or when disabled via SPI. During output switching, especially with capacitive loads, a false Output OFF Open Load Fault may be triggered. To prevent this false fault from being reported, an internal fault filter of 100 µs to 450 µs is incorporated. The duration for which a false fault may be reported is a function of the load impedance, RDS(ON), COUT of the MOSFET, as well as the supply voltage, VPWR. The rising edge of CS triggers the built-in fault delay timer. The timer must time out before the fault comparator is enabled to detect a faulted threshold. Once the condition causing the Open Load Fault is removed, the device resumes normal operation. The Open Load Fault, however, will be latched in the output SO Response register for the MCU to read. Shorted Load Fault A shorted load (overcurrent) fault can be caused by any output being shorted directly to supply, or by an output experiencing a current greater than the current limit. Three safety circuits progressively in operation during load short conditions afford system protection: 1. The device’s output current is monitored in an analog fashion using a SENSEFET approach and is current limited. 2. With the output in current limit, the drain-to-source voltage will increase. By setting the SFPD bit to 0, the output will shut down on VDS > 2.7 V typical after 450 µs. 3. The device’s output thermal limit is sensed and when attained causes only the specific faulted output to shutdown. The device remains OFF until cooled. The device then operates as programmed by the shutdown/ retry bit. The cycle continues until the fault is removed or the command bit instructs the output OFF. All three protection schemes set the Fault Status bit (bit 23 in the SO Response register) to logic [1]. Undervoltage Shutdown An undervoltage SOPWR condition results in the global shutdown of all outputs and reset of all control registers. The undervoltage threshold is between 2.0 V and 3.0 V. Output Voltage Clamp Each output of the 33996 incorporates an internal voltage clamp to provide fast turn-OFF and transient protection of each output. Each clamp independently limits the drain-to-source voltage to 50 V. The total energy clamped (EJ) can be calculated by multiplying the current area under the current curve (IA) times the clamp voltage (VCL) (see Figure 7). Characterization of the output clamps, using a single pulse non-repetitive method at 0.3 A, indicates the maximum energy to be 50 mJ at 150°C junction temperature per output. Drain-to-Source C lamp Drain-to-Source Voltage (V CL =Clamp 45 50 V) V) Voltage (VCL = 50 V) Drain DrainVoltage Voltage Clamp Energy Clamp Energy (E(E J = I= A Ix V x CL V) ) DrainCurrent Current Drain 0.3A) A) (I(IDD==0.3 Drain-to-Source ON Drain-to-Source ON Voltage (V (O N) ) Voltage (VDS DS(ON)) GND GND J A Curren t Area (IA ) CL Time Time Figure 7. Output Voltage Clamping Reverse Battery Protection The 33996 device requires external reverse battery protection on the VPWR pin. All outputs consist of a power MOSFET with an integral substrate diode. During reverse battery condition, current will flow through the load via the substrate diode. Under this circumstance relays may energize and lamps will turn on. If load reverse battery protection is desired, a diode must be placed in series with the load. Overtemperature Fault Overtemperature detect circuits are specifically incorporated for each individual output. The shutdown following an overtemperature condition depends on the control bit set in the Global Shutdown/Retry Control register. Each independent output shuts down at 155°C to 180°C. When an output shuts down due to an Overtemperature Fault, no other outputs are affected. The MCU recognizes the fault by a logic [1] in the Fault Status bit (bit 23 in the SO Response register). After the 33996 has cooled below the switch point temperature and 10°C hysteresis, the output will function as defined by the shutdown/ retry bit 17 in the Global Shutdown/Retry Control register. An undervoltage condition at the VPWR pin results in an output shutdown and reset. The undervoltage threshold is between 3.2 V and 3.5 V. When VPWR is between 5.0 V and 3.5 V, the output may operate per the command word and the status is reported on SO pin, though this is not guaranteed. 33996 14 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. PACKAGE DIMENSIONS EK (Pb-FREE) SUFFIX 32-LEAD SOICW EXPOSED PAD PLASTIC PACKAGE CASE 1454-01 ISSUE O 10.3 7.6 7.4 C 5 Freescale Semiconductor, Inc... 1 B 2.65 2.35 9 30X 32 0.65 PIN 1 ID 4 B 9 B 16 11.1 10.9 CL 17 32X 2X 16 TIPS 0.3 SEATING PLANE A 5.15 0.10 A A B C (0.29) 0.25 0.19 0.3 4.96 4.44 (0.203) 6 A B C BASE METAL 0.13 0.38 0.22 M C A PLATING M B 8 SECTION A-A ROTATED 90 ° CLOCKWISE 4.96 4.44 0.3 A B C NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DATUMS B AND C TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15 mm PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25 mm PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 6. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.4 mm PER SIDE. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT LESS THAN 0.07 mm. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 mm AND 0.3 mm FROM THE LEAD TIP. 9. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. THIS DIMENSION IS DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTER-LEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. R0.08 MIN 0.25 GAUGE PLANE 8° 0° VIEW C-C MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 0° MIN 0.29 0.13 0.9 0.5 SECTION B-B 33996 15 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. 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All other product or service names are the property of their respective owners. © Motorola, Inc. 2004 HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1-800-521-6274 or 480-768-2130 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center 3-20-1 Minami-Azabu. Minato-ku, Tokyo 106-8573, Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 HOME PAGE: http://motorola.com/semiconductors For More Information On This Product, Go to: www.freescale.com MC33996