MOTOROLA PC34710EWR2

Freescale Semiconductor, Inc.
MOTOROLA
Document order number: MC34710
Rev 1.0, 04/2004
SEMICONDUCTOR TECHNICAL DATA
Preliminary Information
34710
Adjustable Dual Output Switching
Power Supply
Freescale Semiconductor, Inc...
The 34710 is a dual-output power regulator IC that integrates a switching
regulator, a linear regulator, supervisor circuitry, and a power supply
sequencer. With a wide operating input voltage range of 12 V to 32 V and
robust temperature limits, the 34710 is applicable in many commercial and
industrial applications that use an MCU.
ADJUSTABLE DUAL OUTPUT
SWITCHING POWER SUPPLY
A user-selectable 5.0 V/3.3 V buck switching regulator is provided for
board-level I/Os and user circuitry. The regulator is capable of delivering up to
1.0 A. The MCU core voltage is an adjustable 3.3 V/2.5 V/1.8 V/1.5 V linear
voltage regulator that can supply up to 500 mA.
The switching and linear regulator output voltage are determined through
three digital input mode terminals that can be controlled by an MCU.
Features
• High-Current Adjustable 5.0 V/3.3 V Switching Regulator
• Low Noise User-Selectable 3.3 V/2.5 V/1.8 V/1.5 V Linear Regulator
• On-Chip Thermal Shutdown and Error Reset Circuitry
• Supervisory Functions (Power-ON Reset and Error Reset Circuitry)
• Sequenced I/O and Core Voltages
• Pb-Free Packaging Designated by Suffix Code EW
EW (Pb-FREE) SUFFIX
CASE 1324-02
32-LEAD SOICW-EP
ORDERING INFORMATION
Device
Temperature
Range (TA)
Package
PC34710EW/R2
0°C to 85°C
32 SOICW-EP
Simplified Application Diagram
34710 Simplified Application Diagram
12 V to 32 V
34710
B+
Vb
VSWITCH
CP2
VI/O
VI/O_OUT
CP1
Mode0
Mode1
Mode2
MCU
LINB+
RST
VCORE
VCORE
GND
This document contains information on a product under development.
Motorola reserves the right to change or discontinue this product without notice.
© Motorola, Inc. 2004
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B+
2000 Hz
Oscillator
Charge
Pump
Freescale Semiconductor, Inc...
Supervisory and
Temperature
Shutdown
CP1
CP2
Vb
RST
Ct
Bandgap
MODE0
MODE1
MODE2
LINB+
VI/O
Switching
Regulator
VCORE
Linear
Regulator
VI/O_OUT
VSWITCH
VCORE (2)
GND
Figure 1. 34710 Simplified Internal Block Diagram
34710
2
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RST
MODE0
MODE1
MODE2
NC
NC
NC
NC
NC
NC
NC
NC
GND
NC
NC
NC
1
32
2
31
3
30
4
29
5
28
6
27
7
26
8
25
9
24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
Ct
CP1
CP2
Vb
B+
VSWITCH
VI/O_OUT
LINB+
VCORE
VCORE
NC
NC
NC
NC
NC
NC
TERMINAL FUNCTION DESCRIPTION
Terminal
Terminal
Name
Formal Name
1
RST
Reset
2
3
4
MODE0
MODE1
MODE2
Mode Control
These input terminals control VI/O_OUT and VCORE output voltages.
5–12,
14–22
NC
No Connects
No internal connection to this terminal.
13
GND
Ground
23, 24
VCORE
Core Voltage Regulator
Output
Core regulator output voltage.
25
LINB+
Core Voltage Regulator
Input
Core regulator input voltage.
26
VI/O_OUT
VI/O Switching Regulator
Feedback
Feedback terminal for VI/O switching regulator and internal logic supply.
27
VSWITCH
VI/O Switching Regulator
Switch Output
VI/O switching regulator switching output.
28
B+
Power Supply Input
29
Vb
Boost Voltage
30
CP2
Switching Capacitor 2
Charge pump capacitor connection 2.
31
CP1
Switching Capacitor 1
Charge pump capacitor connection 1.
32
Ct
Reset Delay Capacitor
Reset delay adjustment capacitor.
Definition
Reset input and output. This terminal is open drain.
Ground.
Regulator input voltage.
Boost voltage storage node.
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MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Max
Unit
GLOBAL ABSOLUTE MAXIMUM RATINGS
VB+
Input Power Supply Voltage
V
-0.3 to 36
IB + = 0 A
Terminal Soldering Temperature (Note 1)
Power Dissipation (Note 2)
TSOLDER
260
°C
PD
3.0
W
VESD1
±2000
RθJA
45
V
ESD Standoff Voltage
Non-Operating, Unbiased, Human Body Model (Note 3)
°C/W
Freescale Semiconductor, Inc...
Thermal Resistance
Junction-to-Ambient (Note 4)
Junction-to-Ambient (Note 2)
RθJA
25
Junction-to-Case
RθJC
2.0
Operating Ambient Temperature
TA
0 to 85
°C
Operating Device Junction Temperature
TJ
105
°C
GLOBAL OPERATING RATINGS
VB+
Input Power Supply Voltage
V
12 to 32
IB+ = 0 A to 3.0 A
IB+(q)
Quiescent Bias Current from B+ (Note 5)
mA
7.5
VB+ = 12 V to 32 V
TJ
Operating Junction Temperature
-0 to 105
°C
VI/O SWITCHING REGULATOR (Note 6)
Maximum Output Voltage Startup Overshoot (COUT = 330 µF)
VI/O(STARTUP)
V
MODE0 = 0
5.4
MODE0 = Open
3.6
IVI/O
Maximum Output Current
A
1.2
TA = 0°C to 105°C
Notes
1. Soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause
malfunction or permanent damage to the device.
2.
3.
With 2.0 in2 of copper headsink.
ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω).
4.
5.
6.
With no additional heatsinking.
Maximum quiescent power dissipation is 0.25 W.
12 V ≤ VB+ ≤ 32 V and -20°C ≤ TJ ≤ 145°C unless otherwise noted.
34710
4
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MAXIMUM RATINGS (continued)
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Max
Unit
VCORE LINEAR REGULATOR (Note 7)
Maximum Output Voltage Startup Overshoot (COUT = 10 µF) (Note 8)
VCORE (STARTUP)
MODE[2:0] = [0,x,0]
3.6
MODE[2:0] = [0,x,Open]
2.7
MODE[2:0] = [Open,x,0]
2.0
MODE[2:0] = [Open,x,Open]
1.65
IVCORE
Maximum Output Current
TJ = 0°C to 105°C, VLINB+ ≤ VCORE (NOM) + 0.8 V (Note 9)
Freescale Semiconductor, Inc...
V
mA
500
Notes
7. 12 V ≤ VB+ ≤ 32 V and -20°C ≤ TJ ≤ 145°C unless otherwise noted.
8.
9.
Refer to Table 1, page 10.
Pulse testing with low duty cycle used.
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STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.75 V ≤ VIO ≤ 5.25 V, 12 V ≤ VB+ ≤ 32 V, and 0°C ≤ TJ ≤ 105°C unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
VI/O SWITCHING REGULATOR
VI/O
Logic Supply Voltage (IVI/O = 25 mA to 1.0 A)
MODE0 = 0
4.8
–
5.2
MODE0 = Open
3.15
–
3.45
IVI/O
Logic Supply Current
VI/O = Nominal, Power Dissipation in Switching Regulator = 0.45 W
A
0.025
–
1.0
0.5
TBD
2.0
–
–
2.5
Ω
RDS(ON)
Output On Resistance
Freescale Semiconductor, Inc...
V
VB+ = 12 V to 32 V
VI/O(SOFT)
Soft Start Threshold Voltage
MODE0 = X
V
A
Current Limit Threshold (TJ = 25°C to 100°C)
ILIMIT (OP)
2.1
–
3.2
ILIMIT (SOFT)
1.3
–
1.8
-0.5
–
–
MODE[2:0] = [0,x,0]
3.15
–
3.45
MODE[2:0] = [0,x,Open]
2.35
–
2.65
MODE[2:0] = [Open,x,0]
1.71
–
1.89
MODE[2:0] = [Open,x,Open]
1.425
–
1.575
Normal Operation
Soft Start, VI/O ≤ 2.5 V
Minimum Voltage Allowable on VSWITCH Terminal
VVSWITCH (MIN)
TJ = 25°C to 100°C
V
VCORE LINEAR REGULATOR
Supply Voltage (IVCORE = 5.0 mA to 500 mA) (Note 10)
VCORE (NOM)
V
IVCORE
Supply Current
VCORE = VCORE (NOM)
mA
1.0
–
500
0.8
–
–
VCORE (NOM)
+ 1.0
–
10
800
–
1000
IVCORE(DROPOUT)
VCORE Dropout Voltage
VCORE = VCORE (NOM), IVCORE = 0.5 A
VLINB+
Regulator Input Voltage
VCORE = VCORE (NOM), IVCORE = 0.5 A
V
V
ILIMIT
Normal Current Limit Threshold
TJ = 25°C to 100°C, VLINB+ = VCORE (NOM) + 1.0 V
mA
Notes
10. Refer to Table 1, page 10.
34710
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.75 V ≤ VIO ≤ 5.25 V, 12 V ≤ VB+ ≤ 32 V, and 0°C ≤ TJ ≤ 105°C unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
MODE TERMINALS OPERATING VOLTAGES
VIL(MODEn)
MODE Control Terminals Low Voltage
V
–
–
0.825
2.6
–
–
TJ = 0°C to TBD°C, VB+ = 12 V to 14 V
7.0
–
12
TJ = 0°C to TBD°C, VB+ = 14 V to 32 V
8.0
–
13.2
VB+ (MIN)
9.0
–
–
V
VB+(ASSERT)
2.0
–
–
V
TJ = 0°C to TBD°C, VB+ = 12 V to 32 V
VIH (MODEn)
MODE Control Terminals High Voltage
V
TJ = 0°C to TBD°C, VB+ = 12 V to 32 V
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MODE Control Terminals Voltage with Input Floating
VMODE(FLOAT)
V
SUPERVISOR CIRCUITRY
Minimum Function VB+ for Charge Pump and Oscillator Running
Minimum VB+ for RST Assertion, VB+ Rising
VOL
RST Low Voltage
V
–
VB+ = 2.0 V, IRST ≤ 5.0 mA
–
0.4
–
VI/O(NOM)
–
V
RST VI/O Threshold
VI/O Rising
VI/O t+
–
VI/O Falling
VI/O t-
VI/O (NOM)
- 225 mV
–
VHYSVI/O
10
–
100
–
VCORE (NOM)
- 225 mV
–
–
10
–
100
RST Hysteresis for VI/O
- 80 mV
mV
V
RST VCORE Threshold
VCORE Rising
VCORE t+
–
VCORE Falling
VCORE t-
VCORE (NOM)
- 80 mV
VHYS CORE
RST Hysteresis for VCORE
mV
VB+ = 12 V to 32 V
VCORE (SHUTDOWN)
VCORE - VI/O for VCORE Shutdown
V
–
–
TBD
170
–
–
20
–
TBD
VB+ +10 V
–
VB+ +12 V
VB+ = 12 V to 32 V
°C
TJ (TSD)
Thermal Shutdown Temperature
TJ Rising
TJ (HYSTERESIS)
Overtemperature Hysteresis
°C
Vb CHARGE PUMP
Vb
Boost Voltage (Note 11)
VB+ = 12 V to 32 V, Ivb = 0.5 mA
V
Notes
11. Bulk capacitor ESR ≤ 10 Ω.
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DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.75 V ≤ VIO ≤ 5.25 V, 12 V ≤ VB+ ≤ 32 V, and 0°C ≤ TJ ≤ 105°C unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted
Characteristic
Symbol
Min
Typ
Max
Unit
D
45
–
55
%
25
–
–
VI/O SWITCHING REGULATOR
Duty Cycle
tr, tf
Switching Rise and Fall Time
Load Resistance = 100 Ω, VB+ = 30 V
tr + tf
Switching Rise and Fall Time
Load Resistance = 100 Ω, VB+ = 30 V
Freescale Semiconductor, Inc...
ns
ns
–
–
50
48
–
82
1.0
–
6.0
–
–
125
30
–
–
SUPERVISOR CIRCUITRY
ms
t delay
RST Delay
Cdelay = 0.1 µF
µs
t filter
RST Filter Time
VB+ = 9.0 V
ns
tf
RST Fall Time
CL = 100 pF, RPULLUP = 4.7 kΩ, 90% to 10%
t slpl
(Note 13)
External Low (Note 12)
VI/O = 5.0 V
RST Recovery Time Before Next RST Input (Note 12)
ns
µs
t phsl
VI/O = 5.0 V
–
–
10
140
–
260
INTERNAL OSCILLATOR
Charge Pump and VI/O Switching Regulator Operating Frequency
VB+ = 9.0 V to 32 V
f OP
kHz
Notes
12. See Figure 2, RST Timing, page 9.
13. t slpl is an input.
34710
8
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Timing Diagram
External
RST
Input
VIH
VIL
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t snl
t phsl
t slpl
34710
t delay
RST
VIH
VIL
Figure 2. RST Timing
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9
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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
VI/O Switching Regulator
The VI/O switching regulator output voltage is determined by
the MODE digital input terminals. The 34710’s MODE[2:0]
select the output voltage (Table 1). For example, if
MODE[2:0] = 0, 0, 0, then VI/O = 5.0 V; if MODE[2:0] = Open,
Open, Open, then VI/O = 3.3 V. The MODE0 terminal controls
the output voltage of both regulators.
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The topology of the regulator is a bang-bang buck regulator
operating from the internal ~200 kHz oscillator.
VCORE Linear Regulator
The VCORE linear regulator can produce a +3.3 V, 2.5 V,
1.8 V, or 1.5 V output voltage at 500 mA. The input to the
VCORE regulator is a terminal that may be connected to the VI/
O regulator output. The minimum input voltage must be
VCORE(NOM) + 0.8 V.
The MODE[2:0] terminals select the output voltage as
depicted in Table 1.
Table 1. VI/O and VCORE(NOM) Regulator
Output Voltage Selection
MODE2
MODE1
MODE0
VI/O
(V)
VCORE(NOM)
(V)
0
0
0
5.0
3.3
0
0
Open
3.3
2.5
0
Open
0
5.0
1.8
0
Open
Open
3.3
1.8
Open
0
0
5.0
2.5
Open
0
Open
3.3
2.5
Open
Open
0
5.0
1.5
Open
Open
Open
3.3
1.5
Open indicates terminal is not connected externally.
SUPERVISORY AND MISCELLANEOUS FUNCTIONS
Introduction
The supervisor circuitry provides control of the RST line, an
open drain signal, based on system operating conditions
monitored by the 34710. VI/O, VCORE, VB+, and thermal
shutdown (TSD) detectors in various parts of the chip are
monitored for error conditions. Because other devices in the
system may trigger a reset, the RST line itself is also monitored,
but the supervisor circuitry controls all reset timing, including
externally generated resets. Driving the RST line low causes the
system to be held in the reset state. VI/O, VCORE, VB+, and
thermal shutdown have both positive- and negative-going
thresholds.
The supervisor circuitry also ensures that the power supplies
sequence properly. Specifically, that VI/O is never less than
TBD V below VCORE. This means that VCORE - VI/O will be
clamped at 0.5 V, and that the VCORE regulator operation will be
suppressed during startup and shutdown to ensure that
VCORE - VI/O = TBD V.
Static Operating Specifications
The RST output is an I/O device with an open drain output
driver with a pullup and a CMOS digital input gate (Figure 3).
This I/O structure allows wired OR connection to the MCU’s
RST I/O terminal, as well as allowing the MCU to initiate a reset
cycle by driving its RST terminal low. When responding to a
MCU request for a reset cycle, the 34710 must respond rapidly
enough to prevent a glitch. Figure 2, page 9, shows the timing
34710
10
parameters for responding to an externally applied RST signal.
The rise time may be relatively slow, depending on the load
capacitance, and the internal RST input gate must operate
reliably (no oscillations during the transition) under these
conditions, i.e., the RST input can be inhibited for up to
tphsl(MAX). Error conditions must be present for a minimum
time, tfilter, before the 34710 responds to them. Once all error
conditions are cleared, RST is held low for an additional time of
tdelay. If any monitored item falls below its negative-going
threshold for tfilter, 1.0 µs to 6.0 µs, the tdelay will be restarted
when system operating conditions are met. The trigger for the
tdelay retriggerable one shot should be ([VI/O(LOW) +
VCORE(LOW) + VB+(LOW) + TJ(TSD)] & tfilter), where tfilter is the
1.0 µs to 6.0 µs delay.
VI/O
To Internal
Gates
From
Internal
Reset
Circuits
RPULLUP
≥ 4.7 kΩ
(Optional)
RST
CLOAD
(Optional)
Figure 3. RST Terminal Interface
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Vb Charge Pump
Internal Oscillator
The high-side MOSFETs in the H-Bridge motor drivers and
voltage regulators switch require a gate voltage in excess of
VB+, which is provided by the Vb supply. The Vb regulator is a
charge pump, switching directly off the VB+ supply, and uses an
internal oscillator operating at 200 kHz.
The internal oscillator provides timing for the charge pump
and switching regulators.
APPLICATIONS
Power Dissipation
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The power budget is described in Table 2. The maximum
dissipation for this device is 1.0 W continuous.
Table 2. Power Budget
Functional Block
Watt
Bias
0.00
Charge Pump
0.15
Switching Regulator
0.45
Linear Regulator
0.35
Total
0.95
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PACKAGE DIMENSIONS
EW (Pb-FREE) SUFFIX
32-LEAD SOICW-EXPOSED PAD
PLASTIC PACKAGE
CASE 1324-02
ISSUE A
10.3
7.6
7.4
C
5
Freescale Semiconductor, Inc...
1
B
2.65
2.35
9
30X
32
0.65
PIN 1 ID
4
B
9
B
16
11.1
10.9
CL
17
A
5.15
32X
2X 16 TIPS
0.3
0.10 A
A B C
A
(0.29)
A
0.25
0.19
6
0.13
BASE METAL
(0.203)
0.38
0.22
M
C A
R0.08 MIN
0.25
PLATING
M
B
SECTION A-A
ROTATED 90 ° CLOCKWISE
34710
12
SEATING
PLANE
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
3. DATUMS B AND C TO BE DETERMINED AT THE PLANE
WHERE THE BOTTOM OF THE LEADS EXIT THE
PLASTIC BODY.
4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH,
PROTRUSION OR GATE BURRS. MOLD FLASH,
PROTRUSION OR GATE BURRS SHALL NOT EXCEED
0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED
AT THE PLANE WHERE THE BOTTOM OF THE LEADS
EXIT THE PLASTIC BODY.
5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSIONS. INTERLEAD FLASH AND
PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER
SIDE. THIS DIMENSION IS DETERMINED AT THE
PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE
PLASTIC BODY.
6. THIS DIMENSION DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.4
MM PER SIDE. DAMBAR CANNOT BE LOCATED ON
THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSION AND ADJACENT LEAD
SHALL NOT LESS THAN 0.07 MM.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT SECTION
OF THE LEAD BETWEEN 0.10 MM AND 0.3 MM FROM
THE LEAD TIP.
9. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM. THIS DIMENSION IS
DETERMINED AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE
BAR BURRS, GATE BURRS AND INTER-LEAD FLASH,
BUT INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
GAUGE PLANE
8
8°
0°
0°
MIN
0.29
0.13
0.9
0.5
SECTION B-B
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NOTES
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13
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NOTES
34710
14
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NOTES
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unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated
with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their
respective owners.
© Motorola, Inc. 2004
HOW TO REACH US:
USA/EUROPE/LOCATIONS NOT LISTED:
Motorola Literature Distribution
P.O. Box 5405, Denver, Colorado 80217
1-800-521-6274 or 480-768-2130
JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center
3-20-1 Minami-Azabu. Minato-ku, Tokyo 106-8573, Japan
81-3-3440-3569
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre
2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong
852-26668334
HOME PAGE: http://motorola.com/semiconductors
For More Information On This Product,
Go to: www.freescale.com
MC34710