Freescale Semiconductor Technical Data Document number: MC34710 Rev 4, 8/2008 Dual Output DC-DC & Linear Regulator IC 34710 The 34710 is a dual-output power regulator IC integrating switching regulator, linear regulator, supervisory and power supply sequencing circuitry. With a wide operating input voltage range of 13 to 32V, the 34710 is applicable to many commercial and industrial applications using embedded MCUs. DUAL OUTPUT DC-DC & LINEAR REGULATOR A mode-selected 5.0 or 3.3V DC-DC switching regulator is provided for board-level I/O and user circuitry up to 700mA. A linear regulator provides mode-selected core supply voltages of either 3.3V, 2.5V, 1.8V, or 1.5V at currents up to 500mA. The supervisor circuitry ensures that the regulator outputs follow a predetermined power-up and power-down sequence. Features • Efficient 5.0V / 3.3V buck regulator • Low Noise LDO Regulator (mode-selected 3.3V, 2.5V,1.8V, or 1.5V) • On-chip thermal shutdown circuitry • Supervisory functions (Power-ON Reset and Error Reset circuitry) • Sequenced I/O and core voltages • Pb-free packaging designated by suffix code EW EW SUFFIX (PB-FREE) 98ASA10627D 32-PIN SOICW ORDERING INFORMATION Device Temperature Range (TA) Package MC34710EW/R2 0°C to 85°C 32 SOICW-EP VI/O 13 V to 32 V 34710 B+ VB CT VSWITCH CP2 VI/O VFB CP1 MCU MODE0 MODE1 MODE2 RST LINB+ VCORE GND VCORE Figure 1. 34710 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2006-2008. All rights reserved. INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM B+ 200 kHz Oscillator CP1 CP2 Charge Pump VB Supervisory and Temperature Shutdown RST CT Bandgap MODE0 MODE1 MODE2 LINB+ VI/O Switching Regulator VFB VSWITCH VCORE Linear Regulator VCORE GND Figure 2. 34710 Simplified Internal Block Diagram 34710 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS RST MODE0 MODE1 MODE2 N/C N/C N/C N/C N/C N/C N/C N/C GND N/C N/C N/C 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 CT CP1 CP2 VB B+ VSWITCH VFB LINB+ N/C VCORE N/C N/C N/C N/C N/C N/C Figure 3. 34710 Pin Connections Table 1. 34710 Pin Definitions Pin Number Pin Name Pin Function Formal Name 1 RST Reset Reset 2 3 4 Mode0 Mode1 Mode2 Input Mode Control These input pins control VFB and VCORE output voltages. 5 – 12, 14 –22, 24 NC NC No Connects No internal connection to this pin. 13 GND Ground Ground 23 VCORE Output Core Voltage Regulator Output 25 LINB+ Input Core Voltage Regulator Input Core regulator input voltage. 26 VFB Input VI/O Switching Regulator Feedback Feedback pin for VI/O switching regulator and internal logic supply. 27 VSWITCH Output VI/O Switching Regulator Switch Output 28 B+ Input Power Supply Input Regulator input voltage. 29 VB Output Boost Voltage Boost voltage storage node. 30 CP2 Passive Component CP Capacitor Positive Charge pump capacitor connection 2. 31 CP1 Passive Component CP Capacitor Negative Charge pump capacitor connection 1. 32 CT Passive Component Reset Delay Capacitor Reset delay adjustment capacitor. Definition Reset is an open drain output only. Ground. Core regulator output voltage. VI/O switching regulator switching output. 34710 Analog Integrated Circuit Device Data Freescale Semiconductor 3 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Rating Symbol Max Unit ELECTRICAL RATINGS VB+ Input Power Supply Voltage V -0.3 to 36 IB+ = 0.0A (1) (2) Peak Package Reflow Temperature During Reflow , Power Dissipation(3) TPPRT Note 2 °C PD 3.0 W V ESD Standoff Voltage VESD1 ±2000 RθJA 45 RθJA 25 RθJC 2.0 Operating Ambient Temperature TA 0 to 85 °C Operating Junction Temperature TJ 0 to 105 °C Non-Operating, Unbiased, Human Body Model(4) °C/W Thermal Resistance Junction-to-Ambient(5) Junction-to-Ambient(3) Junction-to-Exposed-Pad THERMAL RATINGS VB+ Input Power Supply Voltage V 13 to 32 IB+ = 0.0A to 3.0A IB+(Q) Quiescent Bias Current from B+(6) mA 7.5 VB+ = 13 to 32V VI /O SWITCHING REGULATOR(7) Maximum Output Voltage Startup Overshoot (COUT = 330μF) VI / O(STARTUP) V Mode0 = 0 5.4 Mode0 = Open 3.6 Maximum Output Current TA = 0°C to 105°C IVI/O mA 700 Notes 1. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), the Machine Model (MM) (CZAP = 200 pF, RZAP = 0 Ω), and the Charge Device Model (CDM), Robotic (CZAP = 4.0pF). 2. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 3. 4. With 2.0 in2 of copper heatsink. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100pF, RZAP = 1500Ω). 5. 6. 7. With no additional heatsinking. Maximum quiescent power dissipation is 0.25W. 13V ≤ VB+ ≤ 32V and - 20°C ≤ TJ ≤ 145°C, unless otherwise noted. 34710 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. MAXIMUM RATINGS (continued) All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Rating VCORE LINEAR REGULATOR Symbol Max Unit (8) Maximum Output Voltage Startup Overshoot (COUT = 10μF) (9) VCORE (STARTUP) V 3.6 Mode2=Low, Mode1=Low, Mode0=Low 2.7 Mode2=Open, Mode1=Low, Mode0=Don’t Care Mode2=Low, Mode1=Open, Mode0=Don’t Care 2.0 Mode2=Open, Mode1=Open, Mode0=Don’t Care 1.65 IVCORE Maximum Output Current TJ = 0°C to 105°C, VLINB+ ≤ VCORE (NOM) + 0.8V (10) mA 500 Notes 8. 13V ≤ VB+ ≤ 32V and - 20°C ≤ TJ ≤ 145°C, unless otherwise noted. 9. 10. Refer to Table 5, page 9. Pulse testing with low duty cycle used. 34710 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.75V ≤ VIO ≤ 5.25V, 13V ≤ VB+ ≤ 32V, and 0°C ≤ TJ ≤ 105°C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Mode0 = 0 4.8 5.0 5.2 Mode0 = Open (floating) 3.15 3.25 3.45 0.5 1.0 2.0 – 2.5 3.1 ILIMIT (OP) 1.9 2.4 2.9 ILIMIT (SOFT) 1.0 – 1.9 -0.5 – – 3.15 3.3 3.45 2.45 2.5 2.75 Unit SWITCHING REGULATOR (VI/O, MODE0) Logic Supply Voltage (IVI/O = 25 to 700mA) Output On Resistance VI / O Ω RDS(ON) VB+ = 13 to 32V Soft Start Threshold Voltage V VI / O(SOFT) Mode0 = any V A Current Limit Threshold (TJ = 25°C to 100°C) Normal Operation Soft Start, VI / O ≤ 2.5V Minimum Voltage Allowable on VSWITCH Pin VVSWITCH (MIN) TJ = 25°C to 100°C V LINEAR REGULATOR (VCORE, MODE 1, 2, 3, 4) Supply Voltage (IVCORE = 5.0mA)(11) V VCORE (NOM) Mode2=Low, Mode1=Don’t Care, Mode0=Low Mode2=Low, Mode1=Don’t Care, Mode0=Open 1.7 1.8 2.05 1.425 1.5 1.575 3.0 – 3.4 Mode2=Low, Mode1=Don’t Care, Mode0=Open 2.2 – 2.6 Mode2=Open, Mode1=Don’t Care, Mode0=Low 1.55 – 1.9 Mode2=Open, Mode1=Don’t Care, Mode0=Open 1.33 – 1.53 – 0.5 0.8 600 800 1000 Mode2=Open, Mode1=Don’t Care, Mode0=Low Mode2=Open, Mode1=Don’t Care, Mode0=Open Supply Voltage (IVCORE = 500mA)(11) Mode2=Low, Mode1=Don’t Care, Mode0=Low VCORE Dropout Voltage IVCORE(DROPOUT) VCORE = VCORE (NOM), IVCORE = 0.5A Normal Current Limit Threshold TJ = 25°C to 100°C, VLINB+ = VCORE (NOM) + 1.0V V VCORE (NOM) V ILIMIT mA Notes 11. Refer to Table 5, page 9. 34710 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.75V ≤ VIO ≤ 5.25V, 13V ≤ VB+ ≤ 32V, and 0°C ≤ TJ ≤ 105°C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit – – 0.825 2.6 – – 7.0 8.0 13 VB+ (MIN) – – 9.0 V VB+(ASSERT) – 1.9 2.2 V – 0.25 0.4 – VI/O(NOM) MODE PINS OPERATING VOLTAGES Mode Control Pins Low Voltage Mode Control Pins High Voltage Mode Control Pins Voltage with Input Floating VIL(Moden) V VIH (Moden) V VMode(FLOAT) VB+ = 13 to 14V V SUPERVISOR CIRCUITRY (RST, VCORE) Minimum Function VB+ for Charge Pump and Oscillator Running Minimum VB+ for RST Assertion, VB+ Rising RST Low Voltage VOL VB+ = 2.0V, IRST ≤ 5.0mA V RST VI / O Threshold V VI / O Rising VI / OT+ – VI / O Falling VI / OT- VI/O (NOM) - 300mV – – VHYSVI/O 10 – 100 VCORE Rising VCORET+ – – VCORE (NOM) VCORE Falling VCORET- VCORE (NOM) RST Hysteresis for VI / O - 50mV V RST VCORE Threshold RST Hysteresis for VCORE – – mV 10 50 100 0.5 – 0.9 VCORE (SHUTDOWN) VB+ = 13 to 32V Thermal Shutdown Temperature - 300mV - 30mV VHYS CORE VB+ = 13 to 32V VCORE - VI / O for VCORE Shutdown V °C TJ (TSD) – – 170 TJ (HYSTERESIS) – 20 – VB+ = 12 V, Ivb = 0.5 mA VB VB+ 8 VB+ 9 VB+ 10 VB+ = 32 V, Ivb = 0.5 mA VB VB+ 10 VB+ 12 VB+ 14 TJ Rising Over-temperature Hysteresis mV °C VB CHARGE PUMP V Boost Voltage(12) Notes 12. Bulk capacitor ESR ≤ 10 milliohms 34710 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.75V ≤ VIO ≤ 5.25V, 13V ≤ VB+ ≤ 32V, and 0°C ≤ TJ ≤ 105°C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted Characteristic Symbol Min Typ Max Unit D 45 49 55 % 20 35 50 40 60 80 2.0 4.0 8.0 – 25 75 VI /O SWITCHING REGULATOR Duty Cycle Switching Rise and Fall Time t R , tF Load Resistance = 100Ω, VB+ = 30V ns SUPERVISOR CIRCUITRY (RST) RST Delay RST Filter Time μs t FILTER VB+ = 9.0V RST Fall Time ms t DELAY Cdelay = 0.1μF ns tF CL = 100pF, RPULLUP = 4.7kΩ, 90% to 10% C Delay Charge Current ICDLY 2.0 3.5 5.0 μA Threshold Voltage VTHCD 1.7 2.0 2.2 V INTERNAL OSCILLATOR Charge Pump and VI / O Switching Regulator Operating Frequency VB+ = 12 to 32V f OP kHz 140 170 260 34710 8 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION voltage + 0.8V. (I.e., 0.8V is the LDO regulator drop out voltage.) VI /O Switching Regulator The VI /O switching regulator output voltage is determined by the Mode digital input pins. The 34710’s Mode pins select the output voltage. For example, if Mode2, Mode1, and Mode0 are set to 0, 0, 0 (respectively) then VI /O will be set to 5.0V; if Mode2, Mode1, and Mode0 are all left floating (i.e., Open, Open, and Open), then the voltage for VI /O will be set to 3.3V. Table 5 provides the truth table for setting the various combination of regulator outputs via the Mode pins. The Mode pins select the output voltage as depicted in Table 5. Table 5. VI /O and VCORE Regulator Output Voltage Selection Mode2 Mode1 Mode0 VI /O (V) VCORE (V) 0 0 0 5.0 3.3 The topology of the regulator is a hysteretic buck regulator operating from the internal ~200kHz oscillator. 0 0 Open 3.3 2.5 0 Open 0 5.0 1.8 VCORE Linear Regulator 0 Open Open 3.3 1.8 Open 0 0 5.0 2.5 Open 0 Open 3.3 2.5 Open Open 0 5.0 1.5 Open Open Open 3.3 1.5 The VCORE linear LDO (low drop-out) regulator can produce either a +3.3V, 2.5V, 1.8V, or 1.5V output voltage at currents up to 500mA. The input to the VCORE regulator is a pin that may be connected to the VI /O regulator output or to an external power supply. Note, the minimum input voltage level must be equal to or greater than the selected VCORE Open indicates pin is not connected externally (i.e. floating). FUNCTIONAL PIN DESCRIPTION POWER SUPPLY INPUT (B+) Main supply voltage for the VI/O Switching Regulator and general chip bias circuitry. CORE VOLTAGE REGULATOR INPUT (LIN B+) Supply voltage for the VCORE Regulator. May be provided by the VI/O regulator output or from an independent supply. MODE CONTROL (MODE 0,1,2) Mode select pins to select the VI/O and VCORE output voltages per table 2. Pull to ground for low state, float for high state. SWITCHING CAPACITORS 1 AND 2 (CP1/CP2) fault conditions. This pin has no input function and requires an external pull-up resistor. The RST pin is an open drain output driver to prevent oscillations during the transition. It is recommended to connect a 0.1uF capacitor between the CT pin and RST pin. Note: error conditions must be present for a minimum time, tFILTER, before the 34710 responds to them. Once all error conditions have been cleared, RST is held low for an additional time of tDELAY. RESET DELAY CAPACITOR (CT) This pin is the external delay. It is used with a capacitor to ground to delay RST turn-on time and to RST to prevent RST oscillations during chip power-on. Pins for the Charge Pump capacitor. VI/O SWITCHING REGULATOR FEEDBACK (VFB) BOOST VOLTAGE (VB) This pin is the feedback input for the VI/O Switching Regulator and the output of the regulator application. The Boost Voltage is an output pin used for the charge pump boost voltage and is a connection point for the Charge Pump bulk capacitor.It provides a gate drive for the VI/O Switch FET. VI/O SWITCHING REGULATOR OUTPUT (VSWITCH) RESET (RST) This pin is the Switching output for the VI/O Buck Regulator. It has internal high side FET. Reset is an output pin for supervisory functions. This pin is in high state during normal operation and low state during 34710 Analog Integrated Circuit Device Data Freescale Semiconductor 9 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION SUPERVISORY FUNCTIONS operation will be suppressed during startup and shutdown to ensure that VCORE - VI /O = 0.9V. Supervisory Circuitry The supervisory circuitry provides control of the RST line, an open drain signal, based on system operating conditions monitored by the 34710. VI /O, VCORE, VB+, and thermal shutdown (TSD) detectors in various parts of the chip are monitored for error conditions. VI /O, VCORE, VB+, and thermal shutdown have both positive and negative-going thresholds for triggering the reset function. The supervisor circuitry also ensures that the regulator outputs follow a predetermined power-up and power-down sequence. Specifically, the sequencing ensures that VI /O is never less than 0.9V below VCORE. This means that VCORE VI /O will be clamped at 0.5V, and that the VCORE regulator VB Charge Pump The high side MOSFET in the switching regulator (buck converter) requires a gate drive supply voltage that is biased higher than the B+ voltage, and this boosted voltage is provided by the internal charge pump and stored in a capacitor between the VB pin and the B+ pin. The charge pump operates directly from the B+ supply, and uses an internal oscillator operating at 200kHz. Internal Oscillator The internal oscillator provides a 200kHz square wave signal for charge pump operation and for the buck converter. 34710 10 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS TYPICAL APPLICATIONS B+ 13- 32V C1 330μF R1 1K C1 0.1mF SW1 1 RST 2 MODE0 3 MODE1 4 MODE2 SUPERVISORY & SHUTDOWN 13 GND CT 32 31 CHARGE CP1 30 PUMP CP2 VB 29 28 B+ BUCK 27 REG VSW 26 VFB 25 LINB 24 LDO 23 VCORE C5 0.1μF C6 10μF RSERIES 1.8 MC34710 L1 100μH D1 MBRS130LT3 C8 330μF 1 2 V I/O VCORE Figure 4. Typical Application Diagram The MC34710 provides both a buck converter and an LDO regulator in one IC. Figure 4 above shows a typical application schematic for the MC34710. L1 is the buck converter's inductor. The buck inductor is a key component and must not only present the required reactance, but do so at a DC resistance of less than 20 milliohms in order to preserve the converter's efficiency. Also important to the converter's efficiency is the utilization of a low VF Schottky diode for D1. Note that a 0.1uF capacitor is connected between CT and the reset pins; this prevents any possibility of oscillations occurring on the reset line during transitions by allowing the CT pin to discharge to ground potential via the RST pin, and then charge when RST returns to a logic high. The capacitor between the CP1 and CP2 pins is the charge pump's “bucket capacitor”, and sequentially charges and discharges to pump up the reservoir capacitor connected to the VB pin. Note that the reservoir capacitor's cathode is connected to B+ rather than ground. Also note that the charge pump is intended only to provide gate-drive potential for the buck regulator's internal power MOSFET, and therefore connecting external loads to the VB pin is not recommended. The IC's internal VCORE LDO regulator can provide up to 500mA of current as long as the operating junction temperature is maintained below 105 degrees C. The heatgenerating power dissipation of the LDO is primarily a function of the Volt x Amp product across the LINB+ and VCORE pins. Therefore, if the LINB+ voltage is >> than the selected VCORE voltage + 0.8V, it is recommended to use a power resistor in series with the LINB+ input to drop the voltage and dissipate the heat externally from the IC. For example, if the output of the buck regulator (V I/O on the schematic) is used as the input to LINB+, and the mode switches are set such that V I/O = 5V and VCORE = 3.3 , then a series resistance of 1.8 ohms at the LINB+ pin would provide an external voltage drop at 500mA while still leaving the minimum required headroom of 0.8V. Conversely, if the mode switches are set such that V I/O = 3.3V and VCORE = 2.5V, then no series resistance would be required, even at the maximum output current of 500mA. Designing a power supply circuit with the MC34710, like all DC-DC converter ICs, requires special attention not only to component selection, but also to component placement (i.e., printed circuit board layout). The MC34710 has a nominal switching frequency of 200kHz, and therefore pcb traces between the buck converter discrete component pins and the IC should be kept as short and wide as possible to keep the parasitic inductance low. Likewise, keeping these pcb traces 34710 Analog Integrated Circuit Device Data Freescale Semiconductor 11 TYPICAL APPLICATIONS short and wide helps prevent the converter's high di/dt switching transients from causing EMI/RFI. Figure 5. Typical PCB Layout Figure 5 shows a typical layout for the pcb traces connecting the IC's switching pin (VSWITCH) and the power inductor, rectifier, and filter components. Also, it is recommended to design the component layout so that the switching currents can be immediately sunk into a broad full-plane ground that provides terminations physically right at the corresponding component leads. This helps prevent switching noise from propagating into other sections of the circuitry. Figure 6. Bottom Copper Layout Figure 6 illustrates a pcb typical bottom copper layout for the area underneath a buck converter populated on the top of the same section of pcb. The ground plane is highlighted so the reader may note how the ground plane has been kept as broad and wide as possible. The square vias in the plane are located to provide an immediate path to ground from the top copper circuitry. Figure 7. Top Copper Layout Figure 7 shows the corresponding top copper circuit area with the component placement. Again, the ground plane and the vias have been highlighted so the reader may note the proximity of these current sink pathways to the key converter components. It is also important to keep the power planes of the switching converter's output spread as broad as possible beneath the passive components, as this helps reduce EMI/RFI and the potential for coupling noise transients into adjacent circuitry. Figure 8. Output Plane of Buck Converter Figure 8 shows the output plane of the buck converter highlighted. 34710 12 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS This layout provides the lowest possible impedance as well as lowest possible dc resistance for the power routing. Note that the power path and its return should be placed, if possible, on top of each other on different layers or opposite sides of the pcb. Small ceramic capacitors are placed in parallel with the Aluminum electrolytics so that the overall bulk filtering presents a low ESL to the high di/dt switching currents. Alternatively, special low ESL/ESR switching-grade electrolytics may be used. An additional feature of the MC34710 is the 32 SOICW-EP exposed pad package. The package allows heat to be conducted from the die down through the exposed metal pad underneath the package and into the copper of the pcb. In order to best take advantage of this feature, a grid array of thru-hole vias should be placed in the area corresponding to the exposed pad, and these vias then should then connect to a large ground plane of copper to dissipate the heat into the ambient environment. An example of these vias can be seen in the previous figures of a typical pcb layout. 34710 Analog Integrated Circuit Device Data Freescale Semiconductor 13 PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. EW (Pb-FREE) SUFFIX 32-LEAD SOICW-EXPOSED PAD 98ASA10627D ISSUE B 34710 14 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS EW (Pb-FREE) SUFFIX 32-LEAD SOICW-EXPOSED PAD 98ASA10627D ISSUE B 34710 Analog Integrated Circuit Device Data Freescale Semiconductor 15 PACKAGING PACKAGE DIMENSIONS EW (Pb-FREE) SUFFIX 32-LEAD SOICW-EXPOSED PAD 98ASA10627D ISSUE B 34710 16 Analog Integrated Circuit Device Data Freescale Semiconductor REVISION HISTORY REVISION HISTORY REVISION DATE DESCRIPTION OF CHANGES 2.0 8/2008 • • • • • Converted to Freescale format Updated Maximum Ratings, Static and Dynamic Characteristics tables. Updated packaging drawing Changed pin VI/O_OUT to VFB Implemented Revision History page 3.0 3/2006 • • Updated format from Preliminary to Advance Information. Format and style corrections to match standard template. 4.0 8/2008 • • • • • Update the Freescale format and style Changed the reflow parameter name to Peak Package Reflow Temperature During Reflow(1), (2) Removed PC33710EW/R2 from the ordering information. Changed Advance status to Final Update the package drawing to Rev B. 34710 Analog Integrated Circuit Device Data Freescale Semiconductor 17 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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