MOTOROLA MC34920

Freescale Semiconductor, Inc.
MOTOROLA
Document order number: MC34920
Rev 1.0, 01/2004
SEMICONDUCTOR TECHNICAL DATA
Advance Information
34920
2.8 Ω (Typ) Quad H-Bridge Motor
Driver
2.8 Ω (TYP) QUAD H-BRIDGE
MOTOR DRIVER
Each motor of the two driver blocks can be configured as either a DC motor
driver with pulse width modulation (PWM)-control or a single bipolar step
motor driver. In step motor mode, both drivers are capable of being operated
in the quarter step mode.
In DC motor mode, both bridges in a driver are in parallel, providing 2.4 A
of drive current. In step motor mode, each bridge in a driver drives one phase.
Each phase is driven with a bipolar current mode drive.
Features
• Individual Thermal Limit Protection
• User-Selectable Motors: 2 DC Motors (2.4 A/Motor), 2 Step Motors
(W1-2 Phase Control), 1 DC Motor and 1 Step Motor
• 2 Buck Regulators (Switching @ 200 kHz)
• VV2 Output Voltage Is Programmable to 10 V to 15 V DC (Externally Set)
EI (Pb-FREE) SUFFIX
FN SUFFIX
CASE 777
44-TERMINAL PLCC
ORDERING INFORMATION
• Low-Voltage Detection Reset (VV1 and VVB+)
Device
Temperature
Range (TA)
Package
MC34920EI/FN/R2
0°C to 70°C
44 PLCC
• Pb-Free Packaging Designated by Suffix Code EI
34920 Simplified
Application
Simplified
Application Diagram
Diagram
VVB+
VV1
VV2
+
+
MCU
SDI
V2_FB
VB+
V2_SWITCH
RESET
V1_SWITCH
34920
V1_FB
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The 34920 is a multifunctional analog ASIC. The 34920 integrates two
circuits, four H-bridge drivers, a reset circuit in a single IC, and two DC/DC
switching voltage regulators. Input voltage is 21 V to 42 V DC.
DR1A
DC
MOTOR
SCLK
DR2A
CS
DR1B
DR1PWM
DR2PWM
GND
DC
MOTOR
CP1
CP2
DR2B
Vb
VVB+
+
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Motorola, Inc. 2004
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V1
Regulator
Oscillator
V2
Regulator
VB+
Vb
CP2
CP1
V2_FB
V2_SWITCH
V1_FB
V1_SWITCH
VB+
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Boost
Voltage
Generator
DR1A1
DR1B1
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DR1SENSE1
DR1A2
DR1B2
RESET
RESET
SCLK
SDI
DR1PWM
DR2PWM
Serial
Input
Port
Control Logic-PWM Drive
CS
DR1SENSE2
DR2A1
DR2B1
DR2SENSE1
DR2A2
DR2B2
DR2SENSE2
Figure 1. 34920 Simplified Internal Block Diagram
34920
2
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GND
DR1A2
DR1SENSE2
DR1B2
DR2PWM
VB+
DR1PWM
DR1B1
DR1SENSE1
DR1A1
GND
28
27
26
25
24
23
22
21
20
19
18
10
V1_SWITCH
DR2_MODE
37
9
DR1_MODE
V2_FB
38
8
V1_FB
GND
39
7
GND
6
36
GND
VB+
V2_SWITCH
5
11
VCC
35
4
DR2A1
VB+
RESET
12
3
34
CP1
DR2SENSE1
DR2A2
2
13
CP2
33
1
DR2B1
DR2SENSE2
Vb
14
44
32
AGND
VB+
DR2B2
43
15
CS
31
42
VB+
VB+
SCLK
GND
16
SDI
17
30
41
29
VB+
40
GND
GND
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TERMINAL FUNCTION DESCRIPTION
Terminal
Terminal Name
Formal Name
1
Vb
Output terminal to VVb
2
CP2
Capacitor to CP1
Terminal for boost generator switch capacitor.
3
CP1
Capacitor to CP2
Terminal for boost generator switch capacitor.
4
RESET
Reset Output
5
VCC
VCC Supply Voltage
6, 7, 17, 18, 28,
29, 39, 40
GND
Substrate Ground
8
V1_FB
V1 Regulator Feedback Input
9
DR1_MODE
Mode Select for Driver 1
10
V1_SWITCH
Internal MOSFET Source for V1 Regulator
11, 15, 16, 23,
30, 31, 35
VB+
VB+ (Bulk) Supply Voltage
High-voltage supply for motors and regulators.
12
DR2A1
Driver 2, Bridge 1, Output A
Motor driver output.
13
DR2SENSE1
Driver 2, Bridge 1, I Sense
Current sense for current mode.
14
DR2B1
Driver 2, Bridge 1, Output B
Motor driver output.
19
DR1A1
Driver 1, Bridge 1, Output A
Motor driver output.
20
DR1SENSE1
Driver 1, Bridge 1, I Sense
Current sense for current mode.
21
DR1B1
Driver 1, Bridge 1, Output B
Motor driver output.
22
DR1PWM
Driver 1 PWM Input
PWM input for Driver 1. Used only when DR1_MODE
terminal = 0.
24
DR2PWM
Driver 2 PWM Input
PWM input for Driver 2. Used only when DR2_MODE
terminal = 0.
25
DR1B2
Driver 1, Bridge 2, Output B
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Definition
Terminal to connect to VVb capacitor.
Active low Reset output.
VCC power input for internal use. The 34920 accepts
either 3.3 V ±10% or 5.0 V ±5% for its logic voltage.
Ground connections for digital IC circuitry.
Voltage feedback for the V1 regulator.
Selects operational mode of Driver 1; Step = 1/DC = 0.
Switching output for V1 regulator.
Motor driver output.
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3
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TERMINAL FUNCTION DESCRIPTION (continued)
Terminal Name
Formal Name
26
DR1SENSE2
Driver 1, Bridge 2, I Sense
Current sense for current mode.
27
DR1A2
Driver 1, Bridge 2, Output A
Motor driver output.
32
DR2B2
Driver 2, Bridge 2, Output B
Motor driver output.
33
DR2SENSE2
Driver 2, Bridge 2, I Sense
Current sense for current mode.
34
DR2A2
Driver 2, Bridge 2, Output A
Motor driver output.
36
V2_SWITCH
Internal MOSFET Source for V2 Regulator
37
DR2_MODE
Mode Select for Driver 2
38
V2_FB
V2 Regulator Feedback Input
41
SDI
Serial Port Data Input
Serial input register serial data input.
42
SCLK
Serial Data Port Clock
Serial input register clock.
43
CS
Serial Data Port Chip Select
44
AGND
Analog Ground
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Terminal
34920
4
Definition
Switching output for V2 regulator.
Selects operational mode of Driver 2. Step = 1/ DC = 0.
Switch output for V2 regulator.
Serial input register chip select input. Active low.
Ground connection for analog circuitry.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
VVB+
45
V
VCC(MAX)
7.0
V
IOUT
1.5
A
VMAXRST
VCC - 0.5
V
Human Body Model (Note 2)
VESD1
±1000
Machine Model (Note 3)
VESD2
±100
TSTG
-40 to 175
°C
Operating Ambient Temperature
TA
0 to 70
°C
Operating Junction Temperature
TJ
135
°C
Power Dissipation (TA = 25° C) (Note 4)
PD
2.0
W
TSOLDER
220
°C
RθJA
37
°C/W
VB+ Supply Voltage
VCC Voltage
Bridge Output Current
Maximum Voltage on RESET (Note 1)
V
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ESD Voltage
Storage Temperature
Terminal Soldering Temperature (Note 5)
Thermal Resistance, Junction to Ambient (Note 6)
Notes
1. RESET is an open drain (open collector) output with an internal pull-up resistor.
2. ESD1 testing is performed in accordance with the Human Body Model (CZAP =100 pF, RZAP =1500 Ω).
3.
ESD2 testing is performed in accordance with the Machine Model (CZAP =200 pF, RZAP =0 Ω).
4.
5.
Maximum power dissipation at indicated ambient temperature in free air with no heatsink used.
Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
RθJA is dependent on customer application and PCB layout.
6.
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STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 21 V ≤ VVB+ ≤ 42 V, TA = 10°C to 55°C, TJ max = 135°C, VCC = 5.25 V max unless otherwise
noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under typical conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
VVB+ Supply Voltage
VVB+
21
–
42
V
VVB+ Standby Current
IVB+
POWER INPUT
VVB+ = 42 V, ICC Load = 5.0 mA, No Serial Clock, No Motor Driver, No Load
on VV2
mA
1.0
14
55
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CMOS LOGIC LEVEL (Note 7)
Input Current, High-Voltage State
IIH
–
0.1
170
µA
Input Current, Low-Voltage State
IIL
-170
-0.1
–
µA
Input Low Input Voltage State
VIL
VCC + 3.3 V ±10%
–
–
0.8
VCC + 5.0 V ±5%
–
–
1.5
VCC + 3.3 V ±10%
2.1
–
–
VCC + 5.0 V ±5%
3.3
–
–
VOUT
-4.0%
Nom
+4.0%
V
TJ(SHUTDOWN)
155
–
175
oC
TJ(ENABLE)
135
–
155
o
Overcurrent Detect Level (Peak) for IV1_SWITCH
IOC_V1
1.5
2.0
2.5
A
Overcurrent Detect Level (Peak) for IV2_SWITCH
IOC_V2
2.5
3.25
4.0
A
Short Circuit Detect Level (Peak) for IV1_SWITCH
ISC_V1
0.75
1.25
1.75
1.75
2.25
2.75
–
2.0
–
V
VIH
Input High-Voltage State
V
V1 AND V2 VOLTAGE REGULATORS
Regulator Output Voltage
Regulator Thermal Shutdown Junction Temperature
Regulator Thermal Junction Temperature
In Soft Start and Foldback Modes
Short Circuit Detect Level (Peak) for IV2_SWITCH
V1 Switching MOSFET on Resistance
Internal Reference Value of 2.50 V ±2%
Turn-Off Regulator
VV1 Output/VV2 Output = 0 V
Ω
Ω
RDS(ON)V2
–
Full On, Typical Value @ TJ = 25°C
Regulator Feedback Input
A
RDS(ON)V1
Full On, Typical Value @ TJ = 25°C
V2 Switching MOSFET on Resistance
A
ISC_V2
In Soft Start and Foldback Modes
C
0.75
–
VV1_FB,
VV2_FB
V
–
2.5
–
VoffV1_FB,
VoffV2_FB
3.0
–
–
V
Notes
7. Applicable to all logic level input signals. Inputs are to be designed to accept 3.3 V logic levels and be +5.0 V tolerant.
34920
6
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 21 V ≤ VVB+ ≤ 42 V, TA = 10°C to 55°C, TJ max = 135°C, VCC = 5.25 V max unless otherwise
noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under typical conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
–
5.0%
–
Unit
V1 AND V2 VOLTAGE REGULATORS (continued)
VOVRSHT
Voltage Overshoot
External VCC Load Current from 0.01 to 0.500 A, tRISE > 100 ns
–
VOUTRIPPLE
Load Ripple
0.5 A maximum
mV
–
100
–
10
–
14
–
–
0.6
–
–
1.6
VBOOST GENERATOR
VVb-VVB+
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Charge Pump Output Voltage
ILOAD = 1.0 mA
V
BIPOLAR CURRENT REGULATED STEP MOTOR DRIVE SYSTEM
ISTEPMOTOR
Peak
Peak Step Motor Current, Phase A or B
Motor Not Stalled
Maximum Allowable Voltage Drop Across Any H-Bridge Switch
A
VDROP
ILOAD = 0.6 A (from Output to GND) or ILOAD = 0.6 A (from VVB+ to Output)
V
VTH
Comparator High Threshold Voltage
mV
450
550
650
300
–
440
105
–
255
-1.0
0.1
1.0
TJ(SHUTDOWN)
155
–
175
o
C
TJ(ENABLE)
135
–
155
o
C
–
1.43
–
CURR_I0_PHASEX=0, CURR_I1_PHASEX=0
VTM
Comparator Medium Threshold Voltage
CURR_I0_PHASEX=1, CURR_I1_PHASEX=0
mV
VTL
Comparator Low Threshold Voltage
CURR_I0_PHASEX=0, CURR_I1_PHASEX=1
VOOFF Output Leakage Current for Step Motor Driver Outputs
IOOFF
VOOFF = 5.0 V
Step Motor Driver Thermal Shutdown Junction Temperature
Step Motor Driver Thermal Enable Junction Temperature
mV
mA
Ω
RDS(ON)
Single MOSFET
Typical Value @ TJ = 25°C
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 21 V ≤ VVB+ ≤ 42 V, TA = 10°C to 55°C, TJ max = 135°C, VCC = 5.25 V max unless otherwise
noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under typical conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
DC MOTOR DRIVE SYSTEM
Maximum Allowable Voltage Drop Across Any H-Bridge Switch
VDROP
ILOAD = 0.75 A (from Output to GND) or ILOAD = 0.75 A (from VVB+ to
Output) (Using 2 H-Bridges in Parallel)
Peak DC Motor Driver Current
Motor Not Stalled (Using 2 H-Bridges in Parallel)
–
–
1.3
–
–
1.2
1.6
2.0
2.5
A
IDCMOTOROCT
DC Motor Overcurrent Threshold (Note 8)
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IDCMOTOR
Peak Current
V
Motor Stalled (Paralleled H-Bridges Used for DC Motor Drive)
A
IDC_SUSTAIN
DC Motor Driver Sustaining Current Value
Current Allowed to Sustain for a Minimum of 100 ms (OCT delay),
Current Ripple 100 mA (Peak-to-Peak or Less)
A
1.6
2.0
2.4
VDCMD
Differential DC Motor Driver Output Voltage
VVB++ Rising Monotonically from 0 V to 42 V (1.0 µs < tR < 10 ms) OR
VVB+ Falling Monotonically from 42 V to 0 V (1.0 µs < tF < 10 ms)
DC Motor Driver Thermal Shutdown Output Voltage
–
–
4.0
VVB+ - 0.5 V
–
–
TJ(SHUTDOWN)
155
–
175
oC
TJ(ENABLE)
135
–
155
o
–
0.73
–
VOH_DCM
IOH = 0.1 V
DC Motor Driver Thermal Shutdown Junction Temperature
DC Motor Driver Thermal Enable Junction Temperature
V
V
Ω
RDS(ON)
Equivalent Resistance
Using 2 H-Bridges in Parallel, Nom Value @ TJ = 25°C
C
Notes
8. Because the current clamp is applied to the top H-bridge transistors only, overcurrent protection applies to motor currents. But note that no
short circuit protection exists against shorts from the DC motor outputs (DR1A1, DR1A2, DR1B1, or DR1B2 to substrate ground or to VB+.
34920
8
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 21 V ≤ VVB+ ≤ 42 V, TA = 10°C to 55°C, TJ max = 135°C, VCC = 5.25 V max unless otherwise
noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under typical conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
VCC - 0.5 V
–
–
–
–
0.2
VCC + 3.3 V ±10%
–
–
0.8
VCC + 5.0 V ±5%
–
–
1.5
VCC + 3.3 V ±10%
2.1
–
–
VCC + 5.0 V ±5%
3.3
–
–
Unit
RESET
VOH
RESET High-State Output Voltage
IOH = -0.1 mA
V
VOL
RESET Low-State Output Voltage
V
VV1_FB < VV1T+
VIL
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Input Low Voltage State
V
VIH
Input High-Voltage State
V
VV1T-
RESET VV1_FB Low Threshold
Voltage at V1_FB
V
1.9
2.08
2.2
2.05
2.23
2.35
13.5
15.4
16.5
13.5
16.6
20
VV1T+
RESET VV1_FB High Threshold
Voltage at V1_FB
V
VVB+T-
RESET VVB+ Low Threshold
VB+
V
VVB+T+
RESET VVB+ High Threshold
VB+
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
V
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DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 21 V ≤ VVB+ ≤ 42 V, TA = 10°C to 55°C, TJ max = 135°C, VCC = 5.25 V max unless otherwise
noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under typical conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Serial Clock Frequency
fCLK
–
4.0
12
MHz
SCLK High Width
tCLH
41.667
125
–
ns
SCLK Low Width
tCLL
41.667
125
–
ns
Delay CS Falling to First SCLK Rising
tCS-SCLK
83.333
250
–
ns
Delay Last SCLK Rising Edge to CS Rising
tSCLK-CS
83.333
250
–
ns
Data Valid to SCLK Set-Up Time
tDSU
41.667
125
–
ns
Data Hold Time
tDHD
41.667
125
–
ns
SDI Rise Time
tRD
5.0
–
10
ns
SDI Fall Time
tFD
5.0
–
10
ns
tRFC
5.0
–
10
ns
tNCS-OFF
83.333
250
–
ns
fOP
175
200
225
kHz
V1 Duty Cycle
V1_DC
35
37.5
40
%
V2 Duty Cycle
V2_DC
80
82.5
85
%
tDEAD
15
200
350
ns
tOFF
20
29
38
µs
tBLANK
300
–
750
ns
–
20
21
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SERIAL INPUT PORT TIMING
SCLK Rise/Fall Time
CS Off-Time (tDHD + tDSU)
V1 AND V2 VOLTAGE REGULATORS
Clock Frequency Overtemperature
BIPOLAR CURRENT REGULATED STEP MOTOR DRIVE SYSTEM
Shoot-Through Delay
Off-Time
Current Blanking Time
DC MOTOR DRIVE SYSTEM
PWM Frequency
fPWM
TA = 25°C
kHz
Shoot-Through Delay
tDEAD
15
180
350
ns
Overcurrent Off-Time
tOC_OFF
10
40
70
µs
34920
10
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DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 21 V ≤ VVB+ ≤ 42 V, TA = 10°C to 55°C, TJ max = 135°C, VCC = 5.25 V max unless otherwise
noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under typical conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
15
33
50
10
20
30
Unit
RESET
tDELAY
RESET Delay
VV1_FB ≥ VV1T+
µs
tPERSIST
VCC Out-of-Tolerance Persistence Time
RESET De-Asserted, VV1_FB < VV1T-
tR
RESET Rise Time
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ms
10% to 90% (Note 9)
ns
–
630
750
–
11
50
tF
RESET Fall Time
90% to 10% (Note 9)
ns
Notes
9. Test circuit is 50 pF capacitor from RESET to GND.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Table 1. Step Motor Truth Table
CURR_I0_
PHASEA
CURR_I1_
PHASEA
IPH_A (mA)
DIR_PH_B
CURR_I0_
PHASEB
CURR_I1_
PHASEB
IPH_B (mA)
0
0
0
550
0
0
0
550
0
1
0
367
0
1
0
367
0
0
1
183
0
0
1
183
X
1
1
Off
X
1
1
Off
1
0
0
-550
1
0
0
-550
1
1
0
-367
1
1
0
-367
1
0
1
-183
1
0
1
-183
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DIR_PH_A
Table 2. DC Motor Drive System Truth Table
34920
12
DRx_DIR_DCM
DRxPWM
High-Side A
Low-Side A
High-Side B
Low-Side B
0
0
On
Off
On
Off
0
1
Off
On
On
Off
1
0
On
Off
On
Off
1
1
On
Off
Off
On
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Timing Diagrams
TcstSCLK-CS
- SCLK
tCS-SCLK
Tcs
+ SCLK
nCS
CS
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Data
latched
rising
Data Latched
on theon
rising
edge edge
of SCLKof SCLK
SCLK
SCLK
tDSU
Tdsu
SDI
SDI
Bit 11
Bit
Bit 22
Bit
Bit 33
Bit
Bit 44
Bit
Bit
Bit55
tDHD
Tend
Bit 66
Bit
Bit
Bit77
Bit
Bit88
Bit 99
Bit
Bit 10
Bit
10
Bit
Bit1111
Bit
Bit1212
Bit
Bit1313*
SDI Stays at Last Value
MSB
MSB
LSB
LSB
Time
Time
*SDI stays at last value
Figure 2. Serial Connectivity Diagram
Power
On
Power On
VCC
VCC
“Glitch”
Response
“Glitch” Response
Trip Level
Trip level
V
V1T
VtVCC
Power
Off
Power Off
Trip Level
VV1T
Trip level
VtVCC
Short
Shortglitch
glitchbelow
below VV1T
forVtVCC
less than
tPERSIST
for less
than Tpersist
1.0
1 VV
RESET
n RESET
undefined
Undefined
Undefined
undefined
15-50mS
t DELAY Tdelay
15–50
ms
(plus Tpersist delay)
(plus t PERSIST)
t PERSIST
Tpersist delay
Tdelay 15–50
15-50 mS ms
t DELAY
(plus Tpersist delay_
(plus t PERSIST)
t PERSIST
Tpersist delay
Assumes
VB+
> VtVB+
during
the
entire period
Timing
Diagram
(Assumes
VVB+ > V
Figure 3. RESET Generation
VB+T+ During Entire Period)
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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
Introduction
The 34920 is a multifunctional analog IC that can be used in
printer and scanner applications. It integrates two switching
voltage regulator circuits, four H-bridge drivers, and a reset
circuit in a single IC. All 34920 control lines are compatible with
CMOS type 3.3 V and 5.0 V logic.
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Switching Voltage Regulator Circuits
Two switching voltage regulators provide the following
voltages from an unregulated input of 21 V to 42 V DC. Both are
buck-type switching regulators using a MOSFET (internal to the
34920), current sense resistor (internal to the 34920), Schottky
diode (external to the 34920), external inductor, and filter
capacitor.
• V1 Voltage Regulator – This regulator is programmable,
has a duty cycle of 37%, and provides either 3.3 V (+5%/
-4%) or 5.0 V (+5%/-4%) at a current of 10 mA (minimum)
to 500 mA (maximum).
• V2 Voltage Regulator – This regulator has a
programmable output voltage (by means of an external
resistor divider network) in the range of 10 V to 15 V ±2%
with a VB+ supply voltage range of 21 V to 42 V.
The V2 voltage regulator is controlled by an Enable bit in the
serial register that allows software to turn this regulator on and
off. However, the Enable bit does not effect the V1 voltage
regulator. The Enable bit will disable the V2 voltage regulator
and disable all motor driver circuits.
Motor Drivers
The two motor drivers can be selectable as either a bidirectional DC motor driver, with PWM control and peak
currents of 2.4 A, or a bipolar step motor driver, with average
current levels of 183 mA and 550 mA per phase, and quarter
step mode capability. In step mode, both drivers are capable of
being operated in the quarter step mode.
RESET Generation
The 34920 provides an output, RESET, that drives an
external reset signal to the system microprocessor and/or the
system digital logic IC. This signal is an active low logic level
signal that is derived by monitoring the level of the VB+ and
V1_FB terminals.
When RESET is asserted, either internally or from an
external source, all 34920 motor driver outputs will be in their
inactive states, and the serial input port will be loaded with the
reset value.
FUNCTIONAL DESCRIPTION
Input Power Supply (VVB+)
The input voltage for the switching regulators and motor
drivers. VVB+ is a voltage range of 21 V to 42 V.
CMOS Logic Level
CMOS logic level specifications are described on page 6 of
the Static Electrical Characteristics table.
34920 Input
Table 3, page 15, describes the 34920 input specifications.
Serial Input Port
The 34920 provides a serial input port for bit depth of 13 bits
of input. This port provides an interface between the 34920 and
the digital controller IC. This port is write-only. The interface
consists of three signal lines: chip select (CS, active low), serial
clock (SCLK), and serial data input (SDI).
34920
14
The digital controller initiates a serial transfer by pulling low
the chip select line (CS). It then generates 13 clock pulses on
the SCLK terminal while presenting the serial data on the serial
data input (SDI). The 34920 presents the data on SDI one setup
time (t DSU) before the rising edge of SCLK. The data is held
constant for the data hold time (t DHD) beyond the SCLK rising
edge. The data is shifted into the 34920 on the rising edge of
SCLK. The least significant bit (LSB) is the first to be shifted out
of the 34920 on the rising edge of SCLK, followed by the
remaining bits to the last of the 13 bits, which is the most
significant bit (MSB). The CS line is then returned to a high
state. The low-to-high transition of CS will load the data into the
internal 34920 input register, where all the inputs are presented
to their appropriate functions in a parallel fashion.
Note The minimum off-time (CS signal equal to logic [1]) for
the CS signal needs to be at least 1.0 t DSU delay + 1.0 t DHD
delay. This will provide the time for the 34920 to clear the serial
input data register (transfer the serial data in parallel to internal
latches that use the data) and thereby avoid a data overrun
condition and loss of data. See the serial input port timing data
in the Dynamic Electrical Characteristics table, page 10.
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Table 3. 34920 Input Specifications
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Name
Description
V1_FB
Voltage feedback for the V1 regulator.
VCC
VCC power input for internal use. The 34920 accepts either 3.3 V ±10% or 5.0 V ±5% for its logic voltage.
V2_FB
Voltage feedback for the V2 regulator.
CS
Serial input register chip select input. Active low.
SCLK
Serial input register clock.
SDI
Serial input register serial data input.
DRxPWM
PWM input for the DC motor driver for either Driver 1 or Driver 2.
DRx_MODE
Selects mode of each motor driver. Step = 1/DC = 0.
The following inputs are through the Serial Input Register
V2_Enable
Enable bit to turn on and off the V2 regulator and the motor drivers. When low (= logic [0]), the V2 regulator and
the motor drivers are turned off and the 34920 is placed in its lowest possible power state. V1 is not affected by
the Enable bit.
DR1_CURR_I1_PHASEA
Second of two inputs that control the current level in the step motor Phase A winding (Driver 1/Step Mode).
DR1_CURR-I0_PHASEA
First of two inputs that control the current level in the step motor Phase A winding (Driver 1/Step Mode).
DR1_DIR_PH_A
Controls the direction of the current flow through Phase A of the step motor; i.e., logic [1] level causes conventional
current flow from DR1A1 to DR1B1 (Driver 1/Step Mode).
DR1_CURR_I1_PHASEB
Second of two inputs that control the current level in the step motor Phase B winding (Driver 1/Step Mode).
DR1_CURR_I0_PHASEB
First of two inputs that control the current level in the step motor Phase B winding (Driver 1/Step Mode).
DR1_DIR_PH_B
Controls the direction of the current flow through Phase B of the step motor. A logic [1] level causes conventional
current flow from DR1A2 to DR1B2 (Driver 1/Step Mode).
DR2_CURR_I1_PHASEA
Second of two inputs that control the current level in the step motor Phase A winding (Driver 2/Step Mode).
DR2_CURR_I0_PHASEA
One of two inputs that control the current level in the step motor Phase A winding (Driver 2/Step Mode).
DR2_DIR_PH_A
Controls the direction of the current flow through Phase A of the step motor. A logic [1] level causes conventional
current flow from DR2A1 to DR2B1 (Driver 2/Step Mode).
DR2_CURR_I1_PHASEB
Second of two inputs that control the current level in the step motor Phase B winding (Driver 2/Step Mode).
DR2_CURR_I0_PHASEB
One of two inputs that control the current level in the step motor Phase B winding (Driver 2/Step Mode).
DR2_DIR_PH_B
Controls the direction of the current flow through Phase B of the step motor. A logic [1] level causes conventional
current flow from DR2A2 to DR2B2 (Driver 2/Step Mode).
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Serial Input Port Bit Definitions
Tables 4 through 7 define the bit definitions as they apply to
the 13 bits of input that are brought into the 34920 through the
serial input port. These signals are listed in bit order from LSB
(first bit to be shifted in) to MSB (last bit to be shifted in).
Table 4. Serial Input Port Definition for Step/Step Mode
Bit
Reset
Value
V2_Enable
1
1
Enable bit to turn on and off the V2 regulator and the motor drivers and place the 34920
in the minimum power consumption state.
SDR2_CURR_I1_PHASEB
2
1
Second of two inputs that control the current level in the SDR2 step motor Phase B
winding.
SDR2_CURR_I0_PHASEB
3
1
One of two inputs that control the current level in the SDR2 step motor Phase B
winding.
SDR2_DIR_PH_B
4
0
Controls the direction of the current flow through Phase B of the SDR2 step motor. A
logic [1] level causes conventional current flow from PH_B+ (source) to PH_B- (sink).
SDR2_CURR_I1_PHASEA
5
1
Second of two inputs that control the current level in the SDR2 step motor Phase A
winding.
SDR2_CURR_I0_PHASEA
6
1
One of two inputs that control the current level in the SDR2 step motor Phase A
winding.
SDR2_DIR_PH_A
7
0
Controls the direction of the current flow through Phase A of the SDR2 step motor. A
logic [1] level causes conventional current flow from PH_A+ (source) to PH_A- (sink).
SDR1_CURR_I1_PHASEB
8
1
Second of two inputs that control the current level in the SDR1 step motor Phase B
winding.
SDR1_CURR_I0_PHASEB
9
1
One of two inputs that control the current level in the SDR1 step motor Phase B
winding.
SDR1_DIR_PH_B
10
0
Controls the direction of the current flow through Phase B of the SDR1 step motor. A
logic [1] level causes conventional current flow from PH_B+ (source) to PH_B- (sink).
SDR1_CURR_I1_PHASEA
11
1
Second of two inputs that control the current level in the SDR1 step motor Phase A
winding.
SDR1_CURR_I0_PHASEA
12
1
One of two inputs that control the current level in the SDR1 step motor Phase A
winding.
SDR1_DIR_PH_A
13
0
Controls the direction of the current flow through Phase A of the SDR1 step motor. A
logic [1] level causes conventional current flow from PH_A+ (source) to PH_A- (sink).
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Name
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Table 5. Serial Input Port Definition for DC Motor/DC Motor Mode (Note 10)
Bit
Reset
Value
V2_Enable
1
1
Enable bit to turn on and off the V2 regulator and the motor drivers and place the 34920
in the minimum power consumption state.
Not Used
2
X
Not used in this mode.
Not Used
3
X
Not used in this mode.
Not Used
4
X
Not used in this mode.
Not Used
5
X
Not used in this mode.
Not Used
6
X
Not used in this mode.
DR2_DIR_DCM
7
0
Controls the direction of the current flow through the DC motor. A logic [1] level causes
conventional current flow from DR2A1 (source)/DR2A2 (source) to DR2B1 (sink)/
DR2B2 (sink).
Not Used
8
X
Not used in this mode.
Not Used
9
X
Not used in this mode.
Not Used
10
X
Not used in this mode.
Not Used
11
X
Not used in this mode.
Not Used
12
X
Not used in this mode.
DR1_DIR_DCM
13
0
Controls the direction of the current flow through the DC motor. A logic [1] level causes
conventional current flow from DR1A1 (source)/DR1A2 (source) to DR1B1 (sink)/
DR1B2 (sink).
Freescale Semiconductor, Inc...
Name
Description
Notes
10. DR1_MODE and DR2_MODE terminals = logic [0] for DC motor drive for both drivers.
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Table 6. Serial Input Port Definition for DR1=Step/DR2=DC Motor Mode
Bit
Reset
Value
V2_Enable
1
1
Enable bit to turn on and off the V2 regulator and the motor drivers and place the 34920
in the minimum power consumption state.
Not Used
2
X
Not used in this mode.
Not Used
3
X
Not used in this mode.
Not Used
4
X
Not used in this mode.
Not Used
5
X
Not used in this mode.
Not Used
6
X
Not used in this mode.
DR2_DIR_DCM
7
0
Controls the direction of the current flow through the DC motor. A logic [1] level causes
conventional current flow from DR2A1 (source)/DR2A2 (source) to DR2B1 (sink)/
DR2B2 (sink).
SDR1_CURR_I1_PHASEB
8
1
Second of two inputs that control the current level in the SDR1DR1 step motor
Phase B winding.
SDR1_CURR_I0_PHASEB
9
1
One of two inputs that control the current level in the SDR1 step motor Phase B
winding.
SDR1_DIR_PH_B
10
1
Controls the direction of the current flow through Phase B of the SDR1 step motor. A
logic [1] level causes conventional current flow from PH_B+ (source) to PH_B- (sink).
SDR1_CURR_I1_PHASEA
11
0
Second of two inputs that control the current level in the SDR1 step motor Phase A
winding.
SDR1_CURR_I0_PHASE
12
1
One of two inputs that control the current level in the SDR1 step motor Phase A
winding.
SDR1_DIR_PH_A
13
1
Controls the direction of the current flow through Phase A of the SDR1 step motor. A
logic [1] level causes conventional current flow from PH_A+ (source) to PH_A- (sink).
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Name
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18
Description
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Table 7. Serial Input Port Definition for DR1=DC Motor/DR2 =Step Mode
Bit
Reset
Value
V2_Enable
1
1
Enable bit to turn on and off the V2 regulator and the motor drivers and place the 34920
in the minimum power consumption state.
SDR2_CURR_I1_PHASEB
2
1
Second of two inputs that control the current level in the SDR2 step motor Phase B
winding.
SDR2_CURR_I0_PHASEB
3
1
One of two inputs that control the current level in the SDR2 step motor Phase B
winding.
SDR2_DIR_PH_B
4
0
Controls the direction of the current flow through Phase B of the SDR2 step motor. A
logic [1] level causes conventional current flow from PH_B+ (source) to PH_B+ (sink).
SDR2_CURR_I1_PHASEA
5
1
Second of two inputs that control the current level in the SDR2 step motor Phase A
winding.
SDR2_CURR_I0_PHASEA
6
1
One of two inputs that control the current level in the SDR2 step motor Phase A
winding.
SDR2_DIR_PH_A
7
0
Controls the direction of the current flow through Phase A of the SDR2 step motor. A
logic [1] level causes conventional current flow from PH_A+ (source) to PH_A- (sink).
Not Used
8
X
Not used in this mode.
Not Used
9
X
Not used in this mode.
Not Used
10
X
Not used in this mode.
Not Used
11
X
Not used in this mode.
Not Used
12
X
Not used in this mode.
DR1_DIR_DCM
13
0
Controls the direction of the current flow through the DC motor. A logic [1] level causes
conventional current flow from DR1A1 (source)/DR1A2 (source) to DR1B1 (sink)/
DR1B2 (sink).
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Description
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Voltage Regulators
The 34920 contains two switching voltage regulators (see
Figure 4). Both are buck-type voltage regulators using an
internal switching MOSFET. The V1 regulator provides either
3.3 V or 5.0 V at +5%/-4% tolerance. The V2 regulator’s output
voltage, VV2, is programmable through the use of an external
resistor divider network. The voltage tolerance on the VV2
output is ±2% of the nominal voltage set point. The switching
frequency of the V1 and V2 regulators is approximately
200 kHz.
Freescale Semiconductor, Inc...
The V1 and V2 regulators are designed with a dual-mode
current limit circuit. The current limit threshold is lowered during
the power-on period to allow for a softer start-up, thereby
reducing electrical stress in the external components.
VVB+, the input voltage for the switching voltage regulators,
ranges from 21 V to 42 V. To minimize the ripple current on
VVB+, the V1 regulator and the V2 regulator switch out of phase.
A boost voltage generator (Vb generator), which acts as a
single-stage charge pump, provides gate drive voltage for the
switching regulators. It uses an external capacitor to store the
charge.
Output voltages VV1 and VV2 are set externally with a resistor
(1% tolerance) divider network. Input voltages at V1_FB and
V2_FB should be chosen to provide a feedback voltage, for the
required output regulated voltage, to equal the internal
regulator reference voltages of 2.5 V ±2%.
VVB+ (21 V to 42 V)
34920
VB+
V1_SWITCH
V1 Regulator
VV1
V1_FB
VB+
Oscillator
V2_SWITCH
VV2
V2 Regulator
V2_FB
ENABLE
VVB+ (21 V to 42 V)
Vb
Oscillator
Vb Generator
22 µF 25 V
CP1
CP2
10 nF 50 V
Figure 4. Voltage Regulator Functions
34920
20
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Voltage Regulator Output Requirements
Table 8 provides a listing of the output voltages and currents.
Both switchmode converters operate at approximately 200 kHz
±25 kHz.
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Table 8. Voltage Regulator Output Requirements
Voltage Name
Minimum Voltage
Maximum Voltage
Load Range
VV1
-4.0% of Nominal
+4.0% of Nominal
10 mA Min, 500 mA Max DC
VV2 (Note 11)
-2.0% of Nominal
+2.0% of Nominal
10 mA Min, 1.3 A Max DC
(Note 12)
Notes
11. This voltage is programmable within a range of 10 V to 15 V via external resistors. The voltage tolerance around
any set point is ±2% of the nominal.
12. Maximum peak duration is 400 ms.
The V1 and V2 regulators provide individual internal overtemperature sensing for protection. During an overtemperature
event, when the device TJ is at or above TJ(SHUTDOWN) , the
internal thermal protection circuit disables the drive outputs by
driving all outputs to the zero current state until the device
temperatures have dropped below the lower thermal threshold
temperature TJ(ENABLE), at which time the driver is re-enabled.
The V1 and V2 voltage regulators may be shut down by
applying a voltage in the range of 3.0 V to 6.0 V to the
respective V1_FB and V2_FB terminals. This will result in the
regulator output voltages to be equal to 0 V.
Overcurrent Protection
Output voltages VV1 and VV2 are short circuit protected. The
outputs respond to an overcurrent situation by limiting the
internal switching duty cycle. This can be reset by removing the
main supply to the chip or when the short circuit condition is
removed. Refer to the respective IOC and ISC values for V1 and
V2 voltage regulators on page 6 of the Static Electrical
Characteristics table.
Power-Saving Mode of Operation
The V2 voltage regulator can be disabled via the serial
interface by setting the V2_Enable bit (bit 1–LSB) to a value of
0. This provides a reduction in the bias current provided by the
V1 supply.
V1 Voltage Regulator
Implementation of the V1 switching voltage regulator is
accomplished through the use of an internal switch MOSFET,
internal MOSFET current sense resistor, external Schottky
diode, external inductor, and filter capacitor. The frequency of
operation of this regulator is controlled by the internal clock,
which is 200 kHz ±25 kHz. The duty cycle (on-time) for this
internal regulator clock is a fixed 37.5%. This regulator switches
out of phase from the V2 regulator to minimize ripple current on
VB+. The line regulation range is 21 V < VVB+ < 42 V. The load
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
side regulation is specified on page 6 of the Static Electrical
Characteristics table.
This converter is designed so that the current limit threshold
is lowered during the power-on period to allow for a “softer”
start-up, thereby reducing electrical stress in the external
components. This limiting is required for their safe operation.
The voltage is set externally with a resistor (1% tolerance)
divider network. The V1_FB input voltage should be chosen,
using external voltage divider resistors, so as to provide a
regulator feedback voltage, for the required output regulated
voltage, to equal the internal regulator reference voltage of
2.50 V ±2%. The V1 regulator is ideal for providing either 3.3 V
or 5.0 V with a precision of +5%/-4%.
Output current sensing is implemented by sensing the
voltage across an internal sense resistor connected between
VB+ and the drain of the internal MOSFET. Current is
measured on a cycle-by-cycle basis. The purpose of this
current sense is to prevent damage to the 34920 and its
associated external components.
V2 Voltage Regulator
The V2 switching voltage regulator is implemented as a buck
regulator with an internal switch MOSFET, internal MOSFET
current sense resistor, external Schottky diode, external
inductor, and filter capacitor. The frequency of operation of this
regulator is controlled by the internal clock, which is 200 kHz
±25 kHz. This regulator switches out of phase from the
V1 regulator to minimize ripple current on VB+.
This converter is designed so that the current limit threshold
is lowered during the power-on period to allow for a “softer”
start-up, thereby reducing electrical stress in the external
components. This limiting is required for their safe operation.
The output voltage is variable with ±2% precision, with a
VVB+ supply voltage range of 21 V to 42 V. The exact voltage
will be set externally with a resistor (1% tolerance) divider
network. The V2_FB input voltage should be chosen, using
external voltage divider resistors, so as to provide a regulator
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feedback voltage, for the required output regulated voltage, to
equal the internal regulator reference voltages of 2.50 V ±2%.
Output current sensing is implemented by sensing the
voltage across an internal sense resistor connected between
VB+ and the drain of the internal MOSFET. Current is
measured on a cycle-by-cycle basis. The purpose of this
current sense is to prevent any damage to the 34920 and its
associated external components.
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Note There is a V2_Enable bit in the Serial Communication
Input register (bit 1). When this bit is set to logic [1], the V2
voltage regulator is enabled. When this bit = logic [0], the V2
voltage regulator is disabled. Refer to Tables 3 through 7,
pp. 15–19, for a description of this bit. The V2_Enable bit will
also disable the motor drivers.
DR1PWM
DR1_MODE
Vb Generator
The boost voltage generator circuit is a charge pump circuit
using two external capacitors to provide the necessary voltage
to drive internal 34920 loads. This circuit is driven at a
frequency of 200 kHz ±25 kHz.
The Vb generator is utilized exclusively by the 34920. There
is no provision for external loading. Also, there is no disable
feature for the Vb generator.
Motor Drive Systems
The 34920 provides two motor drivers. Both drivers are
mode selectable to be either a multi-current level bi-directional
driver for bipolar step motors or a bi-directional DC motor driver
with PWM control. The DR1_MODE (Mode1) and DR2_MODE
(Mode2) terminals select whether the appropriate motor driver
will drive a step motor (terminal = 1) or DC motor (terminal = 0).
Figures 5 and 6 depict the two motor configurations.
34920
VB+
DR1
DR1A1
SDR1_DIR_PH A
Phase A H-Bridge
SDR1_CURR_I1 PHASEA
DR1B1
DR1SENSE1
SDR1_CURR_I0 PHASEA
Step
Motor
DR1_DIR_DCM
DR1A2
DR1B2
SDR1_DIR_PH_B
SDR1_CURR_I1_PHASEB
Phase B H-Bridge
DR1SENSE2
SDR1_CURR_I0_PHASEB
Figure 5. Simplified Step Application Diagram Showing 1 of 2 Step Drive Circuits
34920
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DR2PWM
DR2_MODE
34920
VB+
DR2
DR2A1
SDR2_DIR_PH A
Phase A H-Bridge
DR2B1
-
SDR2_CURR_I1 PHASEA
SDR2_CURR_I0 PHASEA
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+
DC
Motor
DR2_DIR_DCM
DR2A2
SDR2_DIR_PH_B
Phase B H-Bridge
DR2B2
SDR2_CURR_I1_PHASEB
SDR2_CURR_I0_PHASEB
Figure 6. Simplified DC Application Diagram Showing 1 of 2 Motor Drive Circuits
Bipolar Current Regulated Step Motor Drive System
The drive circuitry is powered by the VVB+ supply voltage.
For example, with external current sense resistors of 0.910 Ω
±1%, the drive circuitry provides drive for a bipolar step motor
at current levels of approximately 183 mA, 367 mA, and
550 mA. Current mode operation supports quarter stepping.
This drive enters the fast current decay mode when both the
CURR_I0_PHASEX and CURR_I1_PHASEX inputs are set to
the logic [1] level. In fast current decay mode, any residual
motor winding current is forced into the VVB+ supply rail when
going to a zero current state from a non-zero current level. This
forces the motor winding current toward zero as quickly as
possible.
For each of the two H-bridge drivers, controlled crossover
delay, a blanking period, and internal overtemperature sensing
are provided. The crossover delay is controlled to provide
sufficient time for cross-conduction suppression. At no time will
both the upper and lower output device on the same side of the
H-bridge be allowed to conduct simultaneously. Also, following
a turn-on event a blanking period is included to prevent false
turn-offs owing to the initial turn-on current spike, which results
from motor circuit capacitance.
This drive has internal overtemperature sensing for
protection. During an overtemperature event, when the device
TJ is at or above TJ(SHUTDOWN), the internal thermal protection
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
circuit disables the drive outputs by driving all outputs to the
zero current state until the device temperatures have dropped
below the lower thermal threshold temperature TJ(ENABLE), at
which time the driver is re-enabled.
Note During power-on the step motor driver circuit inhibits
its outputs when VVB+ is at 4.0 V or greater until RESET is
released. Likewise, during power-down the step motor driver
circuit inhibits its outputs from the point when RESET goes low
until VVB+ has dropped below 4.0 V.
DC Motor Drive System
This drive circuitry provides bi-directional drive to a DC motor
via two inputs, DCM_PWM (an external terminal, CMOScompatible input) and DRx_DIR_DCM (a bit in the serial input
port; refer to Tables 5 through 7, pp. 17–19). This drive is
powered from VB+. The DC motor control circuitry uses voltage
mode control.
To drive a DC motor the 34920 outputs DR2A1 and DR2A2
must be connected together externally, then connected to the
DC motor “+” lead. Likewise, the 34920 outputs DR2B1 and
DR2B2 must be connected together externally, then connected
to the DC motor “-“ lead (see Figure 6).
This drive provides internal overtemperature sensing for
protection. During an overtemperature event, when the device
TJ is at or above TJ(SHUTDOWN), the internal thermal protection
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34920
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circuit disables the drive outputs by driving both outputs to the
high state until the device temperatures have dropped below
the lower thermal threshold temperature TJ(ENABLE), at which
time the drive is re-enabled.
Freescale Semiconductor, Inc...
The crossover delay must be controlled to provide sufficient
time for cross-condition suppression. At no time can both the
upper and lower output devices on the same side of the
H-bridge be allowed to conduct simultaneously. Also, following
a turn-on event a blanking period is included to prevent false
turn-offs owing to the initial turn-on current spike, which results
from motor circuit capacitance.
Note During power-on the DC Motor Driver circuit inhibits its
outputs when VVB+ is at 4.0 V or greater until RESET is
released. Likewise, during power-down of the machine the DC
Motor Driver circuit inhibits its outputs from the point when
RESET goes low until VVB+ has dropped below 4.0 V.
RESET Functionality
The 34920 provides an output, RESET, that drives an
external reset signal to the system microprocessor and/or the
system digital logic IC. This signal is an active low logic level
signal that is derived by monitoring the level of the VCC terminal.
This output is the equivalent of an open drain- (or open
collector-) type output, with an internal 2.5 kΩ pull-up to VCC.
This output terminal can be driven by other external sources
and therefore the state of RESET must be monitored by the
34920.
Note When RESET is asserted either internally or from an
external source, all 34920 motor drive outputs will be in their
inactive states, and the serial input port will be loaded with the
“Reset Value” (refer to Tables 4 through 7). The V2 voltage
regulator will be enabled.
During power-up this output asserts a logic low level, and it
monitors the V1 regulator output voltage and detects the point
that it reaches VV1T+ . The output will then remain low for a delay
of 15 ms to 50 ms before releasing to a high state. A second
case is if VV1_FB is at or above VV1T+ for a period longer than
the delay period of tDELAY and VVB+ is still less than VVB+T- .
In this situation RESET will remain low until VVB+ is greater than
VVB+T- , at which point RESET will be released immediately and
there will be no delay period. If VVB+ passes through VVB+T+
during the tDELAY period, RESET will remain low until the end of
the tDELAY period, which started at the time VV1_FB passed
through the VV1T+ level.
During power-down this output immediately asserts a logic
low at the point when VV1_FB drops down to the trip point of
VV1T- . Also, if VVB+ drops below VVB+T- and VV1_FB is still at or
above VV1T- , RESET will be pulled low.
RESET Behavior
The following conditions describe the behavior of the RESET
circuit.
A Note on Terminology Assertion of RESET is defined as
the RESET terminal outputting a logic low voltage, and deassertion is when the terminal is pulled up to the VCC voltage.
On the power-up condition, RESET behaves as follows:
• If 1.0 V < VV1_FB < VV1T+ or VVB+ < VVB+T+ , RESET will be
asserted.
Important If VV1_FB < 1.0 V, RESET is undefined.
• If RESET is asserted owing to VV1_FB < VV1T- , then when
VV1_FB rises monotonically from below VV1T- to above
VV1T+ , RESET will de-assert after a duration of tDELAY.
• If RESET is asserted owing to VVB+ < VVB+T+ and VV1_FB
≥ VV1T+ , then when VVB+ rises to the VVB+T+ level RESET
will de-assert with no delay. The only case where a delay
would be seen is if the time period from where VV1_FB
rises to the VV1T+ level to the point where VVB+ rises to the
VVB+T+ level is less than the tDELAY period. Then the delay
in de-asserting RESET would be the remaining tDELAY
time, thereby maintaining the full tDELAY period, between
the time when VV1_FB reaches VV1T+ and the de-assertion
of RESET, that is required for a reliable system reset.
On the power-down condition, RESET behaves as follows:
• If RESET is not asserted, and the VV1_FB voltage
monotonically decreases to a value below the negativegoing threshold of VV1T- and remains below VV1T- for
longer than tPERSIST (10 µs to 30 µs), RESET will be
asserted. RESET will remain asserted while 1.0 V <
VV1_FB < VV1T+ . If VV1_FB falls below 1.0 V, the RESET
signal is undefined.
• RESET will also be asserted when VVB+ decreases below
the VVB+T+ level. This will occur even if the VV1_FB level is
still above VV1T- .
On the VV1_FB glitch condition, RESET behaves as follows:
• If the VV1_FB supply falls below VV1T- and remains there
for less than tPERSIST (10 µs to 30 µs), RESET will not be
asserted. However, if the condition lasts longer than
tPERSIST, RESET will be asserted for a duration of tDELAY.
34920
24
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Environmental Specifications
ESD Immunity
Refer to the Maximum Ratings table, page 5.
Ambient Temperature and Relative Humidity
Overtemperature Protection
Table 9 lists the temperature and relative humidity for
operating and storage conditions for the 34920.
Freescale Semiconductor, Inc...
Table 9. Ambient Temperature and Humidity
Condition
Temperature (°C)
% Relative Humidity
Operating
0 to 70
8.0 to 80
Storage
-40 to 150
5.0 to 80
The 34920 implements overtemperature detection and
shutdown functions. The overtemperature circuitry monitors the
device’s internal temperature and activates thermal shutdown
circuitry when the temperature exceeds TJ(SHUTDOWN) (155°C
minimum, 175°C maximum). The thermal shutdown condition is
maintained until the die temperature falls below TJ(ENABLE)
(135°C minimum, 155°C maximum). Each voltage regulator
and motor driver circuit has its own individual shutdown circuit.
APPLICATIONS
Logic Voltage (VCC) and Reset Interoperability
The 3.3 V or 5.0 V VV1 output voltage should feed back to the
VCC input terminal directly (see Figure 7) to ensure that the
34920 can be properly reset during a power-down situation. If
this typology is not the one implemented, the user needs to be
aware that the VCC terminal is not monitored for undervoltage.
Only the V1_FB and VB+ terminals are monitored for
undervoltage. Thus, it is possible for VCC to be under voltage
without the 34920 issuing a reset.
VVB+ (21 V to 42 V)
34920
VB+
VCC
V1_SWITCH
V1 Regulator
VV1
V1_FB
VB+
Oscillator
V2_SWITCH
VV2
V2 Regulator
V2_FB
ENABLE
VVB+ (21 V to 42 V)
Vb
Oscillator
Vb Generator
22 µF 25 V
CP1
CP2
10 nF 50 V
Figure 7. Voltage Regulator Functions
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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34920
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PACKAGE DIMENSIONS
EI (Pb-FREE) SUFFIX
FN SUFFIX
44-TERMINAL PLCC
PLASTIC PACKAGE
CASE 777-02
ISSUE C
-N-
Y
V
44
L-M
N
S
L-M
S
S
0.007(0.180) M T
U
N
S
Z
G1
0.010 (0.25)
X
W D
1
0.007(0.180) M T
B
D
-M-
-L-
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BRK
VIEW D-D
A
0.007(0.180) M T
L-M
S
N
S
R
0.007(0.180) M T
L-M
S
N
S
S
T
L-M
0.007(0.180) M T
H
S
L-M
S
N
S
N
N
S
S
Z
J
C
K1
E
0.004 (0.10)
G
-TG1
0.010 (0.25)
S
T
L-M
S
N
S
K
SEATING
PLANE
F
VIEW S
0.007(0.180) M T
L-M
S
VIEW S
NOTES:
1. DATUMS -L-, -M-, AND -N- ARE DETERMINED WHERE
TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT
MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE MEASURED
AT DATUM -T-, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.25) PER
SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE
BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY
MISMATCH BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940). THE
DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE SMALLER THAN 0.025 (0.635).
34920
26
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.685
0.695
0.685
0.695
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
--0.025
--0.650
0.656
0.650
0.656
0.042
0.048
0.042
0.048
0.042
0.056
--0.020
2°
10 °
0.610
0.630
0.040
---
MILLIMETERS
MIN
MAX
17.40
17.65
17.40
17.65
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
--0.64
--16.51
16.66
16.51
16.66
1.07
1.21
1.07
1.21
1.07
1.42
--0.50
2°
10°
15.50
16.00
1.02
---
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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NOTES
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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34920
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MC34920