SN54/74LS166 8-BIT SHIFT REGISTERS The SN54L/ 74LS166 is an 8-Bit Shift Register. Designed with all inputs buffered, the drive requirements are lowered to one 54/ 74LS standard load. By utilizing input clamping diodes, switching transients are minimized and system design simplified. The LS166 is a parallel-in or serial-in, serial-out shift register and has a complexity of 77 equivalent gates with gated clock inputs and an overriding clear input. The shift/load input establishes the parallel-in or serial-in mode. When high, this input enables the serial data input and couples the eight flip-flops for serial shifting with each clock pulse. Synchronous loading occurs on the next clock pulse when this is low and the parallel data inputs are enabled. Serial data flow is inhibited during parallel loading. Clocking is done on the low-to-high level edge of the clock pulse via a two input positive NOR gate, which permits one input to be used as a clock enable or clock inhibit function. Clocking is inhibited when either of the clock inputs are held high, holding either input low enables the other clock input. This will allow the system clock to be free running and the register stopped on command with the other clock input. A change from low-to-high on the clock inhibit input should only be done when the clock input is high. A buffered direct clear input overrides all other inputs, including the clock, and sets all flip-flops to zero. 8-BIT SHIFT REGISTERS LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 16 1 • Synchronous Load • Direct Overriding Clear • Parallel to Serial Conversion N SUFFIX PLASTIC CASE 648-08 16 1 PARALLEL PARALLEL INPUTS SHIFT/ INPUT OUTPUT H QH G VCC LOAD 16 15 14 13 12 F E CLEAR 11 10 9 F E D SUFFIX SOIC CASE 751B-03 16 1 SHIFT/ LOAD H QH G SERIAL INPUT 1 SERIAL INPUT A B C D 2 A 3 B 4 C 5 D CLEAR CLOCK INHIBIT CK ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD 8 6 7 CLOCK CLOCK GND INHIBIT Ceramic Plastic SOIC PARALLEL INPUTS FUNCTION TABLE INPUTS PARALLEL CLEAR SHIFT/ LOAD CLOCK INHIBIT CLOCK SERIAL L H H H H H X X L H H X X L L L L H X L ↑ ↑ ↑ ↑ X X X H L X A...H QA QB X X a...h X X X L QA0 a H L QA0 L QB0 b QAn QAn QB0 FAST AND LS TTL DATA 5-1 INTERNAL OUTPUTS OUTPUT QH L QH0 h QGn QGn QH0 SN54/74LS166 Typical Clear, Shift, Load, Inhibit, and Shift Sequences CLOCK CLOCK INIHIBIT CLEAR SERIAL INPUT SHIFT/LOAD PARALLEL INPUTS A H B L C H L D E H L F G H H H OUTPUT QH INHIBIT SERIAL SHIFT CLEAR H H L LOAD (9) CLEAR (1) SERIAL INPUT (15) SHIFT/LOAD (2) A R CK S QA B (3) R CK S QB C (4) R CK S QC D (5) R E S QD (10) R F CK CK S QE (11) R CK S QF (12) G R CK S QG H CLOCK CLOCK INHIBIT (14) (7) R (6) CK S (13) Q H FAST AND LS TTL DATA 5-2 H L H L SERIAL SHIFT H SN54/74LS166 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 74 4.5 4.75 5.0 5.0 5.5 5.25 V TA Operating Ambient Temperature Range 54 74 – 55 0 25 25 125 70 °C IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 74 4.0 8.0 mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Min Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIH Input HIGH Current IIL Input LOW Current IOS Short Circuit Current (Note 1) ICC Power Supply Current Typ Max Unit 2.0 54 0.7 74 0.8 – 0.65 – 1.5 Test Conditions V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN, IIN = – 18 mA 54 2.5 3.5 V 74 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table 54, 74 0.25 0.4 V IOL = 4.0 mA 74 0.35 0.5 V IOL = 8.0 mA 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V – 0.4 mA VCC = MAX, VIN = 0.4 V – 100 mA VCC = MAX 38 mA VCC = MAX – 20 Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 5-3 SN54/74LS166 TEST TABLE FOR SYNCHRONOUS INPUTS DATA INPUT FOR TEST SHIFT/LOAD OUTPUT TESTED H 0V QH at tn+1 Serial Input 4.5 V QH at tn+8 AC WAVEFORMS tw(clear) CLEAR INPUT 3V Vref Vref 0V tn + 1 tn (SEE NOTE 1) tn tn + 1 3V Vref CLOCK INPUT tsu tw(clock) DATA INPUT (SEE TEST TABLE) Vref Vref Vref Vref 0V th tsu th 3V Vref Vref 0V tPHL (clear-Q) Vref OUTPUT Q tPHL (CLK-Q) tPLH (CLK-Q) VOH Vref Vref VOL NOTE 1. tn = bit time before clocking transition NOTE 1. tn+1 = bit time after one clocking transition NOTE 1. tn+8 = bit time after eight clocking transition NOTE 1. LS166 Vref = 1.3 V. AC CHARACTERISTICS (TA = 25°C) Limits Symbol Parameter Min Typ 25 35 Max Unit fMAX Maximum Clock Frequency tPHL Clear to Output 19 30 ns Clock to Output 23 24 35 35 ns Max Unit tPLH tPHL Test Conditions MHz VCC = 5.0 V CL = 15 pF AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol Parameter Min Typ tW Clock Clear Pulse Width 30 ns ts Mode Control Setup Time 30 ns ts Data Setup Time 20 ns th Hold Time, Any Input 15 ns FAST AND LS TTL DATA 5-4 Test Conditions VCC = 5.0 V