ETC UPD78P018FGK-8A8

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD78P018F
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The µPD78P018F is a member of the µPD78018F Subseries within the 78K/0 Series. The internal mask ROM of
the µPD78018F is replaced with one-time PROM or EPROM.
Because the µPD78P018F can be programmed by users, it is suited for applications involving the evaluation of
systems in development stages, small-scale production of many different products, and rapid development and timeto-market of new products.
The µ PD78P018FDW and 78P018FKK-S are not guaranteed to maintain the reliability level required
Caution
for mass production of the customer’s devices.
Use only experimentally or for evaluation
purposes during trial manufacture.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
µPD78018F, 78018FY Subseries User's Manual: U10659E
78K/0 Series User's Manual–Instructions: U12326E
FEATURES
• Pin compatible with mask ROM version (except VPP pin)
• Internal PROM: 60 Kbytes Note 1
µPD78P018FDW, 78P018FKK-S: Re-programmable (suited for system evaluation)
µPD78P018FCW, 78P018FGC-AB8, 78P018FGK-8A8: Programmable only once (suited for small-scale production)
• Internal high-speed RAM: 1024 bytes Note 1
• Internal expansion RAM: 1024 bytes Note 2
• Internal buffer RAM: 32 bytes
• Operable over same supply voltage range as mask ROM version: VDD = 1.8 to 5.5 V (except an A/D converter)
• QTOPTM microcontroller supported
Notes 1. The capacities of internal PROM and internal high-speed RAM can be changed by means of the internal
memory size switching register (IMS).
2. The capacity of the internal expansion RAM can be changed by means of the internal expansion RAM size
switching register (IXS).
Remarks 1. QTOP Microcontroller is a general term for microcontrollers that incorporate one-time PROM and are totally
supported by NEC's programming service (from programming to marking, screening and verification).
2. For differences between the PROM version and mask ROM versions, refer to 1. DIFFERENCES
BETWEEN µPD78P018F AND MASK ROM VERSIONS.
In this document, the term PROM is used in parts common to one-time PROM versions and EPROM versions.
The information in this document is subject to change without notice.
Document No. U10955EJ3V0DS00 (3rd edition)
Date Published November 1998 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1994
µPD78P018F
ORDERING INFORMATION
Part Number
Package
Internal ROM
µ PD78P018FCW
64-pin plastic shrink DIP (750 mils)
One-time PROM
µ PD78P018FDW
64-pin ceramic shrink DIP (with window) (750 mils)
EPROM
µ PD78P018FGC-AB8
64-pin plastic QFP (14 × 14 mm)
One-time PROM
µ PD78P018FGK-8A8
64-pin plastic LQFP (12 × 12 mm)
One-time PROM
µ PD78P018FKK-S
64-pin ceramic WQFN (14 × 14 mm)
EPROM
QUALITY GRADE
Part Number
Package
Quality Grade
µ PD78P018FCW
64-pin plastic shrink DIP (750 mils)
Standard
µ PD78P018FDW
64-pin ceramic shrink DIP (with window) (750 mils)
Not applicable
µ PD78P018FGC-AB8
64-pin plastic QFP (14 × 14 mm)
Standard
µ PD78P018FGK-8A8
64-pin plastic LQFP (12 × 12 mm)
Standard
µ PD78P018FKK-S
64-pin ceramic WQFN (14 × 14 mm)
Not applicable
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number C11531E) published by NEC
Corporation to know the specification of quality grade on the devices and its recommended applications.
2
µPD78P018F
78K/0 SERIES LINEUP
The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries names.
Products in
mass production
Products under
development
Y subseries products are compatible with I2C bus.
Control
100-pin
100-pin
100-pin
100-pin
80-pin
80-pin
80-pin
80-pin
64-pin
64-pin
64-pin
64-pin
42/44-pin
µPD78075B
µPD78078
µ PD78070A
µ PD780058
µ PD78058F
µ PD78054
µ PD780065
µ PD780034
µ PD780024
µ PD78014H
µPD78018F
µPD78083
EMI-noise reduced version of the µPD78078
µPD78078Y
µPD78070AY
µ PD780018AY
µ PD780058YNote
µ PD78058FY
µ PD78054Y
µ PD780034Y
µPD780024Y
µ PD78018FY
Timer was added to the µPD78054 and external interface was enhanced
ROM-less version of the µPD78078
Serial I/O of the µPD78078Y was enhanced and the function is limited
Serial I/O of the µPD78054 was enhanced and EMI-noise was reduced
EMI-noise reduced version of the µPD78054
UART and D/A converter were added to the µPD78018F and I/O was enhanced
RAM capacity of µPD780024 was expanded
A/D converter of the µPD780024 was enhanced
Serial I/O of the µPD78018F was enhanced
EMI-noise reduced version of the µPD78018F
Basic subseries for control
On-chip UART, capable of operating at low voltage (1.8 V)
Inverter control
64-pin
78K/0
Series
µ PD780988
On-chip inverter control circuit and UART. EMI-noise was reduced
FIPTM drive
100-pin
100-pin
80-pin
80-pin
80-pin
I/O and FIP C/D of the µPD78044F were enhanced, Display output total: 53
I/O and FIP C/D of the µPD78044H were enhanced, Display output total: 48
For panel control. On-chip FIP C/D. Display output total: 53
µPD780208
µ PD780228
µ PD780232
µPD78044H
µPD78044F
N-ch open drain was added to the µPD78044F, Display output total: 34
Basic subseries for driving FIP, Display output total: 34
LCD drive
100-pin
µ PD780308
µPD780308Y
SIO of the µPD78064 was enhanced and ROM, RAM capacity expanded
100-pin
100-pin
µ PD78064B
µPD78064
µ PD78064Y
EMI-noise reduced version of the µPD78064
Basic subseries for driving LCDs, On-chip UART
Bus interface supported
80-pin
80-pin
80-pin
80-pin
µPD78098B
µ PD780948
µ PD780701Y
µ PD780833Y
IEBusTM controller is added to µPD78054. EMI-noise was reduced.
On-chip DCAN controller
On-chip DCAN/IEBus controller
On-chip J1850 (CLASS2) controller
Meter control
80-pin
µ PD780973
80-pin
100-pin
µPD780955
µPD780958
On-chip controller/driver for automotive meter drive
Ultra-low power consumption and on-chip UART
For industrial meter control
Note Under planning
3
µPD78P018F
The major functional differences among subseries are shown below.
Function
I/O
VDD
External
MIN.
Expansion
Value
2 ch 3 ch (UART: 1 ch)
88
1.8 V Available
61
2.7 V
µPD780058 24 K to 60 K 2 ch
3 ch (time-division
UART: 1 ch)
68
1.8 V
µPD78058F 48 K to 60 K
3 ch (UART: 1 ch)
69
2.7 V
4 ch (UART: 1 ch)
60
2.7 V
3 ch (UART: 1 ch, time- 51
1.8 V
Subseries Name
Control
Timer
ROM
Capacity
8-bit 10-bit 8-bit
8-bit 16-bit Watch WDT
A/D
µPD78075B 32 K to 40 K 4 ch 1 ch 1 ch 1 ch 8 ch
µPD78078
—
D/A
48 K to 60 K
µPD78070A
µPD78054
A/D
Serial Interface
—
16 K to 60 K
2.0 V
µPD780065 40 K to 48 K
—
µPD780034 8 K to 32 K
—
µPD780024
8 ch
8 ch
division 3-wire: 1 ch)
—
µPD78014H
2 ch
53
1 ch (UART: 1 ch)
33
µPD78018F 8 K to 60 K
µPD78083
8 K to 16 K
—
—
Inverter
control
µPD780988 16 K to 60 K 3 ch Note
FIP drive
µPD780208 32 K to 60 K 2 ch 1 ch 1 ch 1 ch 8 ch
µPD780228 48 K to 60 K 3 ch
—
—
1 ch
—
8 ch
—
3 ch (UART: 2 ch)
47
4.0 V Available
—
—
2 ch
74
2.7 V
1 ch
72
4.5 V
—
—
µPD780232 16 K to 24 K
4 ch
2 ch
40
µPD78044H 32 K to 48 K 2 ch 1 ch 1 ch
8 ch
1 ch
68
2.7 V
57
2.0 V
—
69
2.7 V
—
79
4.0 V
µPD78044F 16 K to 40 K
2 ch
LCD drive µPD780308 48 K to 60 K 2 ch 1 ch 1 ch 1 ch 8 ch
—
—
µPD78064B 32 K
µPD78064
3 ch (time-division
UART: 1 ch)
2 ch (UART: 1 ch)
16 K to 32 K
Bus interface µPD78098B 40 K to 60 K 2 ch 1 ch 1 ch 1 ch 8 ch
supported µPD780948 60 K
Meter
µPD780973 24 K to 32 K 3 ch 1 ch 1 ch 1 ch 5 ch
µPD780955 40 K
6 ch
10-bit timer: 1 channel
2 ch 3 ch (UART: 1 ch)
—
control
Note 16-bit timer: 2 channels
—
2 ch
µPD780958 48 K to 60 K 4 ch 2 ch
4
—
—
2 ch (UART: 1 ch)
56
4.5 V
1 ch
—
—
2 ch (UART: 2 ch)
50
2.2 V
—
2 ch (UART: 1 ch)
69
—
µPD78P018F
FUNCTION OVERVIEW
Item
Internal
memory
Function
Note 1
PROM
60 Kbytes
High-speed RAM
1024 bytes
Note 1
Expansion RAM
1024 bytes
Note 2
Buffer RAM
32 bytes
Memory space
64 Kbytes
General-purpose registers
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution
time
When main system
Minimum instruction execution time cycle modification function provided.
0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs (@10.0-MHz operation)
clock selected
When subsystem
122 µs (@32.768-kHz operation)
clock selected
Instruction set
•
•
•
•
I/O ports
Total:
• CMOS input:
• CMOS I/O:
• N-channel open-drain I/O (15-V withstand voltage):
A/D converter
• 8-bit resolution × 8 channels
• Operable over a wide power supply voltage range: VDD = 2.2 to 5.5 V
Serial interface
16-bit operation
Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)
Bit manipulate (set, reset, test, Boolean operation)
BCD adjust, etc.
53
2
47
4
• 3-wire serial I/O/SBI/2-wire serial I/O mode selectable: 1 channel
• 3-wire serial I/O mode (on-chip max. 32 bytes automatic data transmit/receive function): 1 channel
Timer
•
•
•
•
Timer output
3 (14-bit PWM output × 1)
Clock output
16-bit timer/event counter:
8-bit timer/event counter:
Watch timer:
Watchdog timer:
1 channel
2 channels
1 channel
1 channel
39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz (@10.0-MHz operation with main
system clock), 32.768 kHz (@32.768-kHz operation with subsystem clock)
Buzzer output
2.4 kHz, 4.9 kHz, 9.8 kHz (@10.0-MHz operation with main system clock)
Vectored
interrupt
source
Maskable
Internal: 8, External: 4
Non-maskable
Internal: 1
Software
1
Test input
Internal: 1, External: 1
Supply voltage
VDD = 1.8 to 5.5 V
Operating ambient temperature TA = –40 to +85°C
Package
•
•
•
•
•
64-pin
64-pin
64-pin
64-pin
64-pin
plastic shrink DIP (750 mils)
ceramic shrink DIP (with window) (750 mils)
plastic QFP (14 × 14 mm)
plastic LQFP (12 × 12 mm)
ceramic WQFN (14 × 14 mm)
Notes 1. The internal PROM and internal high-speed RAM capacities can be changed with the internal memory
size switching register (IMS).
2. The internal expansion RAM capacity can be changed with the internal expansion RAM size switching
register (IXS).
5
µPD78P018F
PIN CONFIGURATION (Top View)
(1) Normal operating mode
• 64-pin Plastic Shrink DIP (750 mils)
µPD78P018FCW
• 64-pin Ceramic Shrink DIP (with window) (750 mils)
µPD78P018FDW
P20/SI1
1
64
AV REF
P21/SO1
2
63
AV DD
P22/SCK1
3
62
P17/ANI7
P23/STB
4
61
P16/ANI6
P24/BUSY
5
60
P15/ANI5
P25/SI0/SB0
6
59
P14/ANI4
P26/SO0/SB1
7
58
P13/ANI3
P27/SCK0
8
57
P12/ANI2
P30/TO0
9
56
P11/ANI1
P31/TO1
10
55
P10/ANI0
P32/TO2
11
54
AV SS
P33/TI1
12
53
P04/XT1
P34/TI2
13
52
XT2
P35/PCL
14
51
V PP
P36/BUZ
15
50
X1
P37
16
49
X2
V SS
17
48
V DD
P40/AD0
18
47
P03/INTP3
P41/AD1
19
46
P02/INTP2
P42/AD2
20
45
P01/INTP1
P43/AD3
21
44
P00/INTP0/TI0
P44/AD4
22
43
RESET
P45/AD5
23
42
P67/ASTB
P46/AD6
24
41
P66/WAIT
P47/AD7
25
40
P65/WR
P50/A8
26
39
P64/RD
P51/A9
27
38
P63
P52/A10
28
37
P62
P53/A11
29
36
P61
P54/A12
30
35
P60
P55/A13
31
34
P57/A15
V SS
32
33
P56/A14
Cautions 1. Connect VPP pin directly to VSS.
2. Connect AVDD pin to VDD.
3. Connect AVSS pin to VSS.
6
µPD78P018F
• 64-pin Plastic QFP (14 × 14 mm)
µPD78P018FGC-AB8
• 64-pin Plastic LQFP (12 × 12 mm)
µPD78P018FGK-8A8
• 64-pin Ceramic WQFN (14 × 14 mm)
P27/SCK0
P26/SO0/SB1
P25/SI0/SB0
P24/BUSY
P23/STB
P22/SCK1
P21/SO1
P20/SI1
AV REF
AV DD
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P13/ANI3
P12/ANI2
µPD78P018FKK-S
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
5
44
XT2
P35/PCL
6
43
V PP
P36/BUZ
7
42
X1
P37
8
41
X2
V SS
9
40
V DD
P40/AD0
10
39
P03/INTP3
P41/AD1
11
38
P02/INTP2
P42/AD2
12
37
P01/INTP1
P43/AD3
13
36
P00/INTP0/TI0
P44/AD4
14
35
RESET
P45/AD5
15
34
P67/ASTB
P46/AD6
16
17
P66/WAIT
18
19
20
21
22
23
24
25
26
27
28
29
30
31
33
32
P65/WR
P34/TI2
P64/RD
P04/XT1
P63
45
P62
4
P61
P33/TI1
P60
AV SS
P57/A15
46
P56/A14
3
V SS
P32/TO2
P55/A13
P10/ANI0
P54/A12
47
P53/A11
2
P52/A10
P31/TO1
P51/A9
P11/ANI1
P50/A8
1
P47/AD7
P30/TO0
Cautions 1. Connect VPP pin directly to VSS.
2. Connect AVDD pin to VDD.
3. Connect AVSS pin to VSS.
7
µPD78P018F
A8 to A15:
8
Address Bus
PCL:
Programmable Clock
AD0 to AD7:
Address/Data Bus
RESET:
Reset
ANI0 to ANI7:
Analog Input
RD:
Read Strobe
ASTB:
Address Strobe
SB0, SB1:
Serial Bus
AVDD:
Analog Power Supply
SCK0, SCK1:
Serial Clock
AVREF:
Analog Reference Voltage
SI0, SI1:
Serial Input
AVSS:
Analog Ground
SO0, SO1:
Serial Output
BUSY:
Busy
STB:
Strobe
BUZ:
Buzzer Clock
TI0 to TI2:
Timer Input
INTP0 to INTP3:
Interrupt from Peripherals
TO0 to TO2:
Timer Output
P00 to P04:
Port 0
VDD:
Power Supply
P10 to P17:
Port 1
VPP:
Programming Power Supply
P20 to P27:
Port 2
VSS:
Ground
P30 to P37:
Port 3
WAIT:
Wait
P40 to P47:
Port 4
WR:
Write Strobe
P50 to P57:
Port 5
X1, X2:
Crystal (Main System Clock)
P60 to P67:
Port 6
XT1, XT2:
Crystal (Subsystem Clock)
µPD78P018F
(2) PROM programming mode
• 64-pin Plastic Shrink DIP (750 mils)
µPD78P018FCW
• 64-pin Ceramic Shrink DIP (with window) (750 mils)
µPD78P018FDW
1
64
V SS
2
63
V DD
3
62
4
61
5
60
6
59
7
58
8
57
D0
9
56
D1
10
55
D2
11
54
V SS
D3
12
53
(L)
D4
13
52
Open
D5
14
51
V PP
D6
15
50
(L)
D7
16
49
Open
V SS
17
48
V DD
A0
18
47
(L)
A1
19
46
PGM
A2
20
45
(L)
A3
21
44
A9
A4
22
43
RESET
A5
23
42
A6
24
41
A7
25
40
CE
A8
26
39
OE
A16
27
38
A10
28
37
A11
29
36
A12
30
35
A13
31
34
A15
V SS
32
33
A14
(L)
Cautions 1. (L):
2. VSS:
(L)
(L)
(L)
Independently connect to VSS via a pull-down resistor.
Connect to GND.
3. RESET: Set to low level.
4. Open:
Leave open.
9
µPD78P018F
• 64-pin Plastic QFP (14 × 14 mm)
µPD78P018FGC-AB8
• 64-pin Plastic LQFP (12 × 12 mm)
µPD78P018FGK-8A8
63
62
61
60
59
58
57
56
55
(L)
V DD
64
(L)
µPD78P018FKK-S
V SS
• 64-pin Ceramic WQFN (14 × 14 mm)
D0
1
54
53
52
51
50
49
48
D1
2
47
D2
3
46
V SS
D3
4
45
(L)
D4
5
44
Open
D5
6
43
V PP
D6
7
42
(L)
D7
8
41
Open
V SS
9
40
V DD
A0
10
39
(L)
A1
11
38
PGM
A2
12
37
(L)
A3
13
36
A9
A4
14
35
RESET
A5
15
34
A6
16
17
(L)
Cautions 1. (L):
2. VSS:
21
22
23
24
25
26
A16
A10
A11
A12
A13
V SS
A14
A15
27
28
29
30
31
CE
20
OE
19
(L)
18
A8
A7
(L)
33
32
Independently connect to VSS via a pull-down resistor.
Connect to GND.
3. RESET: Set to low level.
4. Open:
10
Leave open.
A0 to A16:
Address Bus
RESET:
Reset
CE:
Chip Enable
VDD:
Power Supply
D0 to D7:
Data Bus
VPP:
Programming Power Supply
OE:
Output Enable
VSS :
Ground
PGM:
Program
µPD78P018F
BLOCK DIAGRAM
TO0/P30
TI0/INTP0/P00
P00
16-bit TIMER/
EVENT COUNTER
PORT0
P01-P03
P04
TO1/P31
TI1/P33
TO2/P32
TI2/P34
8-bit TIMER/
EVENT COUNTER 1
8-bit TIMER/
EVENT COUNTER 2
WATCHDOG TIMER
WATCH TIMER
78K/0
CPU CORE
SI0/SB0/P25
SO0/SB1/P26
PORT1
P10-P17
PORT2
P20-P27
PORT3
P30-P37
PORT4
P40-P47
PORT5
P50-P57
PORT6
P60-P67
PROM
(60 Kbytes)
SERIAL
INTERFACE 0
SCK0/P27
SI1/P20
SO1/P21
SCK1/P22
AD0/P40AD7/P47
SERIAL
INTERFACE 1
STB/P23
BUSY/P24
ANI0/P10ANI7/P17
AVDD
A8/P50A15/P57
RAM
(2048 bytes)
EXTERNAL
ACCESS
RD/P64
WR/P65
WAIT/P66
A/D CONVERTER
AVSS
ASTB/P67
AVREF
RESET
INTP0/P00INTP3/P03
INTERRUPT
CONTROL
X1
SYSTEM
CONTROL
X2
XT1/P04
BUZ/P36
BUZZER OUTPUT
PCL/P35
CLOCK OUTPUT
CONTROL
XT2
VDD
VSS
VPP
11
µPD78P018F
CONTENTS
1.
DIFFERENCES BETWEEN µPD78P018F AND MASK ROM VERSIONS ................................... 13
2.
PIN FUNCTIONS .............................................................................................................................. 14
2.1
Pins During Normal Operating Mode ................................................................................................... 14
2.2
Pins During PROM Programming Mode .............................................................................................. 16
2.3
Pin I/O Circuits and Recommended Connection of Unused Pins ................................................... 17
3.
INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) ......................................................... 19
4.
INTERNAL EXPANSION RAM SIZE SWITCHING REGISTER (IXS) ........................................... 20
5.
PROM PROGRAMMING .................................................................................................................. 21
5.1
Operating Modes ..................................................................................................................................... 21
5.2
PROM Write Procedure .......................................................................................................................... 23
5.3
PROM Read Procedure .......................................................................................................................... 27
6.
PROGRAM ERASURE (FOR µPD78P018FDW, 78P018FKK-S) .................................................. 28
7.
OPAQUE FILM ON ERASURE WINDOW (FOR µPD78P018FDW, 78P018FKK-S) ................... 28
8.
ONE-TIME PROM VERSION SCREENING .................................................................................... 28
9.
ELECTRICAL SPECIFICATIONS .................................................................................................... 29
10. CHARACTERISTIC CURVE (REFERENCE VALUE) .................................................................... 58
11. PACKAGE DRAWINGS ................................................................................................................... 59
12. RECOMMENDED SOLDERING CONDITIONS .............................................................................. 64
APPENDIX A. DEVELOPMENT TOOLS .............................................................................................. 65
APPENDIX B. RELATED DOCUMENTS .............................................................................................. 71
12
µPD78P018F
1. DIFFERENCES BETWEEN µPD78P018F AND MASK ROM VERSIONS
The µPD78P018F is a single-chip microcontroller with an on-chip one-time PROM or EPROM that has program
write, erase, and rewrite capability.
It is possible to make all the functions except for PROM specification and mask option of P60 to P63 pins, the same
as those of mask ROM versions (µPD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, and 78018F) by setting
the internal memory size switching register (IMS) and the internal expansion RAM size switching register (IXS).
Differences between the µPD78P018F and mask ROM versions are shown in Table 1-1.
Table 1-1. Differences between µPD78P018F and Mask ROM Versions
µPD78P018F
Parameter
Mask ROM Versions
Internal ROM type
One-time PROM or EPROM
Mask ROM
Internal ROM capacity
60 Kbytes
µPD78011F:
µPD78012F:
µPD78013F:
µPD78014F:
µPD78015F:
µPD78016F:
µPD78018F:
8 Kbytes
16 Kbytes
24 Kbytes
32 Kbytes
40 Kbytes
48 Kbytes
60 Kbytes
Internal high-speed RAM capacity
1024 bytes
µPD78011F:
µPD78012F:
µPD78013F:
µPD78014F:
µPD78015F:
µPD78016F:
µPD78018F:
512 bytes
512 bytes
1024 bytes
1024 bytes
1024 bytes
1024 bytes
1024 bytes
Internal expansion RAM capacity
1024 bytes
µPD78011F:
µPD78012F:
µPD78013F:
µPD78014F:
µPD78015F:
µPD78016F:
µPD78018F:
Internal ROM, internal high-speed RAM capacity changeable
with internal memory size switching register (IMS)
Yes Note 1
No
Internal expansion RAM capacity changeable with
internal expansion RAM size switching register (IXS)
Yes Note 2
No
IC pin
No
Yes
VPP pin
Yes
No
Mask option of P60 to P63 pins
Pull-up resistor is not
incorporated.
Pull-up resistor can be
incorporated by mask option.
Electrical specifications, recommended soldering conditions
See respective data sheet of individual products.
No
No
No
No
512 bytes
512 bytes
1024 bytes
Notes 1. The internal PROM capacity becomes 60 Kbytes and the internal high-speed RAM capacity becomes 1024
bytes by input of RESET.
2. The internal expansion RAM capacity becomes 1024 bytes by input of RESET.
Caution
There are differences in noise immunity and noise radiation between the PROM and mask ROM
versions. When pre-producing an application set with the PROM version and then mass-producing
it with the mask ROM version, be sure to conduct sufficient evaluations for the commercial
samples (not engineering samples) of the mask ROM version.
13
µPD78P018F
2. PIN FUNCTIONS
2.1 Pins During Normal Operating Mode
(1) Port Pins (1/2)
Pin Name
I/O
Function
P00
Input
P01
Input/ 5-bit I/O port
output
P02
Port 0
Note 1
Input
Alternate
Function
Input only
Input
INTP0/TI0
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be
Input
INTP1
INTP2
connected by software.
P03
P04
After
Reset
Input
XT1
Input/ Port 1
output 8-bit input/output port.
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be connected by
software. Note 2
Input
ANI0 to ANI7
P20
Input/
Input
SI1
P21
output 8-bit input/output port.
Input/output can be specified in 1-bit units.
P10 to P17
P22
Input only
INTP3
Port 2
SO1
SCK1
When used as an input port, an on-chip pull-up resistor can be connected by
software.
P23
STB
P24
BUSY
P25
SI0/SB0
P26
SO0/SB1
P27
SCK0
P30
Input/ Port 3
output 8-bit input/output port.
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be connected by
P31
P32
P33
Input
TO0
TO1
TO2
TI1
software.
P34
TI2
P35
PCL
P36
BUZ
P37
—
P40 to P47
Input/ Port 4
output 8-bit input/output port.
Input/output can be specified in 8-bit units.
When used as an input port, an on-chip pull-up resistor can be connected by
software.
Test input flag (KRIF) is set to 1 by falling edge detection.
Input
AD0 to AD7
Notes 1. When using the P04/XT1 pin as an input port, set bit 6 (FRC) of the processor clock control register (PCC)
to 1. Do not use the internal feedback resistor of the subsystem clock oscillator.
2. When using the P10/ANI0 to P17/ANI7 pins as the A/D converter analog input, set port 1 to input mode.
This causes the internal pull-up resistor is automatically disabled.
14
µPD78P018F
(1) Port Pins (2/2)
Pin Name
P50 to P57
I/O
Function
Input/ Port 5
output 8-bit input/output port.
LEDs can be driven directly.
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be connected by
After
Reset
Input
Alternate
Function
A8 to A15
software.
P60
P61
Input/ Port 6
output 8-bit input/output port.
N-ch open-drain input/output port.
LEDs can be driven directly.
Input
—
Input/output can be specified in
P62
1-bit units.
P63
P64
When used as an input port, an on-chip
RD
P65
pull-up resistor can be connected by
WR
P66
software.
WAIT
P67
ASTB
(2) Non-port Pins (1/2)
Pin Name
INTP0
I/O
Input/
INTP1
Function
External interrupt request input by which the valid edge (rising edge, falling
edge, or both rising edge and falling edge) can be specified.
After
Reset
Input
P02
INTP3
Falling edge detection external interrupt request input.
Input
Serial interface serial data input.
P03
Input
SI1
SO0
P25/SB0
P20
Output Serial interface serial data output.
Input
SO1
SB0
P00/TI0
P01
INTP2
SI0
Alternate
Function
P26/SB1
P21
Input/ Serial interface serial data input/output.
output
Input
Input
P27
SCK1
Input/ Serial interface serial clock input/output.
output
STB
Output Serial interface automatic transmit/receive strobe output.
Input
P23
BUSY
Input
Serial interface automatic transmit/receive busy input.
Input
P24
TI0
Input
External count clock input to 16-bit timer (TM0).
Input
P00/INTP0
SB1
SCK0
P25/SI0
P26/SO0
P22
TI1
External count clock input to 8-bit timer (TM1).
P33
TI2
External count clock input to 8-bit timer (TM2).
P34
TO0
Output 16-bit timer (TM0) output (shared as 14-bit PWM output).
Input
P30
TO1
8-bit timer (TM1) output.
P31
TO2
8-bit timer (TM2) output.
P32
PCL
Output Clock output (for main system clock, subsystem clock trimming).
Input
P35
BUZ
Output Buzzer output.
Input
P36
15
µPD78P018F
(2) Non-port Pins (2/2)
Pin Name
I/O
AD0 to AD7
Input/
Function
Low-order address/data bus at external memory expansion.
After
Reset
Alternate
Function
Input
P40 to P47
output
A8 to A15
Output High-order address bus at external memory expansion.
Input
P50 to P57
RD
Output External memory read operation strobe signal output.
Input
P64
WR
External memory write operation strobe signal output.
Wait insertion at external memory access.
P65
WAIT
Input
Input
P66
ASTB
Output Strobe output which latches the address information output at port 4 and port 5 Input
to access external memory.
P67
ANI0 to ANI7 Input
A/D converter analog input.
AVREF
Input
A/D converter reference voltage input.
—
—
AVDD
—
A/D converter analog power supply. Connect to VDD.
—
—
—
AVSS
Input
P10 to P17
A/D converter ground potential. Connect to VSS.
—
—
RESET
Input
System reset input.
—
—
X1
Input
Main system clock oscillation crystal connection.
—
—
X2
—
—
—
XT1
Input
XT2
—
VDD
—
VPP
VSS
Subsystem clock oscillation crystal connection.
Input
P04
—
—
Positive power supply.
—
—
—
High voltage applied during program write/verify. In normal operating mode,
connect to VSS directly.
—
—
—
Ground potential.
—
—
2.2 Pins During PROM Programming Mode
Pin Name
I/O
Function
RESET
Input
Sets PROM programming mode.
When +5 V or +12.5 V is applied to the VPP and low level is applied to RESET pin, microcontroller is
shifted to PROM programming mode.
VPP
Input
Applies high voltage during PROM programming mode setting and program write/verify.
A0 to A16
Input
Address bus
D0 to D7
Input/ Data bus
output
CE
Input
PROM enable input/program pulse input.
OE
Input
Read strobe input to PROM.
PGM
Input
Program/program inhibit input in PROM programming mode.
VDD
—
Positive power supply
VSS
—
Ground potential
16
µPD78P018F
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 2-1.
For the input/output circuit configuration of each type, see Figure 2-1.
Table 2-1. Types of Pin I/O Circuits
Pin Name
Input/output
Circuit Type
I/O
Recommended Connection when Not Used
P00/INTP0/TI0
2
Input
Connect to VSS .
P01/INTP1
8-A
Input/output
Independently connect to VSS via a resistor.
P04/XT1
16
Input
Connect to VDD.
P10/ANI0 to P17/ANI7
11
Input/output
Independently connect to VDD or VSS via a resistor.
P20/SI1
8-A
P21/SO1
5-A
P22/SCK1
8-A
P23/STB
5-A
P24/BUSY
8-A
P25/SI0/SB0
10-A
P02/INTP2
P03/INTP3
P26/SO0/SB1
P27/SCK0
P30/TO0
5-A
P31/TO1
P32/TO2
P33/TI1
8-A
P34/TI2
P35/PCL
5-A
P36/BUZ
P37
P40/AD0 to P47/AD7
5-E
Independently connect to VDD via a resistor.
P50/A8 to P57/A15
5-A
Independently connect to VDD or VSS via a resistor.
P60 to P63
13-D
Independently connect to VDD via a resistor.
P64/RD
5-A
Independently connect to VDD or VSS via a resistor.
P65/WR
P66/WAIT
P67/ASTB
RESET
2
XT2
16
AV REF
Input
—
—
—
Leave open.
Connect to VSS .
AV DD
Connect to VDD .
AV SS
Connect to VSS .
VPP
Connect directly to VSS.
17
µPD78P018F
Figure 2-1. Pin Input/Output Circuits
V DD
Type 10-A
Type 2
pullup
enable
P-ch
V DD
IN
data
P-ch
IN/OUT
open drain
output disable
N-ch
Schmitt-Triggered Input with Hysteresis Characteristic
Type 5-A
Type 11
V DD
pullup
enable
pullup
enable
P-ch
IN/OUT
P-ch
IN/OUT
output
disable
N-ch
N-ch
P-ch
+
–
input
enable
Type 5-E
data
output
disable
Comparator
N-ch
VREF (Threshold Voltage)
input
enable
pullup
enable
P-ch
V DD
P-ch
data
V DD
data
V DD
Type 13-D
V DD
P-ch
IN/OUT
V DD
data
output disable
N-ch
P-ch
V DD
IN/OUT
output
disable
N-ch
P-ch
RD
Middle-Voltage Input Buffer
V DD
Type 8-A
pullup
enable
Type 16
feedback
cut-off
P-ch
V DD
data
P-ch
P-ch
IN/OUT
output
disable
N-ch
XT1
18
XT2
µPD78P018F
3. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS)
This register is used to disable the use of part of the internal memory by software. By setting this register (IMS),
it is possible to get the same memory map as that of the mask ROM versions with a different internal memory (ROM,
RAM).
IMS is set with an 8-bit memory manipulate instruction.
RESET input sets IMS to CFH.
Figure 3-1. Internal Memory Size Switching Register Format
Symbol
IMS
7
6
5
RAM2 RAM1 RAM0
4
0
3
2
1
0
ROM3 ROM2 ROM1 ROM0
Address
After reset
R/W
FFF0H
CFH
W
ROM3 ROM2 ROM1 ROM0
Selection of Internal ROM
Capacity
0
0
1
0
8 Kbytes
0
1
0
0
16 Kbytes
0
1
1
0
24 Kbytes
1
0
0
0
32 Kbytes
1
0
1
0
40 Kbytes
1
1
0
0
48 Kbytes
1
1
1
0
56 KbytesNote
1
1
1
1
60 Kbytes
Other than above
Setting prohibited
RAM2 RAM1 RAM0
Selection of Internal High-Speed RAM
Capacity
0
1
0
512 bytes
1
1
0
1024 bytes
Other than above
Setting prohibited
Note When the external device expansion function is used, the internal ROM capacity should be set to 56 Kbytes
or less.
Table 3-1 shows the setting values of IMS which make the memory map the same as that of the mask ROM versions.
Table 3-1. Internal Memory Size Switching Register Setting Values
Target Mask ROM Versions
IMS Setting Values
µPD78011F
42H
µPD78012F
44H
µPD78013F
C6H
µPD78014F
C8H
µPD78015F
CAH
µPD78016F
CCH
µPD78018F
CFH
19
µPD78P018F
4. INTERNAL EXPANSION RAM SIZE SWITCHING REGISTER (IXS)
This register is used to disable the use of part of the internal expansion RAM capacity by software. By setting this
register (IXS), it is possible to get the same memory map as that of the mask ROM versions with a different internal
expansion RAM.
IXS is set with an 8-bit memory manipulate instruction.
RESET input sets IXS to 0AH.
Figure 4-1. Internal Expansion RAM Size Switching Register Format
Symbol
7
6
5
4
IXS
0
0
0
0
3
2
1
0
IXRAM3 IXRAM2 IXRAM1 IXRAM0
Address
After reset
R/W
FFF4H
0AH
W
IXRAM3 IXRAM2 IXRAM1 IXRAM0
1
0
Selection of Internal
Expansion RAM Capacity
1
0
1024 bytes (F400H to F7FFH)
1
0
1
1
512 bytes (F600H to F7FFH)
1
1
0
0
0 bytes
Other than above
Setting prohibited
Table 4-1 shows the setting values of IXS which make the memory map the same as that of the mask ROM versions.
Table 4-1. Internal Expansion RAM Size Switching Register Setting Values
Target Mask ROM Versions
IXS Setting Values
µPD78011F
0CHNote
µPD78012F
µPD78013F
µPD78014F
µPD78015F
0BH
µPD78016F
µPD78018F
0AH
Note Even if a program for the µPD78P018F in which "MOV IXS, #0CH" is written is executed in the µPD78011F,
78012F, 78013F, and 78014F, the operations are not affected.
20
µPD78P018F
5. PROM PROGRAMMING
The µPD78P018F has an internal 60-Kbyte PROM as a program memory. For programming, set the PROM
programming mode by setting the VPP and RESET pins. For the handling of unused pins, refer to PIN CONFIGURATION (Top View) (2) PROM programming mode.
Caution
When writing in a program, use locations 0000H-EFFFH (Specify the last address as EFFFH). You
cannot write in using a PROM programmer that cannot specify the addresses to write.
5.1 Operating Modes
When +5 V or +12.5 V is applied to the VPP pin and the low-level signal is applied to the RESET pin, the PROM
programming mode is set. This mode will become the operating mode as shown in Table 5-1 when the CE, OE, and
PGM pins are set.
Further, when the read mode is set, it is possible to read the contents of the PROM.
Table 5-1. Operating Modes of PROM Programming
Pin
RESET
VPP
VDD
CE
OE
PGM
D0 to D7
L
+12.5 V
+6.5 V
H
L
H
Data input
Page write
H
H
L
High-impedance
Byte write
L
H
L
Data input
Program verify
L
L
H
Data output
Program inhibit
×
H
H
High-impedance
Operating Mode
Page data latch
×
L
L
L
L
H
Data output
Output disable
L
H
×
High-impedance
Standby
H
×
×
High-impedance
Read
+5 V
+5 V
× : L or H
21
µPD78P018F
(1) Read mode
Read mode is set if CE = L, OE = L is set.
(2) Output disable mode
Data output becomes high-impedance and is in the output disable mode if OE = H is set.
Therefore, it allows data to be read from any device by controlling the OE pin, if multiple µ PD78P018Fs are
connected to the data bus.
(3) Standby mode
Standby mode is set if CE = H is set.
In this mode, data outputs become high-impedance irrespective of the OE status.
(4) Page data latch mode
Page data latch mode is set if CE = H, PGM = H, OE = L are set at the beginning of page write mode.
In this mode, 1 page 4-byte data is latched in an internal address/data latch circuit.
(5) Page write mode
After 1 page 4 bytes of addresses and data are latched in the page data latch mode, a page write is executed
by applying a 0.1-ms program pulse (active low) to the PGM pin with CE = H, OE = H. Then, program verification
can be performed, if CE = L, OE = L are set.
If programming is not performed by a one-time program pulse, X (X ≤ 10) write and verification operations should
be executed repeatedly.
(6) Byte write mode
Byte write is executed when a 0.1-ms program pulse (active low) is applied to the PGM pin with CE = L, OE =
H. Then, program verification can be performed if OE = L is set.
If programming is not performed by a one-time program pulse, X (X ≤ 10) write and verification operations should
be executed repeatedly.
(7) Program verify mode
Program verify mode is set if CE = L, PGM = H, OE = L are set. In this mode, check if a write operation is performed
correctly, after the write.
(8) Program inhibit mode
Program inhibit mode is used when the OE pin, VPP pin, and D0 to D7 pins of multiple µPD78P018Fs are connected
in parallel and a write is performed to one of those devices.
When a write operation is performed, the page write mode or byte write mode described above is used. At this
time, a write is not performed to a device which has the PGM pin driven high.
22
µPD78P018F
5.2 PROM Write Procedure
Figure 5-1. Page Program Mode Flow Chart
Start
Address = G
VDD = 6.5 V, VPP = 12.5 V
X=0
Latch
Address = Address + 1
Latch
Address = Address + 1
Latch
Address = Address + 1
Address = Address + 1
Latch
No
X=X+1
X = 10 ?
0.1-ms program pulse
Verify 4 bytes
Yes
Fail
Pass
No
Address = N ?
Yes
VDD = 4.5 to 5.5 V, VPP = VDD
Pass
Verify all bytes
Fail
All Pass
Write end
Defective product
G = Start address
N = Program last address
23
µPD78P018F
Figure 5-2. Page Program Mode Timing
Page Data Latch
Page Program
Program Verify
A2 to A16
A0, A1
Hi-Z
D0 to D7
Data Input
VPP
VPP
VDD
VDD + 1.5
VDD
VDD
VIH
CE
VIL
VIH
PGM
VIL
VIH
OE
VIL
24
Data Output
µPD78P018F
Figure 5-3. Byte Program Mode Flow Chart
Start
Address = G
VDD = 6.5 V, VPP = 12.5 V
X=0
X=X+1
No
X = 10 ?
0.1-ms program pulse
Yes
Address = Address + 1
Fail
Verify
Pass
No
Address = N ?
Yes
VDD = 4.5 to 5.5 V, VPP = VDD
Pass
Verify all bytes
Fail
All Pass
Write end
Defective product
G = Start address
N = Program last address
25
µPD78P018F
Figure 5-4. Byte Program Mode Timing
Program
Program Verify
A0 to A16
Hi-Z
D0 to D7
Data Input
Data Output
VPP
VPP
VDD
VDD + 1.5
VDD
VDD
VIH
CE
VIL
VIH
PGM
VIL
VIH
OE
VIL
Cautions 1. VDD should be applied before VPP and cut after V PP.
2. VPP must not exceed +13.5 V including overshoot.
3. Removing and reinserting while +12.5 V is applied to VPP may adversely affect reliability.
26
µPD78P018F
5.3 PROM Read Procedure
The contents of PROM are readable to the external data bus (D0 to D7) according to the read procedure shown
below.
(1) Fix the RESET pin at low level, supply +5 V to the VPP pin, and handle all other unused pins as shown in PIN
CONFIGURATION (Top View) (2) PROM programming mode.
(2) Supply +5 V to the VDD and VPP pins.
(3) Input address of read data into the A0 to A16 pins.
(4) Read mode
(5) Output data to D0 to D7 pins.
The timings of the above steps (2) to (5) are shown in Figure 5-5.
Figure 5-5. PROM Read Timings
Address Input
A0 to A16
CE (Input)
OE (Input)
D0 to D7
Hi-Z
Data Output
Hi-Z
27
µPD78P018F
6. PROGRAM ERASURE (FOR µPD78P018FDW, 78P018FKK-S)
The µPD78P018FDW, 78P018FKK-S are capable of erasing (FFH) the contents of data written in a program
memory and rewriting.
When erasing the contents of data, irradiate light having a wavelength of less than about 400 nm to the erasure
window. Normally, irradiate ultraviolet rays of 254 nm wavelength. Volume of irradiation required to completely erase
the contents of data is as follows:
• UV intensity × erasing time: 30 W•s/cm2 or more
• Erasing time: 40 min. or longer (When a UV lamp of 12mW/cm2 is used. However, a longer time may be needed
because of deterioration in performance of the UV lamp, contamination of the erasure window,
etc.)
When erasing the contents of data, set up the UV lamp within 2.5 cm from the erasing window. Further, if a filter
is provided for a UV lamp, irradiate the ultraviolet rays after removing the filter.
7. OPAQUE FILM ON ERASURE WINDOW (FOR µPD78P018FDW, 78P018FKK-S)
To protect from miserasure by rays other than that of the lamp for erasing EPROM contents, or to protect internal
circuit other than EPROM from malfunction by rays, stick an opaque film on the erasure window when EPROM contents
erasure is not performed.
8. ONE-TIME PROM VERSION SCREENING
The one-time PROM versions (µPD78P018FCW, 78P018FGC-AB8, 78P018FGK-8A8) cannot be tested completely by NEC before it is shipped, because of its structure. It is recommended to perform screening to verify PROM
after writing necessary data and performing high-temperature storage under the conditions below.
Storage Temperature
Storage Time
125°C
24 hours
NEC provides for a fee one-time PROM writing, marking, screening, and verify service for products designated as
“QTOP Microcontrollers.” For details, contact an NEC sales representative.
28
µPD78P018F
9. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Input voltage
Symbol
Ratings
Unit
VDD
Test Conditions
–0.3 to +7.0
V
VPP
–0.3 to +13.5
V
AVDD
–0.3 to VDD + 0.3
V
AVREF
–0.3 to VDD + 0.3
V
AVSS
–0.3 to +0.3
V
–0.3 to VDD + 0.3
V
VI1
P00 to P04, P10 to P17, P20 to P27, P30 to P37,
P40 to P47, P50 to P57, P64 to P67, X1, X2, XT2,
RESET
VI2
P60 to P63
Open-drain
VI3
A9
PROM
programming mode
–0.3 to +16
V
–0.3 to +13.5
V
–0.3 to VDD + 0.3
V
AVSS – 0.3 to AVREF + 0.3
V
Output voltage
VO
Analog input voltage
VAN
P10 to P17
Output current, high
IOH
Per pin
–10
mA
Total for P10 to P17, P20 to P27, P30 to P37
–15
mA
Total for P01 to P03, P40 to P47, P50 to P57, P60 to P67
–15
mA
Per pin
Peak value
30
mA
rms value
15
mA
100
mA
rms value
70
mA
Total for P01 to P03, P56, P57,
Peak value
100
mA
P60 to P67
rms value
70
mA
50
mA
Output current, low
IOLNote
Analog input pin
Total for P40 to P47, P50 to P55 Peak value
Total for P01 to P03, P64 to P67 Peak value
rms value
Operating ambient
temperature
Storage temperature
20
mA
Total for P10 to P17, P20 to P27, Peak value
50
mA
P30 to P37
20
mA
TA
–40 to +85
°C
Tstg
–65 to +150
°C
rms value.
Note The rms value should be calculated as follows: [rms value] = [peak value] × √duty
Caution
Product quality may suffer if the absolute maximum ratings is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
29
µPD78P018F
Capacitance (TA = 25°C, VDD = VSS = 0 V )
MAX.
Unit
Input capacitance
Parameter
Symbol
CIN
f = 1 MHz Unmeasured pins returned to 0 V
Test Conditions
MIN.
TYP.
15
pF
I/O capacitance
CIO
f = 1 MHz
P01 to P03, P10 to P17, P20 to P27,
Unmeasured pins P30 to P37, P40 to P47, P50 to P57,
returned to 0 V
P64 to P67
15
pF
20
pF
P60 to P63
Remark Unless specified othewise, the characteristics of alternate-function pins are the same as those of port pins.
Main System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator
Ceramic
resonator
Recommended
Circuit
X2
X1 VPP
Parameter
Test Conditions
Oscillation
frequency (fX) Note 1
R1
C2
Crystal
resonator
X2
C2
MAX.
Unit
MHz
2.7 V ≤ VDD ≤ 5.5 V
1
10
1.8 V ≤ VDD < 2.7 V
1
5
X1 VPP
Oscillation
stabilization time Note 2
After VDD reaches oscillator
voltage range MIN.
Oscillation
2.7 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 2.7 V
4
ms
1
10
MHz
1
5
frequency (fX) Note 1
C1
stabilization time
X2
TYP.
C1
Oscillation
External
clock
MIN.
X1
µPD74HCU04
VDD = 4.5 to 5.5 V
10
Note 2
ms
30
X1 input
frequency (fX) Note 1
1.0
10.0
MHz
X1 input
high-/low-level width
(tXH , tXL)
45
500
ns
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.
Cautions 1. When using the main system clock oscillator, wire the area enclosed by the broken line in the
above figures as follows to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always keep the ground point of the oscillator capacitor to the same potential as VSS.
• Do not ground the capacitor to a ground pattern in which a high current flows.
• Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the system is operated by the subsystem clock,
the subsystem clock should be switched again to the main system clock after the oscillation
stabilization time is secured by the program.
30
µPD78P018F
Subsystem Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator
Crystal
resonator
Recommended
Circuit
VPP XT2
XT1
Parameter
Test Conditions
Oscillation
frequency (fXT) Note 1
MIN.
TYP.
MAX.
Unit
32
32.768
35
kHz
1.2
2
s
R2
C4
C3
Oscillation
stabilization time
External
clock
XT2
µPD74HCU04
XT1
VDD = 4.5 to 5.5 V
Note 2
10
XT1 input
frequency (fXT) Note 1
32
100
kHz
XT1 input
high-/low-level width
(tXTH , tXTL)
5
15
µs
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after VDD reaches oscillation voltage range MIN.
Cautions 1. When using the subsystem clock oscillator, wire the area enclosed by the broken line in the
above figures as follows to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always keep the ground point of the oscillator capacitor to the same potential as VSS.
• Do not ground the capacitor to a ground pattern in which a high current flows.
• Do not fetch signals from the oscillator.
2. The subsystem clock oscillator is a low-amplitude circuit in order to achive a low consumption
current, and is more prone to malfunction due to noise than the main system clock oscillator.
Particular care is therefore required with the wiring method when the subsystem clock is used.
31
µPD78P018F
RECOMMENDED OSCILLATOR CONSTANTS
Main system clock: Ceramic resonator (TA = –40 to +85°C)
Manufacturer
TDK
Name
Frequency
(MHZ)
Recommended
Oscillator Constants
C1 (pF)
Oscillation
Voltage Range
Remarks
C2 (pF) MIN. (V) MAX. (V)
CCR4.0MC3
4.00
On-Chip On-Chip
1.8
5.5
On-chip capacitor, surface mounting type
FCR4.0MC5
4.00
On-Chip On-Chip
1.8
5.5
On-chip capacitor, insertion type
CCR4.19MC3
4.19
On-Chip On-Chip
1.8
5.5
On-chip capacitor, surface mounting type
FCR4.19MC5
4.19
On-Chip On-Chip
1.8
5.5
On-chip capacitor, insertion type
CCR5.00MC3
5.00
On-Chip On-Chip
1.8
5.5
On-chip capacitor, surface mounting type
FCR5.00MC5
5.00
On-Chip On-Chip
1.8
5.5
On-chip capacitor, insertion type
CCR8.00MC
8.00
On-Chip On-Chip
2.7
5.5
On-chip capacitor, surface mounting type
FCR8.00MC5
8.00
On-Chip On-Chip
2.7
5.5
On-chip capacitor, insertion type
CCR8.38MC
8.38
On-Chip On-Chip
2.7
5.5
On-chip capacitor, surface mounting type
FCR8.38MC5
8.38
On-Chip On-Chip
2.7
5.5
On-chip capacitor, insertion type
CCR10.00MC
10.00
On-Chip On-Chip
2.7
5.5
On-chip capacitor, surface mounting type
FCR10.00MC5
10.00
On-Chip On-Chip
2.7
5.5
On-chip capacitor, insertion type
Murata Mfg. CSA4.00MG
Co., Ltd.
CST4.00MGW
4.00
1.8
5.5
Insertion type
1.8
5.5
On-chip capacitor, insertion type
1.8
5.5
Insertion type
1.8
5.5
On-chip capacitor, insertion type
1.8
5.5
Insertion type
1.8
5.5
On-chip capacitor, insertion type
2.7
5.5
Insertion type
2.7
5.5
On-chip capacitor, insertion type
2.7
5.5
Insertion type
2.7
5.5
On-chip capacitor, insertion type
2.7
5.5
Insertion type
2.7
5.5
On-chip capacitor, insertion type
Caution
4.00
CSA4.19MG
4.19
CST4.19MGW
4.19
CSA5.00MG
5.00
CST5.00MGW
5.00
CSA8.00MTZ
8.00
CST8.00MTW
8.00
CSA8.38MTZ
8.38
CST8.38MTW
8.38
CSA10.00MTZ
10.00
CST10.00MTW
10.00
30
30
On-Chip On-Chip
30
30
On-Chip On-Chip
30
30
On-Chip On-Chip
30
30
On-Chip On-Chip
30
30
On-Chip On-Chip
30
30
On-Chip On-Chip
The oscillator constant and oscillation voltage range indicate conditions of stable oscillation. The
oscillation frequency precision is not guaranteed. For applications requiring oscillation frequency
precision, the oscillation frequency must be adjusted on the implementation circuit. For details,
please contact directly the manufacturer of the resonator you will use.
32
µPD78P018F
Main system clock: Ceramic resonator (TA = –20 to +80°C)
Manufacturer
Name
Kyocera
PBRC4.00A
Corporation
PBRC4.00B
Caution
Frequency
(MHZ)
4.00
4.00
Recommended
Oscillator Constants
C1 (pF)
33
Remarks
C2 (pF) MIN. (V) MAX. (V)
33
On-Chip On-Chip
33
Oscillation
Voltage Range
33
1.8
5.5
Surface mounting type
1.8
5.5
On-chip capacitor, surface mounting type
1.8
5.5
Insertion type
1.8
5.5
On-chip capacitor, insertion type
1.8
5.5
Surface mounting type
1.8
5.5
On-chip capacitor, surface mounting type
1.8
5.5
Insertion type
1.8
5.5
On-chip capacitor, insertion type
KBR-4.00MSA
4.00
KBR-4.00MKS
4.00
PBRC5.00A
5.00
PBRC5.00B
5.00
KBR-5.00MSA
5.00
KBR-5.00MKS
5.00
KBR-8M
8.00
33
33
2.7
5.5
Insertion type
KBR-10M
10.00
33
33
2.7
5.5
Insertion type
On-Chip On-Chip
33
33
On-Chip On-Chip
33
33
On-Chip On-Chip
The oscillator constant and oscillation voltage range indicate conditions of stable oscillation. The
oscillation frequency precision is not guaranteed. For applications requiring oscillation frequency
precision, the oscillation frequency must be adjusted on the implementation circuit. For details,
please contact directly the manufacturer of the resonator you will use.
33
µPD78P018F
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Input voltage,
high
VIH1
VIH2
VIH3
Input voltage,
low
MAX.
Unit
P10 to P17, P21, P23, P30 to P32, VDD = 2.7 to 5.5 V
P35 to P37, P40 to P47,
P50 to P57, P64 to P67
Test Conditions
0.7 VDD
MIN.
TYP.
VDD
V
0.8 VDD
VDD
V
P00 to P03, P20, P22, P24 to P27, VDD = 2.7 to 5.5 V
P33, P34, RESET
0.8 VDD
VDD
V
0.85 VDD
VDD
V
0.7 VDD
15
V
0.8 VDD
15
V
VDD – 0.5
VDD
V
P60 to P63
(N-ch open-drain)
VDD = 2.7 to 5.5 V
VIH4
X1, X2
VDD = 2.7 to 5.5 V
VDD – 0.2
VDD
V
VIH5
XT1/P04, XT2
4.5 V ≤ VDD ≤ 5.5 V
0.8 VDD
VDD
V
2.7 V ≤ VDD < 4.5 V
0.9 VDD
VDD
V
1.8 V ≤ VDD < 2.7
0.9 VDD
VDD
V
P10 to P17, P21, P23, P30 to P32, VDD = 2.7 to 5.5 V
P35 to P37, P40 to P47,
P50 to P57, P64 to P67
0
0.3 VDD
V
0
0.2 VDD
V
P00 to P03, P20, P22, P24 to P27, VDD = 2.7 to 5.5 V
P33, P34, RESET
0
0.2 VDD
V
0
0.15 VDD
V
4.5 V ≤ VDD ≤ 5.5 V
0
0.3 VDD
V
2.7 V ≤ VDD < 4.5 V
0
0.2 VDD
V
0
0.1 VDD
V
VIL1
VIL2
VIL3
VIL4
VIL5
P60 to P63
X1, X2
XT1/P04, XT2
VDD = 2.7 to 5.5 V
0
0.4
V
0
0.2
V
4.5 V ≤ VDD ≤ 5.5 V
0
0.2 VDD
V
2.7 V ≤ VDD < 4.5 V
0
0.1 VDD
V
0
0.1 VDD
V
1.8 V ≤ VDD < 2.7
Output
voltage, high
VOH1
Output
voltage, low
VOL1
VNote
VNote
VDD = 4.5 to 5.5 V, IOH = –1 mA
VDD – 1.0
V
IOH = –100 µA
VDD – 0.5
V
P50 to P57, P60 to P63
VDD = 4.5 to 5.5 V,
IOL = 15 mA
P01 to P03, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P64 to P67
VDD = 4.5 to 5.5 V,
IOL = 1.6 mA
VOL2
SB0, SB1, SCK0
VDD = 4.5 to 5.5 V,
open-drain pulled-up
(R = 1 kΩ)
VOL3
IOL = 400 µA
0.4
2.0
V
0.4
V
0.2 VDD
V
0.5
V
Note When using XT1/P04 as P04, input the inverse of P04 to XT2.
Remark Unless specified othewise, the characteristics of alternate-function pins are the same as those of port pins.
34
µPD78P018F
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Input leakage
current, high
ILIH1
Test Conditions
VIN = VDD
ILIH2
Input leakage
current, low
MIN.
TYP.
Unit
3
µA
X1, X2, XT1/P04, XT2
20
µA
ILIH3
VIN = 15 V
P60 to P63
80
µA
ILIL1
VIN = 0 V
P00 to P03, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
P64 to P67, RESET
–3
µA
X1, X2, XT1/P04, XT2
–20
µA
–3Note
µA
ILIL2
ILIL3
Output leakage
MAX.
P00 to P03, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
P60 to P67, RESET
P60 to P63
ILOH
VOUT = VDD
3
µA
ILOL
VOUT = 0 V
–3
µA
90
kΩ
current, high
Output leakage
current, low
Software
pull-up resistor
R
VIN = 0 V, P01 to P03, P10 to P17, P20 to P27, P30 to P37,
P40 to P47, P50 to P57, P64 to P67
15
40
Note For P60 to P63, a low-level input leak current of –200 µA (MAX.) flows only during the 3 clocks (no-wait time)
after an instruction has been executed to read out port 6 (P6) or port mode register 6 (PM6). Outside the period
of 3 clocks following execution a read-out instruction, the current is –3 µA (MAX.).
Remark Unless specified othewise, the characteristics of alternate-function pins are the same as those of port pins.
35
µPD78P018F
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Supply
currentNote 1
Symbol
IDD1
IDD2
IDD3
IDD4
IDD5
IDD6
Test Conditions
10.00-MHz crystal
oscillation operation mode
10.00-MHz crystal
oscillation HALT mode
TYP.
MAX.
Unit
VDD = 5.0 V ±10 %Note 2
MIN.
12.0
24.0
mA
VDD = 3.0 V ±10
%Note 3
1.4
2.8
mA
VDD = 5.0 V ±10
%Note 2
4.0
8.0
mA
VDD = 3.0 V ±10
%Note 3
1.4
2.8
mA
VDD = 5.0 V ±10 %
150
300
µA
VDD = 3.0 V ±10 %
100
200
µA
VDD = 2.0 V ±10 %
60
120
µA
VDD = 5.0 V ±10 %
25
50
µA
VDD = 3.0 V ±10 %
5
15
µA
VDD = 2.0 V ±10 %
2.5
10
µA
XT1 = VDD
STOP mode, when using feedback
resistor
VDD = 5.0 V ±10 %
2.0
30
µA
VDD = 3.0 V ±10 %
1.0
10
µA
VDD = 2.0 V ±10 %
0.5
10
µA
XT1 = VDD
STOP mode, when not using
feedback resistor
VDD = 5.0 V ±10 %
0.1
30
µA
VDD = 3.0 V ±10 %
0.05
10
µA
VDD = 2.0 V ±10 %
0.05
10
µA
32.768-kHz crystal
oscillation operation modeNote 4
32.768-kHz crystal
oscillation HALT modeNote 4
Notes 1. Refers to the current flowing to the VDD pin. The current flowing to the on-chip pull-up resistors, ports, and
A/D converter is not included.
2. High-speed mode operation (when processor clock control register (PCC) is set to 00H)
3. Low-speed mode operation (when PCC is set to 04H)
4. When main system clock operation is stopped.
36
µPD78P018F
AC Characteristics
(1) Basic Operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Cycle time
(Min. instruction
execution time)
Symbol
TCY
Test Conditions
Operating on
main system clock
tTIH0,
tTIL0
TYP.
MAX.
Unit
3.5 V ≤ VDD ≤ 5.5 V
0.4
64
µs
2.7 V ≤ VDD < 3.5 V
0.8
64
µs
1.8 V ≤ VDD < 2.7 V
2.0
64
µs
125
µs
Operating on subsystem clock
TI0 input
high-/low-level width
MIN.
40Note 1
122
3.5 V ≤ VDD ≤ 5.5 V
2/fsam +
0.1Note 2
µs
2.7 V ≤ VDD < 3.5 V
2/fsam + 0.2Note 2
µs
1.8 V ≤ VDD < 2.7 V
0.5Note 2
µs
2/fsam +
TI1, TI2 input
frequency
fTI1
VDD = 4.5 to 5.5 V
0
4
MHz
0
275
kHz
TI1, TI2 input
high-/low-level width
tTIH1,
tTIL1
VDD = 4.5 to 5.5 V
100
ns
1.8
µs
Interrupt input request
high-/low-level width
tINTH,
tINTL
INTP0
3.5 V ≤ VDD ≤ 5.5 V
2/fsam + 0.1Note 2
µs
2.7 V ≤ VDD < 3.5 V
2/fsam +
0.2Note 2
µs
1.8 V ≤ VDD < 2.7 V
2/fsam + 0.5Note 2
µs
10
µs
20
µs
10
µs
20
µs
INTP1 to INTP3,
KR0 to KR7
RESET low-level width
tRSL
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
Notes 1. Value when using an external clock. When a crystal resonator is used, the value becomes 114 µs (MIN.).
2. In combination with bits 0 (SCS0) and 1 (SCS1) of sampling clock select register (SCS), selection of fsam
is possible between fX/2N+1, fX/64, and fX/128 (when N= 0 to 4).
37
µPD78P018F
TCY vs. VDD (At main system clock operation)
60.0
Operation Guaranteed
Range
Cycle Time TCY [µ s]
10.0
5.0
1.0
0.5
0.1
0
1.0
3.0 3.5 4.0
2.0
1.8
2.7
Supply Voltage VDD [V]
38
5.0 5.5 6.0
µPD78P018F
(2) Read/Write Operation (TA = –40 to +85°C, VDD = 2.7 to 5.5 V)
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
ASTB high-level width
tASTH
0.5 tCY
ns
Address setup time
tADS
0.5 tCY – 30
ns
Address hold time
tADH
50
Data input time from address
tADD1
(2.5 + 2n)tCY – 50
ns
tADD2
(3 + 2n)tCY – 100
ns
tRDD1
(1 + 2n)tCY – 25
ns
(2.5 + 2n)tCY – 100
ns
Data input time from RD↓
tRDD2
ns
Read data hold time
tRDH
0
ns
RD low-level width
tRDL1
(1.5 + 2n)tCY – 20
ns
tRDL2
(2.5 + 2n)tCY – 20
WAIT↓ input time from RD↓
tRDWT1
0.5 tCY
ns
tRDWT2
1.5 tCY
ns
WAIT↓ input time from WR↓
tWRWT
0.5 tCY
ns
WAIT low-level width
tWTL
(0.5 + 2n)tCY + 10
Write data setup time
tWDS
100
ns
Write data hold time
tWDH
20
ns
Load resistance ≥ 5 kΩ
ns
(2 + 2n)tCY
ns
WR low-level width
tWRL
(2.5 + 2n)tCY – 20
ns
RD↓ delay time from ASTB↓
tASTRD
0.5 tCY – 30
ns
WR↓ delay time from ASTB↓
tASTWR
1.5 tCY – 30
ns
ASTB↑ delay time from
tRDAST
tCY – 10
tCY + 40
ns
Address hold time from
RD↑ in external fetch
tRDADH
tCY
tCY + 50
ns
Write data output time from RD↑
tRDWD
0.5 tCY + 5
0.5 tCY + 30
ns
0.5 tCY + 15
0.5 tCY + 90
ns
RD↑ in external fetch
Write data output time from WR↓
Address hold time from WR↑
tWRWD
tWRADH
VDD = 4.5 to 5.5 V
VDD = 4.5 to 5.5 V
VDD = 4.5 to 5.5 V
5
30
ns
15
90
ns
tCY
tCY + 60
ns
tCY
tCY + 100
ns
RD↑ delay time from WAIT↑
tWTRD
0.5 tCY
2.5 tCY + 80
ns
WR↑ delay time from WAIT↑
tWTWR
0.5 tCY
2.5 tCY + 80
ns
Remarks 1. tCY = TCY/4
2. n indicates the number of waits.
39
µPD78P018F
(3) Serial Interface (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
(a) Serial Interface Channel 0
(i)
3-wire serial I/O mode (SCK0... Internal clock output)
Parameter
SCK0 cycle time
Symbol
tKCY1
Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
800
ns
2.7 V ≤ VDD < 4.5 V
1600
ns
2.0 V ≤ VDD < 2.7 V
3200
ns
4800
ns
tKCY1/2 – 50
ns
SCK0 high-/low-level
width
tKH1,
tKL1
VDD = 4.5 to 5.5 V
tKCY1/2 – 100
ns
SI0 setup time
(to SCK0↑)
tSIK1
4.5 V ≤ VDD ≤ 5.5 V
100
ns
2.7 V ≤ VDD < 4.5 V
150
ns
2.0 V ≤ VDD < 2.7 V
300
ns
400
ns
400
ns
SI0 hold time
tKSI1
(from SCK0↑)
SO0 output delay time
from SCK0↓
tKSO1
C = 100 pFNote
300
ns
MAX.
Unit
Note C is the load capacitance of the SCK0 and SO0 output lines.
(ii) 3-wire serial I/O mode (SCK0... External clock input)
Parameter
SCK0 cycle time
SCK0 high-/low-level
width
Symbol
tKCY2
tKH2,
tKL2
Conditions
tSIK2
SI0 hold time
(from SCK0↑)
tKSI2
SO0 output delay time
from SCK0↓
tKSO2
SCK0 rise, fall time
tR2,
tF2
ns
2.7 V ≤ VDD < 4.5 V
1600
ns
2.0 V ≤ VDD < 2.7 V
3200
ns
4800
ns
4.5 V ≤ VDD ≤ 5.5 V
400
ns
2.7 V ≤ VDD < 4.5 V
800
ns
VDD = 2.0 to 5.5 V
C = 100 pFNote
VDD = 2.0 to 5.5 V
1600
ns
2400
ns
100
ns
150
ns
400
ns
300
ns
500
ns
When external device
expansion function is used
160
ns
When external
When 16-bit timer
device expansion
output function is
function is not used used
700
ns
When 16-bit timer
output function is
not used
1000
ns
Note C is the load capacitance of the SO0 output line.
40
TYP.
800
2.0 V ≤ VDD < 2.7 V
SI0 setup time
(to SCK0↑)
MIN.
4.5 V ≤ VDD ≤ 5.5 V
µPD78P018F
(iii) SBI mode (SCK0... Internal clock output)
Parameter
SCK0 cycle time
Symbol
tKCY3
Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
800
ns
2.0 V ≤ VDD < 4.5 V
3200
ns
4800
ns
tKCY3/2 – 50
ns
tKCY3/2 – 150
ns
SCK0 high-/low-level
width
tKH3,
tKL3
VDD = 4.5 to 5.5 V
SB0, SB1 setup time
(to SCK0↑)
tSIK3
4.5 V ≤ VDD ≤ 5.5 V
100
ns
2.0 V ≤ VDD < 4.5 V
300
ns
400
ns
tKCY3/2
ns
SB0, SB1 hold time
(from SCK0↑)
tKSI3
SB0, SB1 output delay
time from SCK0↓
tKSO3
SB0, SB1↓ from SCK0↑
tKSB
tKCY3
ns
SCK0↓ from SB0, SB1↓
R = 1 kΩ,
C = 100 pFNote
VDD = 4.5 to 5.5 V
0
250
ns
0
1000
ns
tSBK
tKCY3
ns
SB0, SB1 high-level width tSBH
tKCY3
ns
SB0, SB1 low-level width
tKCY3
ns
tSBL
Note R and C are the load resistance and load capacitance of the SB0, SB1 and SCK0 output lines.
(iv) SBI mode (SCK0... External clock input)
Parameter
SCK0 cycle time
SCK0 high-/low-level
width
SB0, SB1 setup time
(to SCK0↑)
Symbol
tKCY4
tKH4,
tKL4
tSIK4
Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
800
ns
2.0 V ≤ VDD < 4.5 V
3200
ns
4800
ns
4.5 V ≤ VDD ≤ 5.5 V
400
ns
2.0 V ≤ VDD < 4.5 V
1600
ns
2400
ns
4.5 V ≤ VDD ≤ 5.5 V
100
ns
2.0 V ≤ VDD < 4.5 V
300
ns
400
ns
tKCY4/2
ns
SB0, SB1 hold time
(from SCK0↑)
tKSI4
SB0, SB1 output delay
time from SCK0↓
tKSO4
SB0, SB1↓ from SCK0↑
tKSB
tKCY4
ns
SCK0↓ from SB0, SB1↓
R = 1 kΩ,
C = 100 pFNote
VDD = 4.5 to 5.5 V
0
300
ns
0
1000
ns
tSBK
tKCY4
ns
SB0, SB1 high-level width tSBH
tKCY4
ns
SB0, SB1 low-level width
tSBL
tKCY4
ns
SCK0 rise, fall time
tR4,
tF4
When external device
expansion function is used
160
ns
When external
When 16-bit timer
device expansion
output function is
function is not used used
700
ns
When 16-bit timer
output function is
not used
1000
ns
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output lines.
41
µPD78P018F
(v) 2-wire serial I/O mode (SCK0... Internal clock output)
Parameter
SCK0 cycle time
SCK0 high-level width
Symbol
tKCY5
Conditions
R = 1 kΩ,
C = 100 pFNote
tKH5
MIN.
TYP.
MAX.
Unit
2.7 V ≤ VDD ≤ 5.5 V
1600
ns
2.0 V ≤ VDD < 2.7 V
3200
ns
4800
ns
tKCY5/2 – 160
ns
tKCY5/2 – 190
ns
tKCY5/2 – 50
ns
VDD = 2.7 to 5.5 V
SCK0 low-level width
tKL5
VDD = 4.5 to 5.5 V
tKCY5/2 – 100
ns
SB0, SB1 setup time
(to SCK0↑)
tSIK5
4.5 V ≤ VDD ≤ 5.5 V
300
ns
2.7 V ≤ VDD < 4.5 V
350
ns
2.0 V ≤ VDD < 2.7 V
400
ns
500
ns
SB0, SB1 hold time
(from SCK0↑)
tKSI5
600
ns
SB0, SB1 output delay
tKSO5
0
300
ns
time from SCK0↓
Note R and C are the load resistance and load capacitance of the SCK0, SB0 and SB1 output lines.
(vi) 2-wire serial I/O mode (SCK0... External clock input)
Parameter
SCK0 cycle time
SCK0 high-level width
SCK0 low-level width
Symbol
tKCY6
tKH6
tKL6
SB0, SB1 setup time
(to SCK0↑)
tSIK6
SB0, SB1 hold time
(from SCK0↑)
tKSI6
SB0, SB1 output delay
time from SCK0↓
tKSO6
SCK0 rise, fall time
tR6,
tF6
Conditions
MIN.
TYP.
Unit
1600
ns
2.0 V ≤ VDD < 2.7 V
3200
ns
4800
ns
2.7 V ≤ VDD ≤ 5.5 V
650
ns
2.0 V ≤ VDD < 2.7 V
1300
ns
2100
ns
2.7 V ≤ VDD ≤ 5.5 V
800
ns
2.0 V ≤ VDD < 2.7 V
1600
ns
2400
ns
100
ns
150
ns
tKCY6/2
ns
VDD = 2.0 to 5.5 V
4.5 V ≤ VDD ≤ 5.5 V
0
300
ns
2.0 V ≤ VDD < 4.5 V
0
500
ns
0
800
ns
When external device
expansion function is used
160
ns
When external
When 16-bit timer
device expansion
output function is
function is not used used
700
ns
When 16-bit timer
output function is
not used
1000
ns
R = 1 kΩ,
C = 100 pFNote
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output lines.
42
MAX.
2.7 V ≤ VDD ≤ 5.5 V
µPD78P018F
(b) Serial Interface Channel 1
(i)
3-wire serial I/O mode (SCK1... Internal clock output)
Parameter
SCK1 cycle time
Symbol
tKCY7
Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
800
ns
2.7 V ≤ VDD < 4.5 V
1600
ns
2.0 V ≤ VDD < 2.7 V
3200
ns
4800
ns
tKCY7/2 – 50
ns
tKCY7/2 – 100
ns
SCK1 high-/low-level
width
tKH7,
tKL7
VDD = 4.5 to 5.5 V
SI1 setup time
(to SCK1↑)
tSIK7
4.5 V ≤ VDD ≤ 5.5 V
100
ns
2.7 V ≤ VDD < 4.5 V
150
ns
2.0 V ≤ VDD < 2.7 V
300
ns
400
ns
400
ns
SI1 hold time
(from SCK1↑)
tKSI7
SO1 output delay time
from SCK1↓
tKSO7
C = 100 pFNote
300
ns
MAX.
Unit
Note C is the load capacitance of the SCK1 and SO1 output lines.
(ii) 3-wire serial I/O mode (SCK1... External clock input)
Parameter
SCK1 cycle time
SCK1 high-/low-level
width
Symbol
tKCY8
Conditions
TYP.
800
ns
2.7 V ≤ VDD < 4.5 V
1600
ns
2.0 V ≤ VDD < 2.7 V
3200
ns
4800
ns
tKH8,
4.5 V ≤ VDD ≤ 5.5 V
400
ns
tKL8
2.7 V ≤ VDD < 4.5 V
800
ns
2.0 V ≤ VDD < 2.7 V
SI1 setup time
(to SCK1↑)
tSIK8
SI1 hold time
(from SCK1↑)
tKSI8
SO1 output delay time
from SCK1↓
tKSO8
SCK1 rise, fall time
MIN.
4.5 V ≤ VDD ≤ 5.5 V
tR8,
tF8
VDD = 2.0 to 5.5 V
C = 100 pFNote
VDD = 2.0 to 5.5 V
1600
ns
2400
ns
100
ns
150
ns
400
ns
300
ns
500
ns
When external device
expansion function is used
160
ns
When external
When 16-bit timer
device expansion
output function is
function is not used used
700
ns
When 16-bit timer
output function is
not used
1000
ns
Note C is the load capacitance of the SO1 output line.
43
µPD78P018F
(iii) 3-wire serial I/O mode with automatic transmit/receive function (SCK1... Internal clock output)
Parameter
SCK1 cycle time
Symbol
tKCY9
SCK1 high-/low-level
width
tKH9,
tKL9
SI1 setup time
(to SCK1↑)
tSIK9
SI1 hold time
(from SCK1↑)
tKSI9
SO1 output delay time
from SCK1↓
tKSO9
STB↑ from SCK1↑
tSBD
Strobe signal
high-level width
tSBW
Busy signal setup time
Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
800
ns
2.7 V ≤ VDD < 4.5 V
1600
ns
2.0 V ≤ VDD < 2.7 V
3200
ns
4800
ns
VDD = 4.5 to 5.5 V
tKCY9/2 – 50
ns
tKCY9/2 – 100
ns
4.5 V ≤ VDD ≤ 5.5 V
100
ns
2.7 V ≤ VDD < 4.5 V
150
ns
2.0 V ≤ VDD < 2.7 V
300
ns
400
ns
400
ns
C = 100 pFNote
300
ns
tKCY9/2 – 100
tKCY9/2 + 100
ns
2.7 V ≤ VDD ≤ 5.5 V
tKCY9 – 30
tKCY9 + 30
ns
2.0 V ≤ VDD < 2.7 V
tKCY9 – 60
tKCY9 + 60
ns
tKCY9 – 90
tKCY9 + 90
ns
tBYS
100
ns
4.5 V ≤ VDD ≤ 5.5 V
100
ns
2.7 V ≤ VDD < 4.5 V
150
ns
2.0 V ≤ VDD < 2.7 V
200
ns
(to busy signal
detection timing)
Busy signal hold time
(from busy signal
detection timing)
tBYH
SCK1↓ from busy
inactive
tSPS
300
Note C is the load capacitance of the SCK1 and SO1 output lines.
44
ns
2tKCY9
ns
µPD78P018F
(iv) 3-wire serial I/O mode with automatic transmit/receive function (SCK1... External clock input)
Parameter
SCK1 cycle time
SCK1 high-/low-level
width
Symbol
tKCY10
tKH10,
tKL10
Conditions
tSIK10
SI1 hold time
tKSI10
TYP.
MAX.
Unit
800
ns
2.7 V ≤ VDD < 4.5 V
1600
ns
2.0 V ≤ VDD < 2.7 V
3200
ns
4800
ns
4.5 V ≤ VDD ≤ 5.5 V
400
ns
2.7 V ≤ VDD < 4.5 V
800
ns
2.0 V ≤ VDD < 2.7 V
SI1 setup time
(to SCK1↑)
MIN.
4.5 V ≤ VDD ≤ 5.5 V
VDD = 2.0 to 5.5 V
1600
ns
2400
ns
100
ns
150
ns
400
ns
(from SCK1↑)
SO1 output delay time
tKSO10
C = 100 pFNote
VDD = 2.0 to 5.5 V
300
ns
500
ns
When external device expansion
function is used
160
ns
When external device expansion
function is not used
1000
ns
from SCK1↓
SCK1 rise, fall time
tR10,
tF10
Note C is the load capacitance of the SO1 output line.
45
µPD78P018F
AC Timing Test Point (Excluding X1, XT1 Input)
0.8 VDD
0.8 VDD
Test Points
0.2 VDD
0.2 VDD
Clock Timing
1/fX
tXL
tXH
VIH4 (MIN.)
VIL4 (MAX.)
X1 Input
1/fXT
tXTL
tXTH
VIH5 (MIN.)
VIL5 (MAX.)
XT1 Input
TI Timing
tTIL0
tTIH0
TI0
1/fTI1
tTIL1
TI1,TI2
46
tTIH1
µPD78P018F
Read/Write Operation
External fetch (No wait):
A8 to A15
Higher 8-Bit Address
tADD1
Hi-Z
Lower 8-Bit
Address
AD0 to AD7
tADS
tADH
Operation Code
tRDD1
tRDADH
tASTH
tRDAST
ASTB
RD
tASTRD
tRDL1
tRDH
External fetch (Wait insertion):
A8 to A15
Higher 8-Bit Address
tADD1
Lower 8-Bit
Address
AD0 to AD7
tADS
tADH
Hi-Z
Operation Code
tRDADH
tRDD1
tASTH
tRDAST
ASTB
RD
tASTRD
tRDL1
tRDH
WAIT
tRDWT1
tWTL
tWTRD
47
µPD78P018F
External data access (No wait):
A8 to A15
Higher 8-Bit Address
tADD2
Hi-Z
Lower 8-Bit
Address
AD0 to AD7
tADS
Read Data
Hi-Z
Hi-Z
Write Data
tRDD2
tADH
tASTH
tRDH
ASTB
RD
tASTRD
tRDWD
tRDL2
tWDS
tWDH
tWRADH
tWRWD
WR
tASTWR
tWRL
External data access (Wait insertion):
A8 to A15
Higher 8-Bit Address
tADD2
Lower 8-Bit
Address
AD0 to AD7
Hi-Z
Read Data
Hi-Z
Hi-Z
Write Data
tADS
tADH
tASTH
tRDD2
tRDH
ASTB
tASTRD
RD
tRDL2
tRDWD
tWDH
tWDS
tWRWD
WR
tASTWR
tWRL
tWRADH
WAIT
tRDWT2
tWTL
tWTRD
tWTL
tWRWT
48
tWTWR
µPD78P018F
Serial Transfer Timing
3-wire serial I/O mode:
tKCYm
tKLm
tKHm
tRn
tFn
SCK0,SCK1
tSIKm
SI0,SI1
tKSIm
Input Data
tKSOm
SO0,SO1
Output Data
m = 1, 2, 7, 8
n = 2, 8
SBI mode (Bus release signal transfer):
tKCY3, 4
tKL3, 4
tKH3, 4
tR4
tF4
SCK0
tSBL
tKSB
tSBH
tSIK3, 4
tSBK
tKSI3, 4
SB0, SB1
tKSO3, 4
SBI Mode (Command signal transfer):
tKCY3, 4
tKL3, 4
tR4
tKH3, 4
tF4
SCK0
tKSB
tSIK3, 4
tSBK
tKSI3, 4
SB0, SB1
tKSO3, 4
49
µPD78P018F
2-wire serial I/O mode:
tKCY5,6
tKL5,6
tR6
tKH5,6
tF6
SCK0
tSIK5,6
tKSO5,6
tKSI5,6
SB0, SB1
3-wire serial I/O mode with automatic transmit/receive function:
SO1
SI1
D2
D1
D2
D7
D0
D1
D7
D0
tSIK9,10
tKSI9,10
tKSO9,10
tKH9,10
tF10
SCK1
tKL9,10
tKCY9,10
tR10
tSBD
tSBW
STB
3-wire serial I/O mode with automatic transmit/receive function (Busy processing):
SCK1
7
8
9
Note
10
tBYS
Note
Note
tBYH
BUSY
(Active High)
Note The signal is not actually driven low here; it is shown as such to indicate the timing.
50
1
10 + n
tSPS
µPD78P018F
A/D Converter Characteristics (TA = –40 to +85°C, AVDD = VDD = 2.2 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
8
8
8
bit
2.7 V ≤ AVREF ≤ AVDD
0.6
%
2.2 V ≤ AVREF < 2.7 V
1.4
%
Resolution
Overall
errorNote
Conversion time
tCONV
2.7 V ≤ AVREF ≤ AVDD
19.1
200
µs
2.2 V ≤ AVREF < 2.7 V
38.2
200
µs
µs
Sampling time
tSAMP
24/fX
Analog input voltage
VIAN
AVSS
AVREF
V
Reference voltage
AVREF
2.2
AVDD
V
AV REF resistance
RAIREF
4
14
kΩ
Note Overall error excluding quantization error (±1/2 LSB). It is indicated as a ratio to the full-scale value.
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Parameter
Symbol
Data retention supply
voltage
VDDDR
Data retention supply
current
IDDDR
Release signal set time
tSREL
Oscillation stabilization
wait time
tWAIT
Conditions
MIN.
TYP.
1.8
VDDDR = 1.8 V
Subsystem clock stops and feedback
resistor disconnected
0.1
MAX.
Unit
5.5
V
10
µA
µs
0
Release by RESET
218/f X
ms
Release by interrupt request
Note
ms
Note In combination with bits 0 to 2 (OSTS0 to OSTS2) of oscillation stabilization time select register (OSTS),
selection of 213/fX and 215/fX to 218/fX is possible.
Data Retention Timing (STOP Mode Release by RESET)
Internal Reset Operation
HALT Mode
Operating Mode
STOP Mode
Data Retention Mode
VDD
VDDDR
tSREL
STOP Instruction Execution
RESET
tWAIT
51
µPD78P018F
Data Retention Timing (Standby Release Signal : STOP Mode Release by Interrupt Request Signal)
HALT Mode
Operating Mode
STOP Mode
Data Retention Mode
VDD
VDDDR
tSREL
STOP Instruction Execution
Standby Release Signal
(Interrupt Request)
tWAIT
Interrupt Request Input Timing
tINTL
INTP0 to INTP2
tINTL
INTP3
RESET Input Timing
tRSL
RESET
52
tINTH
µPD78P018F
PROM PROGRAMMING CHARACTERISTICS
DC Characteristics
(1) PROM Write Mode (T A = 25 ±5 °C, VDD = 6.5 ±0.25 V, VPP = 12.5 ±0.3 V)
Symbol
SymbolNote
Input voltage, high
VIH
VIH
Input voltage, low
VIL
VIL
Output voltage, high
VOH
VOH
IOH = –1 mA
Output voltage, low
VOL
VOL
IOL = 1.6 mA
Input leakage current
ILI
ILI
0 ≤ VIN ≤ VDD
VPP supply voltage
VPP
VPP
VDD supply voltage
VDD
VCC
VPP supply current
IPP
IPP
VDD supply current
IDD
ICC
Parameter
Conditions
MIN.
TYP.
MAX.
Unit
0.7 VDD
VDD
V
0
0.3 VDD
V
VDD – 1.0
V
–10
0.4
V
+10
µA
V
12.2
12.5
12.8
6.25
6.5
6.75
V
50
mA
50
mA
PGM = V IL
Note Corresponding µPD27C1001A symbol
(2) PROM Read Mode (TA = 25 ±5°C, VDD = 5.0 ±0.5 V, VPP = VDD ±0.6 V)
Symbol
SymbolNote
MAX.
Unit
Input voltage, high
VIH
VIH
0.7 VDD
VDD
V
Input voltage, low
VIL
VIL
0
0.3 VDD
V
Parameter
Output voltage, high
Conditions
MIN.
TYP.
VOH1
VOH1
IOH = –1 mA
VDD – 1.0
V
VOH2
VOH2
IOH = –100 µA
VDD – 0.5
V
Output voltage, low
VOL
VOL
IOL = 1.6 mA
Input leakage current
ILI
ILI
0 ≤ VIN ≤ VDD
Output leakage current
ILO
ILO
0 ≤ VOUT ≤ VDD, OE = VIH
VPP supply voltage
VPP
VPP
VDD – 0.6
VDD
VDD supply voltage
VDD
VCC
4.5
5.0
5.5
V
VPP supply current
IPP
IPP
VPP = V DD
100
µA
VDD supply current
IDD
ICCA1
CE = V IL, VIN = VIH
50
mA
–10
–10
0.4
V
+10
µA
+10
µA
VDD + 0.6
V
Note Corresponding µPD27C1001A symbol
53
µPD78P018F
AC Characteristics
(1) PROM Write Mode
(a) Page program mode (TA = 25 ±5°C, VDD = 6.5 ±0.25 V, VPP = 12.5 ±0.3 V)
Parameter
Symbol
SymbolNote
Conditions
MIN.
TYP.
MAX.
Unit
Address setup time (to OE↓)
tAS
tAS
2
µs
OE setup time
tOES
tOES
2
µs
CE setup time (to OE↓)
tCES
tCES
2
µs
Input data setup time (to OE↓)
tDS
tDS
2
µs
Address hold time (from OE↑)
tAH
tAH
2
µs
tAHL
tAHL
2
µs
tAHV
tAHV
0
µs
Input data hold time (from OE↑)
tDH
tDH
2
µs
Data output float delay time from OE↑
tDF
tDF
0
VPP setup time (to OE↓)
tVPS
tVPS
1.0
ms
VDD setup time (to OE↓)
tVDS
tVCS
1.0
ms
Program pulse width
tPW
tPW
0.095
Valid data delay time from OE↓
tOE
tOE
OE pulse width during data latching
tLW
tLW
1
µs
PGM setting time
tPGMS
tPGMS
2
µs
CE hold time
tCEH
tCEH
2
µs
OE hold time
tOEH
tOEH
2
µs
250
0.1
ns
0.105
ms
1
µs
Note Corresponding µPD27C1001A symbol
(b) Byte program mode (TA = 25 ±5°C, VDD = 6.5 ±0.25 V, VPP = 12.5 ±0.3 V)
Parameter
Symbol
SymbolNote
Conditions
MIN.
TYP.
MAX.
Unit
tAS
tAS
2
µs
OE setup time
tOES
tOES
2
µs
CE setup time (to PGM↓)
tCES
tCES
2
µs
Input data setup time (to PGM↓)
tDS
tDS
2
µs
Address hold time (from OE↑)
tAH
tAH
2
µs
Input data hold time (from PGM↑)
tDH
tDH
2
Data output float delay time from OE↑
tDF
tDF
0
VPP setup time (to PGM↓)
tVPS
tVPS
1.0
VDD setup time (to PGM↓)
tVDS
tVCS
1.0
Program pulse width
tPW
tPW
0.095
Valid data delay time from OE↓
tOE
tOE
OE hold time
tOEH
—
Address setup time (to PGM↓)
Note Corresponding µPD27C1001A symbol
54
2
µs
250
ns
ms
ms
0.1
0.105
ms
1
µs
µs
µPD78P018F
(2) PROM Read Mode (TA = 25 ±5°C, VDD = 5.0 ±0.5 V, VPP = VDD ±0.6 V)
Symbol
SymbolNote
MAX.
Unit
Data output time from address
tACC
tACC
CE = OE = VIL
800
ns
Data output delay time from CE↓
tCE
tCE
OE = VIL
800
ns
Data output delay time from OE↓
tOE
tOE
CE = VIL
200
ns
Data output float delay time from OE↑
tDF
tDF
CE = VIL
0
60
ns
Data hold time from address
tOH
tOH
CE = OE = VIL
0
Parameter
Conditions
MIN.
TYP.
ns
Note Corresponding µPD27C1001A symbol
(3) PROM Programming Mode Setting (T A = 25°C, VSS = 0 V)
Parameter
Symbol
PROM programming mode setup time
tSMA
Conditions
MIN.
TYP.
MAX.
Unit
µs
10
PROM Write Mode Timing (Page program mode)
Page Data Latch
Page Program
Program Verify
A2 to A16
tAS
tAHL
tDS
tDH
tAHV
A0, A1
D0 to D7
Hi–Z
tDF
Hi–Z
Hi–Z
tPGMS
tVPS
Data Input
tOE
VPP
Data
Output
tAH
VPP
VDD
tVDS
VDD + 1.5
VDD
VDD
tCES
tOEH
VIH
CE
VIL
tCEH
tPW
VIH
PGM
VIL
tLW
tOES
VIH
OE
VIL
55
µPD78P018F
PROM Write Mode Timing (Byte program mode)
Program
Program Verify
A0 to A16
t AS
D0 to D7
t DF
Hi-Z
Hi-Z
Hi-Z
Data Input
t DS
Data Output
t DH
t AH
VPP
VPP
VDD
t VPS
VDD + 1.5
VDD
VDD
t VDS
t OEH
VIH
CE
VIL
t CES
t PW
VIH
PGM
VIL
t OES
t OE
VIH
OE
VIL
Cautions 1. VDD must be applied before VPP and cut off after VPP.
2. VPP must not exceed +13.5 V including overshoot.
3. Removing and reinserting while +12.5 V is applied to VPP may adversely affect reliability.
PROM Read Mode Timing
Effective Address
A0 to A16
VIH
CE
VIL
t CE
VIH
OE
VIL
Note 1
t ACC
D0 to D7
Hi-Z
t DF
Note 1
t OE
Note 2
t OH
Data Output
Hi-Z
Notes 1. When reading within the tACC range, the OE input delay time from the CE fall time must be maximum of
tACC – tOE.
2. tDF is the time from the point at which either OE or CE (whichever is first) reaches VIH.
56
µPD78P018F
PROM Programming Mode Setting Timing
VDD
VDD
0
RESET
VDD
VPP
0
t SMA
A0 to A16
Effective Address
57
µPD78P018F
10. CHARACTERISTIC CURVE (REFERENCE VALUE)
IDD vs. VDD (Main System Clock: 10.0 MHz)
TA = 25 °C
10.0
PCC = 00H
PCC = 01H
PCC = 02H
PCC = 03H
PCC = 04H
PCC = 30H
5.0
HALT (X1 Oscillation, XT1 Halt)
1.0
Supply Current IDD [mA]
0.5
PCC = B0H
0.1
0.05
HALT (X1 Halt, XT1 Oscillation)
0.01
0.005
fX = 10.0 MHz
fXT = 32.768 kHz
0.001
0
1
2
3
4
5
Supply Voltage VDD [V]
58
6
7
8
µPD78P018F
11. PACKAGE DRAWINGS
64 PIN PLASTIC SHRINK DIP (750 mils)
64
33
1
32
A
K
H
G
J
I
L
F
D
N
M
NOTE
B
C
M
R
ITEM
MILLIMETERS
INCHES
1) Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
A
58.68 MAX.
2.311 MAX.
B
1.78 MAX.
0.070 MAX.
2) Item "K" to center of leads when formed parallel.
C
1.778 (T.P.)
0.070 (T.P.)
D
0.50±0.10
0.020+0.004
–0.005
F
0.9 MIN.
0.035 MIN.
G
3.2±0.3
0.126±0.012
H
0.51 MIN.
0.020 MIN.
I
4.31 MAX.
0.170 MAX.
J
5.08 MAX.
0.200 MAX.
K
19.05 (T.P.)
0.750 (T.P.)
L
17.0
0.669
M
0.25+0.10
–0.05
0.010+0.004
–0.003
N
0.17
0.007
R
0~15°
0~15°
P64C-70-750A,C-1
Remark The dimensions and materials of ES versions are the same as those of mass-produced versions.
59
µPD78P018F
64 PIN CERAMIC SHRINK DIP (750 mils)
S
64
33
1
32
A
K
J
I
L
H
C
F
G
D
N
M
NOTES
1) Each lead centerline is located within 0.25 mm (0.010 inch) of
its true position (T.P.) at maximum material condition.
2) Item "K" to center of leads when formed parallel.
M
B
R
ITEM
MILLIMETERS
INCHES
A
58.68 MAX.
2.310 MAX.
B
C
1.78 MAX.
1.778 (T.P.)
0.070 MAX.
0.070 (T.P.)
D
F
0.46±0.05
0.8 MIN.
0.018±0.002
0.031 MIN.
G
3.5±0.3
0.138±0.012
H
I
1.0 MIN.
3.0
0.039 MIN.
0.118
J
5.08 MAX.
0.200 MAX.
K
L
19.05 (T.P.)
18.8
0.750 (T.P.)
0.740
M
0.25±0.05
0.010 +0.002
–0.003
N
0.25
0.010
R
0~15°
0~15°
S
φ 8.89
φ 0.350
P64DW-70-750A-1
60
µPD78P018F
64 PIN PLASTIC QFP (14 × 14)
A
B
33
32
48
49
detail of lead end
S
C D
Q
64
1
R
17
16
F
J
G
H
I
M
P
K
S
N
S
L
M
NOTE
1. Controlling dimension
ITEM
millimeter.
2. Each lead centerline is located within 0.15 mm (0.006 inch) of
its true position (T.P.) at maximum material condition.
MILLIMETERS
INCHES
A
17.6±0.4
B
14.0±0.2
0.693±0.016
0.551 +0.009
–0.008
C
14.0±0.2
0.551 +0.009
–0.008
D
17.6±0.4
0.693±0.016
F
G
1.0
1.0
0.039
0.039
H
0.37 +0.08
–0.07
0.015 +0.003
–0.004
0.006
I
0.15
J
0.8 (T.P.)
0.031 (T.P.)
K
1.8±0.2
0.071±0.008
L
0.8±0.2
0.031 +0.009
–0.008
M
0.17 +0.08
–0.07
0.007 +0.003
–0.004
N
0.10
0.004
P
2.55±0.1
0.100±0.004
Q
0.1±0.1
0.004±0.004
R
S
5°±5°
2.85 MAX.
5°±5°
0.113 MAX.
P64GC-80-AB8-4
Remark The dimensions and materials of ES versions are the same as those of mass-produced versions.
61
µPD78P018F
64 PIN PLASTIC LQFP (12 × 12)
A
B
33
32
detail of lead end
Q
R
D
C
S
48
49
F
64
17
16
1
H
I
M
J
K
M
P
G
N
L
NOTE
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
INCHES
A
14.8±0.4
0.583±0.016
B
12.0±0.2
0.472 +0.009
–0.008
C
12.0±0.2
0.472 +0.009
–0.008
D
14.8±0.4
0.583±0.016
F
1.125
0.044
G
1.125
0.044
H
0.30±0.10
0.012 +0.004
–0.005
0.005
I
0.13
J
0.65 (T.P.)
0.026 (T.P.)
K
1.4±0.2
0.055±0.008
L
0.6±0.2
0.024 +0.008
–0.009
M
0.15 +0.10
–0.05
0.006 +0.004
–0.003
N
0.10
0.004
P
1.4
0.055
Q
R
0.125±0.075
5°±5°
0.005±0.003
5°±5°
S
1.7 MAX.
0.067 MAX.
P64GK-65-8A8-1
Remark
62
The dimensions and materials of ES versions are the same as those of mass-produced versions.
µPD78P018F
64 PIN CERAMIC WQFN
A
B
Q
D
C
U
T
S
64
1
K
W
U1
H
I
M
R
F
G
J
Z
X64KW-80A1
NOTE
Each lead centerline is located within 0.08
mm (0.003 inch) of its true position (T.P.) at
maximum material condition.
ITEM
MILLIMETERS
INCHES
A
14.0 ± 0.18
0.551 ± 0.007
B
13.4
0.528
C
13.4
0.528
D
14.0 ± 0.18
0.551 ± 0.007
F
1.84
0.072
G
3.56 MAX.
0.141 MAX.
H
0.51 ± 0.1
0.02 ± 0.004
I
0.08
0.003
J
0.8 (T.P.)
0.031 (T.P.)
K
1.0 ± 0.15
0.039+0.007
–0.006
Q
C 0.3
C 0.012
R
1.0
0.039
S
1.0
0.039
T
R 3.0
R 0.118
U
10.8
0.425
U1
1.4
0.055
W
0.75 ± 0.15
0.03+0.006
–0.007
Z
0.10
0.004
63
µPD78P018F
12. RECOMMENDED SOLDERING CONDITIONS
The µPD78P018F should be soldered and mounted under the following recommended conditions.
For the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology
Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact your NEC sales representative.
Table 12-1. Surface Mounting Type Soldering Conditions
(1) µPD78P018FGC-AB8: 64-pin Plastic QFP (14 × 14 mm)
Soldering Method
Soldering Conditions
Symbol
Infrared rays reflow
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Count: Three times or less
IR35-00-3
VPS
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
Count: Three times or less
VP15-00-3
Wave soldering
Solder temperature: 260°C, Time: 10 seconds max., Count: Once,
Preheating temperature: 120°C max. (package surface temperature)
WS60-00-1
Partial heating
Pin temperature: 300°C or below, Time: 3 seconds max. (per pin row)
—
(2) µPD78P018FGK-8A8: 64-pin Plastic LQFP (12 × 12 mm)
Soldering Method
Soldering Conditions
Symbol
Infrared rays reflow
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Count: Twice or less, Exposure limit: 7 days Note (after 7 days, prebake 125°C
for 10 hours)
IR35-107-2
VPS
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
Count: Twice or less, Exposure limit: 7 days Note (after 7 days, prebake 125°C
for 10 hours)
VP15-107-2
Wave soldering
Solder temperature: 260°C, Time: 10 seconds max., Count: Once,
Preheating temperature: 120°C max. (package surface temperature),
Exposure limit: 7 days Note (after 7 days, prebake 125°C for 10 hours)
WS60-107-1
Partial heating
Pin temperature: 300°C or below, Time: 3 seconds max. (per pin row)
—
Note Maximum allowable time from taking the soldering packages out of dry pack to soldering.
Storage conditions: 25°C and relative humidity of 65% or less.
Caution Do not use different soldering methods together (except for partial heating).
Table 12-2. Insertion Type Soldering Conditions
µ PD78P018FCW: 64-pin Plastic Shrink DIP (750 mils)
µ PD78P018FDW: 64-pin Ceramic Shrink DIP (with window) (750 mils)
Soldering Method
Soldering Conditions
Wave soldering (pin only)
Solder temperature: 260°C or below, Time: 10 seconds max.
Partial heating
Pin temperature: 300°C or below, Time: 3 seconds max. (per pin row)
Caution
Apply wave soldering only to the pins and be careful not to bring solder into direct contact
with the package.
64
µPD78P018F
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the µPD78P018F.
Also refer to (5) Cautions on using development tools.
(1) Language Processing Software
RA78K/0
78K/0 Series common assembler package
CC78K/0
78K/0 Series common C compiler package
DF78014
Device file for µPD78018F Subseries
CC78K/0-L
78K/0 Series common C compiler library source file
(2) PROM Writing Tools
PG-1500
PROM programmer
PA-78P018CW
PA-78P018GC
PA-78P018GK
PA-78P018KK-S
Programmer adapter connected to PG-1500
PG-1500 controller
PG-1500 control program
(3) Debugging Tool
• When using in-circuit emulator IE-78K0-NS
IE-78K0-NS
In-circuit emulator common to 78K/0 Series
IE-70000-MC-PS-B
Power supply unit for IE-78K0-NS
IE-70000-98-IF-C
Interface adapter when using PC-9800 series as host machine (excluding notebook PCs, C bus
supported )
IE-70000-CD-I-A
PC card and interface cable when using notebook PC of PC-9800 series as host machine (PCMCIA
socket supported)
IE-70000-PC-IF-C
Interface adapter when using IBM PC/ATTM compatible as host machine (ISA bus supported)
IE-70000-PCI-IF
Adapter when using PC that incorporates PCI bus as host machine
IE-78018-NS-EM1
Emulation board for µPD78018F Subseries
NP-64CW
Emulation probe for 64-pin plastic shrink DIP (CW type)
NP-64GC
Emulation probe for 64-pin plastic QFP (GC-AB8 type)
NP-64GK
Emulation probe for 64-pin plastic LQFP (GC-8A8 type)
TGK-064SBW
Conversion adapter for connecting target system board designed to mount a 64-pin plastic LQFP (GK8A8 type) and NP-64GK.
EV-9200GC-64
Socket to be mounted on target system board manufactured for 64-pin plastic QFP (GC-AB8 type)
ID78K0-NSNote
Integrated debugger for IE-78K0-NS
SM78K0
System simulator common to 78K/0 Series
DF78014
Device file for µPD78018F Subseries
65
µPD78P018F
• When using in-circuit emulator IE-78001-R-A
IE-78001-R-A
In-circuit emulator common to 78K/0 Series
IE-70000-98-IF-C
IE-70000-PC-IF-C
IE-78000-R-SV3
Interface adapter when using PC-9800 series as host machine (excluding notebook PCs, C bus
supported)
Interface adapter when using IBM PC/AT compatible as host machine (ISA bus supported)
Interface adapter and cable when using EWS as host machine
IE-70000-PCI-IF
Adapter when using PC that incorporates PCI bus as host machine
IE-78018-NS-EM1
Emulation board for µPD78018F Subseries
IE-78K0-R-EX1
Emulation probe conversion board to use IE-78018-NS-EM1 on IE-78001-R-A
EP-78240CW-R
Emulation probe for 64-pin plastic shrink DIP (CW type)
EP-78240GC-R
Emulation probe for 64-pin plastic QFP (GC-AB8 type)
EP-78012GK-R
Emulation probe for 64-pin plastic LQFP (GK-8A8 type)
TGK-064SBW
Conversion adapter for connecting target system board designed to mount a 64-pin plastic LQFP (GK8A8) and NP-64GK.
EV-9200GC-64
Socket to be mounted on target system board manufactured for 64-pin plastic QFP (GC-AB8 type)
ID78K0
Integrated debugger for IE-78001-R-A
SM78K0
System simulator common to 78K/0 Series
DF78014
Device file for µPD78018F Subseries
(4) Real-time OS
RX78K/0
Real-time OS for 78K/0 Series
MX78K0
OS for 78K/0 Series
66
µPD78P018F
(5) Cautions on using development tools
• The ID-78K0-NS, ID78K0, and SM78K0 are used in combination with the DF78014.
• The CC78K/0 and RX78K/0 are used in combination with the RA78K/0 and the DF78014.
• The NP-64CW, NP64GC, and NP-64GK are products made by Naitou Densei Machidaseisakusho (+81-44822-3813).
Contact an NEC dealer regarding the purchase of these products.
• The TGK-064SBW is a product made by TOKYO ELETECH CORPORATION.
For further information, connect to: Daimaru Kogyo, Ltd.
Tokyo Electronics Dept. (+81-3-3820-7112)
Osaka Electronics Dept. (+81-6-244-6672)
• For third party development tools, see the 78K/0 Series Selection Guide (U11126E).
• The host machines and OSs supporting each software are as follows.
Host Machine
[OS]
PC
EWS
Software
PC-9800 series [WindowsTM]
IBM PC/AT compatible
[Japanese/English Windows]
HP9000 series 700TM [HP-UXTM]
SPARCstationTM [SunOSTM, SolarisTM]
NEWSTM (RISC) [NEWS-OSTM]
RA78K/0
√Note
√
CC78K/0
√Note
√
PG-1500 controller
√Note
—
ID78K0-NS
√
—
ID78K0
√
√
SM78K0
√
—
RX78K/0
√Note
√
MX78K0
√Note
√
Note DOS-based software
67
µPD78P018F
Drawing of Conversion Socket (EV-9200GC-64) and Recommended Footprint
Figure A-1. Drawing of EV-9200GC-64 (for reference only)
A
N
O
L
K
T
J
C
D
S
F
Q
M
R
B
E
EV-9200GC-64
1
P
No.1 pin index
G
H
I
EV-9200GC-64-G0
ITEM
68
MILLIMETERS
INCHES
A
18.8
0.74
B
14.1
0.555
C
14.1
0.555
D
18.8
0.74
E
4-C 3.0
4-C 0.118
F
0.8
0.031
G
6.0
0.236
H
15.8
0.622
I
18.5
0.728
J
6.0
0.236
K
15.8
0.622
L
18.5
0.728
M
8.0
0.315
N
7.8
0.307
O
2.5
0.098
P
2.0
0.079
Q
1.35
0.053
R
0.35 ± 0.1
0.014+0.004
–0.005
S
φ 2.3
φ 0.091
T
φ 1.5
φ 0.059
µPD78P018F
Figure A-2. Recommended Footprint of EV-9200GC-64 (for reference only)
G
J
H
D
E
F
K
I
L
C
B
A
EV-9200GC-64-P1E
ITEM
MILLIMETERS
A
19.5
B
14.8
INCHES
0.768
0.583
C
0.8±0.02 × 15=12.0±0.05
D
+0.003
0.8±0.02 × 15=12.0±0.05 0.031+0.002
–0.001 × 0.591=0.472 –0.002
0.031+0.002
–0.001 ×
0.591=0.472 +0.003
–0.002
E
14.8
0.583
F
19.5
0.768
G
6.00 ± 0.08
0.236 +0.004
–0.003
H
6.00 ± 0.08
0.236 +0.004
–0.003
I
0.5 ± 0.02
0.197 +0.001
–0.002
J
φ 2.36 ± 0.03
φ 0.093 +0.001
–0.002
K
φ 2.2 ± 0.1
φ 0.087 +0.004
–0.005
L
φ 1.57 ± 0.03
φ 0.062 +0.001
–0.002
Caution
Dimensions of mount pad for EV-9200 and that for
target device (QFP) may be different in some parts. For
the recommended mount pad dimensions for QFP,
refer to "SEMICONDUCTOR DEVICE MOUNTING
TECHNOLOGY MANUAL" (C10535E).
69
µPD78P018F
Drawing of Conversion Adapter (TGK-064SBW)
Figure A-3. Drawing of TGK-064SBW (for reference only)
TGK-064SBW (TQPACK064SB + TQSOCKET064SBW)
Package dimension (unit: mm)
A
B
K
L
X
M
C
T
G F E D
H I
J
Protrusion height
U
S
V
Q
W
R
N
O
P
a
Z
e
Y
d
k
j
h
i
c
b
f
g
ITEM
MILLIMETERS
INCHES
ITEM
A
B
18.4
0.65x15=9.75
0.724
0.026x0.591=0.384
a
b
C
D
0.65
0.026
0.305
c
d
φ 0.012
1.85
0.073
3.5
2.0
0.138
0.079
E
0.400
e
3.9
0.154
F
G
12.55
14.95
0.494
0.589
f
1.325
0.052
g
1.325
0.052
H
0.65x15=9.75
0.026x0.591=0.384
h
5.9
0.232
I
11.85
0.467
i
0.8
0.031
J
K
18.4
C 2.0
0.724
C 0.079
j
k
2.4
2.7
0.094
0.106
L
M
12.45
10.25
0.490
0.404
N
O
7.7
10.02
0.394
0.303
P
14.92
0.587
Q
R
11.1
1.45
0.437
0.057
S
1.45
0.057
T
4- φ 1.3
4-φ 0.051
U
1.8
0.071
V
5.0
0.197
W
φ 5.3
φ 0.209
X
Z
70
INCHES
φ 0.3
7.75
10.15
Y
note: Product of TOKYO ELETECH CORPORATION.
MILLIMETERS
4-C 1.0
4-C 0.039
φ 3.55
φ 0.9
φ 0.140
φ 0.035
TGK-064SBW-G1E
µPD78P018F
APPENDIX B. RELATED DOCUMENTS
Device Related Documents
Document No.
Document Name
English
Japanese
µPD78011F, 78012F, 78013F, 78014F, 78015F, 78016F, 78018F Data Sheet
U10280E
U10280J
µPD78P018F Data Sheet
This document
U10955J
µPD78018F, 78018FY Subseries User's Manual
U10659E
U10659J
78K/0 Series User's Manual - Instructions
U12326E
U12326J
78K/0 Series Instruction List
—
U10903J
78K/0 Series Instruction Set
—
U10904J
µPD78018F Subseries Special Function Register Table
—
IEM-5594
78K/0 Series Application Note
Basics (I)
U12704E
U12704J
Floating-Point Arithmetic Programs
IEA-1289
U13482J
Development Tool Documents (User's Manual)
Document No.
Document Name
English
RA78K0 Assembler Package
Operation
U11802E
U11802J
Assembly Language
U11801E
U11801J
Structured Assembly Language
U11789E
U11789J
EEU-1402
U12323J
Operation
U11517E
U11517J
Language
U11518E
U11518J
Programming Know-How
U13034E
U13034J
U11940E
U11940J
RA78K Series Structured Assembler Preprocessor
CC78K0 C Compiler
CC78K/0 C Compiler Application Note
Japanese
PG-1500 PROM Programmer
PG-1500 Controller PC-9800 Series (MS-DOS™) Based
EEU-1291
EEU-704
PG-1500 Controller IBM PC Series (PC DOS™) Based
U10540E
EEU-5008
IE-78K0-NS
To be prepared
To be prepared
IE-78001-R-A
To be prepared
To be prepared
IE-78K0-R-EX1
To be prepared
To be prepared
IE-78018-NS-EM1
To be prepared
U13289J
EP-78240
U10332E
EEU-986
EP-78012GK-R
EEU-1538
EEU-5012
SM78K0 System Simulator Windows Based
Reference
U10181E
U10181J
SM78K Series System Simulator
External Part User Open
Interface Specification
U10092E
U10092J
ID78K/0-NS Integrated Debugger Windows Based
Reference
U12900E
U12900J
ID78K/0 Integrated Debugger EWS Based
Reference
—
U11151J
ID78K/0 Integrated Debugger PC Based
Reference
U11539E
U11539J
ID78K/0 Integrated Debugger Windows Based
Guide
U11649E
U11649J
Caution
The contents of the above related documents are subject to change without notice. The latest
documents should be used for design.
71
µPD78P018F
Embedded Software Documents (User's Manual)
Document No.
Document Name
English
78K/0 Series Real-Time OS
78K/0 Series OS MX78K0
Japanese
Basics
U11537E
U11537J
Installation
U11536E
U11536J
Basics
U12257E
U12257J
Other Documents
Document No.
Document Name
English
Japanese
NEC IC Package Manual (CD-ROM)
C13388E
—
Semiconductor Device Mounting Technology Manual
C10535E
C10535J
Quality Grades on NEC Semiconductor Devices
C11531E
C11531J
NEC Semiconductor Device Reliability/Quality Control System
C10983E
C10983J
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E
C11892J
Guide to Quality Assurance for Semiconductor Devices
Microcomputer Product Series Guide
Caution
—
—
U11416J
The contents of the above related documents are subject to change without notice. The latest
documents should be used for design.
72
MEI-1202
µPD78P018F
[MEMO]
73
µPD78P018F
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material.
All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry.
Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
74
µPD78P018F
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860
United Square, Singapore 1130
Tel: 65-253-8311
Fax: 65-250-3583
NEC Electronics (France) S.A.
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Taiwan Ltd.
NEC Electronics Italiana s.r.1.
NEC Electronics (Germany) GmbH
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829
J98. 8
75
µPD78P018F
FIP, IEBus, and QTOP are trademarks of NEC Corporation.
MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the
United States and/or other countries.
PC/AT and PC DOS are trademarks of International Business Machines Corporation.
HP9000 Series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
The export of these products from Japan is regulated by the Japanese government. The export of some or all
of these products may be prohibited without governmental license. To export or re-export some or all of these
products from a country other than Japan may also be prohibited without a license from that country. Please call
an NEC sales representative.
License not needed:
µPD78P018FDW, 78P018FKK-S
The customer must judge the need for license: µPD78P018FCW, 78P018FGC-AB8, 78P018FGK-8A8
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5