NEC UPD784214A

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
16-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The
µPD78F4216A/78F4218A
and
78F4216AY/78F4218AY
are
products
of
µPD784216A/784218A,
784216AY/784218AY Subseries in the 78K/IV Series.
The µPD78F4216A/78F4218A have flash memory in place of the internal ROM of the µPD784216A/784218A. The
incorporation of flash memory allows a program to be written or erased while mounted on the target board.
The µPD78F4216AY/78F4218AY are based on the µPD78F4216A/78F4218A Subseries with the addition of a
multimaster-supporting I2C bus interface.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
µPD784216A, 784216AY Subseries User’s Manual Hardware: U13570E
µPD784218A, 784218AY Subseries User’s Manual Hardware: U12970E
78K/IV Series User’s Manual Instructions:
U10905E
FEATURES
• Pin compatible with the mask ROM products
• Flash memory: 128 KB (µPD78F4216A/78F4216AY)
256 KB (µPD78F4218A/78F4218AY)
• Internal RAM:
8,192 bytes (µPD78F4216A/78F4216AY)
12,800 bytes (µPD78F4218A/78F4218AY)
• Supply voltage: VDD = 1.9 to 5.5 V
APPLICATIONS
Cellular phones, PHS, cordless telephones, CD-ROM, AV equipment
Unless otherwise specified, references in this document to the µPD78F4218AY refer to the µPD78F4216A,
78F4218A, 78F4216AY, and 78F4218AY.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U14125EJ1V0DS00 (1st edition)
Date Published November 2000 N CP(K)
Printed in Japan
2000
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
ORDERING INFORMATION
Part Number
Package
Internal ROM (Bytes)
Internal RAM (Bytes)
µPD78F4216AGC-8EU
100-pin plastic LQFP
(fine pitch) (14 × 14)
128 K
8,192
µPD78F4216AGF-3BA
100-pin plastic QFP
(14 × 20)
128 K
8,192
µPD78F4218AGC-8EU
100-pin plastic LQFP
(fine pitch) (14 × 14)
256 K
12,800
µPD78F4218AGF-3BA
100-pin plastic QFP
(14 × 20)
256 K
12,800
µPD78F4216AYGC-8EU
100-pin plastic LQFP
(fine pitch) (14 × 14)
128 K
8,192
µPD78F4216AYGF-3BA
100-pin plastic QFP
(14 × 20)
128 K
8,192
µPD78F4218AYGC-8EU
100-pin plastic LQFP
(fine pitch) (14 × 14)
256 K
12,800
µPD78F4218AYGF-3BA
100-pin plastic QFP
(14 × 20)
256 K
12,800
2
Data Sheet U14125EJ1V0DS00
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
78K/IV SERIES LINEUP
: Products in mass-production
: Products under development
Supports I2C bus
µ PD784038Y
µ PD784038
Standard models
µ PD784026
Enhanced
A/D converter,
16-bit timer, and
power management
Enhanced internal memory capacity
Pin-compatible with the µ PD784026
Supports multimaster I2C bus
µ PD784225Y
µ PD784225
80-pin, ROM correction added
Supports multimaster I2C bus
Supports multimaster I2C bus
µ PD784216AY
µPD784218AY
µ PD784216A
100-pin, enhanced I/O and
internal memory capacity
µ PD784218A
Enhanced internal memory
capacity, ROM correction added
µ PD784054
µ PD784046
ASSP models
µ PD784956A
For DC inverter control
µ PD784908
On-chip IEBusTM controller
On-chip 10-bit A/D converter
µ PD784938A
Enhanced functions of the
µ PD784908, enhanced
internal memory capacity,
ROM correction added.
µ PD784967
Enhanced functions of the
µ PD784938A, enhanced
I/O and internal memory
capacity.
Supports multimaster I2C bus
µ PD784928Y
µPD784915
Software servo control
On-chip analog circuit for VCRs
Enhanced timer
µ PD784928
Enhanced functions
of the µ PD784915
µPD784976
On-chip VFD controller/driver
Data Sheet U14125EJ1V0DS00
3
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
OVERVIEW OF FUNCTIONS (1/2)
Part Number
Item
µPD78F4216A,
µPD78F4218A,
µPD78F4216AY
µPD78F4218AY
Number of basic instructions (mnemonics)
113
General-purpose registers
8 bits × 16 registers × 8 banks, or 16 bits × 8 registers × 8 banks (memory
mapping)
Minimum instruction execution time
• 160 ns/320 ns/640 ns/1,280 ns/2,560 ns (@fXX = 12.5 MHz operation with
main system clock)
• 61 µs (@fXT = 32.768 kHz operation with subsystem clock)
Internal
memory
128 KB
256 KB
8,192 bytes
12,800 bytes
Flash memory
RAM
Memory space
I/O ports
Pins with
additional
functionsNote 1
1 MB with program and data spaces combined
Total
86
CMOS input
8
CMOS I/O
72
N-ch open-drain I/O
6
Pins with pull-up resistor
70
LED direct drive output
22
Middle-voltage pin
6
Real-time output port
4 bits × 2 or 8 bits × 1
Timer/event counter
Timer/event counter:
(16-bit)
Timer counter × 1
Pulse output
Capture/compare register × 2 • PPG output
• Square wave output
• One-shot pulse output
Timer/event counter 1: Timer counter × 1
(8-bit)
Compare register × 1
Pulse output
• PWM output
• Square wave output
Timer/event counter 2: Timer counter × 1
(8-bit)
Compare register × 1
Pulse output
• PWM output
• Square wave output
Timer/event counter 5: Timer counter × 1
(8-bit)
Compare register × 1
Pulse output
• PWM output
• Square wave output
Timer/event counter 6: Timer counter × 1
(8-bit)
Compare register × 1
Pulse output
• PWM output
• Square wave output
Timer/event counter 7: Timer counter × 1
(8-bit)
Compare register × 1
Pulse output
• PWM output
• Square wave output
Timer/event counter 8: Timer counter × 1
(8-bit)
Compare register × 1
Pulse output
• PWM output
• Square wave output
Serial interface
• UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator)
2
• CSI (3-wire serial I/O, multimaster supporting I C busNote 2): 1 channel
A/D converter
8-bit resolution × 8 channels
D/A converter
8-bit resolution × 2 channels
Notes 1. Pins with additional functions are included with the I/O pins.
2. µPD78F4216AY, 78F4218AY only
4
Data Sheet U14125EJ1V0DS00
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
OVERVIEW OF FUNCTIONS (2/2)
Part Number
Item
µPD78F4216A,
µPD78F4218A,
µPD78F4216AY
µPD78F4218AY
2
3
4
5
6
7
Selectable from fXX, fXX/2, fXX/2 , fXX/2 , fXX/2 , fXX/2 , fXX/2 , fXX/2 , fXT
Clock output
10
11
12
13
Buzzer output
Selectable from fXX/2 , fXX/2 , fXX/2 , fXX/2
Watch timer
1 channel
Watchdog timer
1 channel
Standby
• HALT/STOP/IDLE modes
• In low power consumption mode (with subsystem clock): HALT/IDLE modes
Interrupt
Hardware sources
29 (internal: 20, external: 9)
Software sources
BRK instruction, BRKCS instruction, operand error
Non-maskable
Internal: 1, external: 1
Maskable
Internal: 19, external: 8
• 4 programmable priority levels
• 3 service modes: Vectored interrupt/macro service/context switching
Supply voltage
VDD = 1.9 to 5.5 V
Package
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic QFP (14 × 20)
Data Sheet U14125EJ1V0DS00
5
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
CONTENTS
1.
DIFFERENCES AMONG MODELS IN µPD784216A/784216AY, 784218A/784218AY
SUBSERIES ............................................................................................................................................. 7
2. PIN CONFIGURATION (TOP VIEW) ................................................................................................... 8
3. BLOCK DIAGRAM ............................................................................................................................... 11
4. PIN
4.1
4.2
4.3
FUNCTIONS .................................................................................................................................. 12
Port Pins ..................................................................................................................................... 12
Non-Port Pins ............................................................................................................................. 14
Pin I/O Circuits and Recommended Connections of Unused Pins ....................................... 16
5. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) ................................................................ 20
6. PROGRAMMING FLASH MEMORY..................................................................................................... 22
6.1 Selecting Communication Mode .............................................................................................. 22
6.2 Flash Memory Programming Function .................................................................................... 23
6.3 Connecting Flashpro ll and Flashpro lll ................................................................................... 24
7. ELECTRICAL SPECIFICATIONS ........................................................................................................ 25
8. PACKAGE DRAWINGS ....................................................................................................................... 47
9. RECOMMENDED SOLDERING CONDITIONS .................................................................................. 49
APPENDIX A. DEVELOPMENT TOOLS ................................................................................................ 50
APPENDIX B. RELATED DOCUMENTS ................................................................................................ 53
6
Data Sheet U14125EJ1V0DS00
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
1. DIFFERENCES AMONG MODELS IN µPD784216A/784216AY, 784218A/784218AY SUBSERIES
The only difference among the µPD784214A, 784215A, 784216A, 784217A, and 784218A lies in the internal
memory capacity.
The µPD784214AY, 784215AY, 784216AY, 784217AY, and 784218AY are models with the addition of an I2C bus
control function.
The µPD78F4216A, 78F4216AY, 78F4218A, and 78F4218AY are provided with a 128 KB/256 KB flash memory
instead of the mask ROM of the above models.
These differences are summarized in Table 1-1.
Table 1-1. Differences Among Models in µPD784216A/784216AY, 784218A/784218AY Subseries
µPD784214A,
µPD784215A,
µPD784216A,
µPD784217A,
µPD784218A,
µPD78F4216A,
µPD78F4218A,
Item
µPD784214AY
µPD784215AY
µPD784216AY
µPD784217AY
µPD784218AY
µPD78F4216AY
µPD78F4218AY
Internal ROM
96 KB
(Mask
ROM)
128 KB (Mask ROM)
192 KB
(Mask
ROM)
256 KB
(Mask
ROM)
128 KB
(Flash
memory)
256 KB
(Flash
memory)
Internal RAM
3,584 bytes
5,120 bytes
12,800 bytes
8,192
bytes
12,800
bytes
Internal memory size
switching register
(IMS)
Not provided
ROM correction
Not provided
Provided
Not
provided
Provided
External access status
function
Not provided
Provided
Not
provided
Provided
Supply voltage
VDD = 1.8 to 5.5 V
Electrical
specifications
Refer to the data sheet for each device.
Part Number
8,192 bytes
ProvidedNote
VDD = 1.9 to 5.5 V
Recommended
soldering conditions
EXA pin
Not provided
Provided
Not
provided
TEST pin
Provided
Not provided
VPP pin
Not provided
Provided
Provided
Note The internal flash memory capacity and internal RAM capacity can be changed using the internal memory
size switching register (IMS).
Caution There are differences in noise immunity and noise radiation between the flash memory and mask
ROM versions. When pre-producing an application set with the flash memory version and then
mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations on the
commercial samples (not engineering samples) of the mask ROM version.
Data Sheet U14125EJ1V0DS00
7
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
2. PIN CONFIGURATION (TOP VIEW)
• 100-pin plastic LQFP (fine pitch) (14 × 14)
P65/WR
P64/RD
P63/A19
P67/ASTB
P66/WAIT
VDD
P30/TO0
P103/TI8/TO8
P102/TI7/TO7
P101/TI6/TO6
P100/TI5/TO5
P32/TO2
P31/TO1
P37/EXANote 5
P36/TI01
P35/TI00
P34/TI2
P33/TI1
P95
P94
P93
P92
P91
P90
VPPNote 1
µPD78F4216AGC-8EU, µPD78F4218AGC-8EU, µPD78F4216AYGC-8EU, µPD78F4218AYGC-8EU
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
P82/A2
P11/ANI1
P12/ANI2
P13/ANI3
P14/ANI4
P15/ANI5
P16/ANI6
P17/ANI7
AVSSNote 3
P130/ANO0
P131/ANO1
AVREF1
X2
X1
VSS
XT2
XT1
RESET
P00/INTP0
P01/INTP1
P02/INTP2/NMI
P03/INTP3
P04/INTP4
P05/INTP5
P06/INTP6
AVDDNote 2
AVREF0
P10/ANI0
P80/A0
P81/A1
P61/A17
P60/A16
VSS
P57/A15
P56/A14
P55/A13
P54/A12
P53/A11
P52/A10
P51/A9
P50/A8
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3
P42/AD2
P41/AD1
P40/AD0
P87/A7
P86/A6
P85/A5
P84/A4
P83/A3
P26/SO0
P27/SCK0/SCL0Note 4
P62/A18
74
2
73
3
72
4
71
5
70
6
69
7
68
8
67
9
66
10
65
11
64
12
63
13
62
14
61
15
60
16
59
17
58
18
57
19
56
20
55
21
54
22
53
23
52
24
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P22/ASCK1/SCK1
P23/PCL
P24/BUZ
P25/SI0/SDA0Note 4
75
P121/RTP1
P122/RTP2
P123/RTP3
P124/RTP4
P125/RTP5
P126/RTP6
P127/RTP7
VDD
P72/ASCK2/SCK2
P20/RxD1/SI1
P21/TxD1/SO1
1
P70/RxD2/SI2
P71/TxD2/SO2
P120/RTP0
Notes 1. Connect the VPP pin to VSS directly or via a pull-down resistor in normal operation mode. Connect the
VPP pin to VSS via a pull-down resistor in a system in which the on-chip flash memory is written while
mounted on the target board. For the pull-down connection, it is recommended to use a resistor with a
resistance ranging from 470 Ω to 10 kΩ.
2. Connect the AVDD pin to VDD.
3. Connect the AVSS pin to VSS.
4. The SCL0 and SDA0 pins are available in the µPD78F4216AY, 78F4218AY only.
5. The EXA pin is available in the µPD78F4218A, 78F4218AY only.
8
Data Sheet U14125EJ1V0DS00
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
• 100-pin plastic QFP (14 × 20)
P55/A13
P54/A12
P53/A11
P52/A10
P51/A9
P50/A8
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3
P42/AD2
P41/AD1
P40/AD0
P87/A7
P86/A6
P85/A5
P57/A15
P56/A14
VSS
µPD78F4216AGF-3BA, µPD78F4218AGF-3BA, µPD78F4216AYGF-3BA, µPD78F4218AYGF-3BA
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
P60/A16
1
80
P84/A4
P61/A17
2
79
P83/A3
P62/A18
P63/A19
3
4
78
77
P82/A2
P81/A1
P64/RD
5
76
P80/A0
P65/WR
6
75
P27/SCK0/SCL0Note 4
P90
P91
P92
P93
P94
P95
P122/RTP2
P123/RTP3
P120/RTP0
P121/RTP1
P26/SO0
P25/SI0/SDA0Note 4
P24/BUZ
P23/PCL
P22/ASCK1/SCK1
P21/TxD1/SO1
P20/RxD1/SI1
P72/ASCK2/SCK2
P71/TxD2/SO2
P70/RxD2/SI2
AVREF1
P131/ANO1
P130/ANO0
AVSSNote 3
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P13/ANI3
P12/ANI2
P11/ANI1
P10/ANI0
AVREF0
AVDDNote 2
XT2
XT1
RESET
P00/INTP0
P01/INTP1
P02/INTP2/NMI
P03/INTP3
P04/INTP4
P05/INTP5
P06/INTP6
VPPNote 1
X2
X1
VSS
P100/TI5/TO5
P101/TI6/TO6
P102/TI7/TO7
P103/TI8/TO8
P30/TO0
P31/TO1
P32/TO2
P33/TI1
P34/TI2
P35/TI00
P36/TI01
P37/EXANote 5
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P124/RTP4
P125/RTP5
P126/RTP6
P127/RTP7
VDD
P66/WAIT
P67/ASTB
VDD
Notes 1. Connect the VPP pin to VSS directly or via a pull-down resistor in normal operation mode. Connect the
VPP pin to VSS via a pull-down resistor in a system in which the on-chip flash memory is written while
mounted on the target board. For the pull-down connection, it is recommended to use a resistor with a
resistance ranging from 470 Ω to 10 kΩ.
2. Connect the AVDD pin to VDD.
3. Connect the AVSS pin to VSS.
4. The SCL0 and SDA0 pins are available in the µPD78F4216AY, 78F4218AY only.
5. The EXA pin is available in the µPD78F4218A, 78F4218AY only.
Data Sheet U14125EJ1V0DS00
9
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
A0 to A19:
Address Bus
P120 to P127:
Port 12
AD0 to AD7:
Address/Data Bus
P130, P131:
Port 13
ANI0 to ANI7:
Analog Input
PCL:
Programmable Clock
ANO0, ANO1:
Analog Output
RD:
Read Strobe
ASCK1, ASCK2:
Asynchronous Serial Clock
RESET:
Reset
ASTB:
Address Strobe
RTP0 to RTP7:
Real-time Output Port
AVDD:
Analog Power Supply
RxD1, RxD2:
Receive Data
AVREF0, AVREF1:
Analog Reference Voltage
SCK0 to SCK2:
Serial Clock
AVSS:
Analog Ground
SCL0Note 1:
Serial Clock
BUZ:
Buzzer Clock
SDA0Note 1:
Serial Data
External Access Status Output
SI0 to SI2:
Serial Input
Serial Output
Note 2
EXA
:
INTP0 to INTP6:
Interrupt from Peripherals
SO0 to SO2:
NMI:
Non-maskable Interrupt
TI00, TI01,
P00 to P06:
Port 0
TI1, TI2, TI5 to TI8:
P10 to P17:
Port 1
TO0 to TO2, TO5 to TO8: Timer Output
P20 to P27:
Port 2
TxD1, TxD2:
Transmit Data
P30 to P37:
Port 3
VDD:
Power Supply
P40 to P47:
Port 4
VPP:
Programming Power Supply
P50 to P57:
Port 5
VSS:
Ground
P60 to P67:
Port 6
WAIT:
Wait
P70 to P72:
Port 7
WR:
Write Strobe
P80 to P87:
Port 8
X1, X2:
Crystal (Main System Clock)
P90 to P95:
Port 9
XT1, XT2:
Crystal (Subsystem Clock)
P100 to P103:
Port 10
Timer Input
Notes 1. The SCL0 and SDA0 pins are available in the µPD78F4216AY, 78F4218AY only.
2. The EXA pin is available in the µPD78F4218A, 78F4218AY only.
10
Data Sheet U14125EJ1V0DS00
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
3. BLOCK DIAGRAM
INTP2/NMI
INTP0, INTP1,
INTP3 to INTP6
UART/IOE1
Baud-rate
generator
Programmable
interrupt
controller
TI00
TI01
TO0
Timer/event
counter
(16 bits)
TI1
TO1
Timer/event
counter 1
(8 bits)
TI2
TO2
Timer/event
counter 2
(8 bits)
TI5/TO5
Timer/event
counter 5
(8 bits)
UART/IOE2
Baud-rate
generator
Clocked
serial
interface
RxD1/SI1
TxD1/SO1
ASCK1/SCK1
RxD2/SI2
TxD2/SO2
ASCK2/SCK2
SI0/SDA0Note 1
SO0
SCK0/SCL0Note 1
AD0 to AD7
A0 to A7
A8 to A15
Bus I/F
A16 to A19
RD
WR
WAIT
ASTB
EXANote 2
TI6/TO6
Timer/event
counter 6
(8 bits)
Timer/event
counter 7
(8 bits)
Port 0
P00 to P06
TI7/TO7
Port 1
P10 to P17
Timer/event
counter 8
(8 bits)
Port 2
P20 to P27
Port 3
P30 to P37
Port 4
P40 to P47
Port 5
P50 to P57
Port 6
P60 to P67
Port 7
P70 to P72
Port 8
P80 to P87
Port 9
P90 to P95
Port 10
P100 to P103
Port 12
P120 to P127
Port 13
P130, P131
TI8/TO8
Watch timer
78K/IV
CPU core
Flash
memory
RAM
Watchdog timer
RTP0 to RTP7
NMI/INTP2
ANO0
ANO1
AVREF1
AVSS
P03/INTP3
ANI0 to ANI7
AVREF0
AVDD
AVSS
PCL
Real-time
output port
D/A
converter
A/D
converter
RESET
X1
Clock output
control
System control
X2
XT1
BUZ
Buzzer output
XT2
VDD
VSS
VPP
2
Notes 1. This function supports the I C bus interface and is available in the µPD78F4216AY, 78F4218AY only.
2. The EXA pin is available in the µPD78F4218A, 78F4218AY only.
Data Sheet U14125EJ1V0DS00
11
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
4. PIN FUNCTIONS
4.1 Port Pins (1/2)
Pin Name
I/O
I/O
P00
Alternate Function
INTP0
P01
INTP1
P02
INTP2/NMI
P03
INTP3
P04
INTP4
P05
INTP5
P06
INTP6
P10 to P17
P20
Input
I/O
Port 1 (P1):
• 8-bit input only port
RxD1/SI1
Port 2 (P2):
• 8-bit I/O port
• Input/output can be specified in 1-bit units.
• Whether specifying input mode or output mode, an on-chip pull-up
resistor can be specified in 1-bit units by means of software.
TxD1/SO1
P22
ASCK1/SCK1
P23
PCL
P24
BUZ
P25
SI0/SDA0Note 1
P26
SO0
P27
SCK0/SCL0Note 1
I/O
Port 0 (P0):
• 7-bit I/O port
• Input/output can be specified in 1-bit units.
• Whether specifying input mode or output mode, an on-chip pull-up
resistor can be specified in 1-bit units by means of software.
ANI0 to ANI7
P21
P30
Function
TO0
P31
TO1
P32
TO2
P33
TI1
P34
TI2
P35
TI00
P36
TI01
P37
EXANote 2
Port 3 (P3):
• 8-bit I/O port
• Input/output can be specified in 1-bit units.
• Whether specifying input mode or output mode, an on-chip pull-up
resistor can be specified in 1-bit units by means of software.
P40 to P47
I/O
AD0 to AD7
Port 4 (P4):
• 8-bit I/O port
• Input/output can be specified in 1-bit units.
• When used as an input port, an on-chip pull-up resistor can be
specified by means of software.
• LEDs can be driven directly.
P50 to P57
I/O
A8 to A15
Port 5 (P5):
• 8-bit I/O port
• Input/output can be specified in 1-bit units.
• When used as an input port, an on-chip pull-up resistor can be
specified by means of software.
• LEDs can be driven directly.
Notes 1.
2.
12
This SDA0 and SCL0 are available in the µPD78F4216AY, 78F4218AY only.
This function is available in the µPD78F4218A, 784218AY only.
Data Sheet U14125EJ1V0DS00
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
4.1 Port Pins (2/2)
Pin Name
P60
I/O
I/O
Alternate Function
A16
P61
A17
P62
A18
P63
A19
P64
RD
P65
WR
P66
WAIT
P67
ASTB
P70
I/O
Port 6 (P6):
• 8-bit I/O port
• Input/output can be specified in 1-bit units.
• When used as an input port, an on-chip pull-up resistor can be
specified by means of software.
RxD2/SI2
P71
TxD2/SO2
P72
ASCK2/SCK2
P80 to P87
I/O
P90 to P95
I/O
P100
I/O
A0 to A7
TI5/TO5
TI6/TO6
P102
TI7/TO7
P103
TI8/TO8
Port 7 (P7):
• 3-bit I/O port
• Input/output can be specified in 1-bit units.
• Whether specifying input mode or output mode, an on-chip pull-up
resistor can be specified in 1-bit units by means of software.
Port 8 (P8):
• 8-bit I/O port
• Input/output can be specified in 1-bit units.
• Whether specifying input mode or output mode, an on-chip pull-up
resistor can be specified in 1-bit units by means of software.
• The interrupt control flag (KRIF) is set to 1 when a falling edge is
detected at a pin of this port.
−
P101
Function
Port 9 (P9):
• N-ch open-drain middle-voltage I/O port
• 6-bit I/O port
• Input/output can be specified in 1-bit units.
• LEDs can be driven directly.
Port 10 (P10):
• 4-bit I/O port
• Input/output can be specified in 1-bit units.
• Whether specifying input mode or output mode, an on-chip pull-up
resistor can be specified in 1-bit units by means of software.
P120 to P127
I/O
RTP0 to RTP7
Port 12 (P12):
• 8-bit I/O port
• Input/output can be specified in 1-bit units.
• Whether specifying input mode or output mode, an on-chip pull-up
resistor can be specified in 1-bit units by means of software.
P130, P131
I/O
ANO0, ANO1
Port 13 (P13):
• 2-bit I/O port
• Input/output can be specified in 1-bit units.
Data Sheet U14125EJ1V0DS00
13
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
4.2 Non-Port Pins (1/2)
Pin Name
TI00
I/O
Alternate Function
Function
P35
External count clock input to 16-bit timer counter
TI01
P36
Capture trigger signal input to capture/compare register 00
TI1
P33
External count clock input to 8-bit timer counter 1
TI2
P34
External count clock input to 8-bit timer counter 2
TI5
P100/TO5
External count clock input to 8-bit timer counter 5
TI6
P101/TO6
External count clock input to 8-bit timer counter 6
TI7
P102/TO7
External count clock input to 8-bit timer counter 7
TI8
P103/TO8
External count clock input to 8-bit timer counter 8
P30
16-bit timer output (shared by 14-bit PWM output)
TO1
P31
8-bit timer output (shared by 8-bit PWM output)
TO2
P32
TO5
P100/TI5
TO6
P101/TI6
TO7
P102/TI7
TO8
P103/TI8
Input
TO0
Output
RxD1
Input
RxD2
TxD1
Output
TxD2
ASCK1
Input
ASCK2
SI0
Input
P20/SI1
Serial data input (UART1)
P70/SI2
Serial data input (UART2)
P21/SO1
Serial data output (UART1)
P71/SO2
Serial data output (UART2)
P22/SCK1
Baud rate clock input (UART1)
P72/SCK2
Baud rate clock input (UART2)
Note
P25/SDA0
Serial data input (3-wire serial I/O 0)
SI1
P20/RxD1
Serial data input (3-wire serial I/O 1)
SI2
P70/RxD2
Serial data input (3-wire serial I/O 2)
P26
Serial data output (3-wire serial I/O 0)
SO0
Output
SO1
P21/TxD1
Serial data output (3-wire serial I/O 1)
SO2
P71/TxD2
Serial data output (3-wire serial I/O 2)
P25/SI0
Serial data input/output (I C bus)
SCK0
P27/SCL0Note
Serial clock input/output (3-wire serial I/O 0)
SCK1
P22/ASCK1
Serial clock input/output (3-wire serial I/O 1)
P72/ASCK2
Serial clock input/output (3-wire serial I/O 2)
P27/SCK0
Serial clock input/output (I C bus)
P02/INTP2
Non-maskable interrupt request input
INTP0
P00
External interrupt request input
INTP1
P01
INTP2
P02/NMI
INTP3
P03
INTP4
P04
Note
SDA0
I/O
SCK2
SCL0
Note
NMI
Input
INTP5
P05
INTP6
P06
2
2
Note This function is available in the µPD78F4216AY, 78F4218AY only.
14
Data Sheet U14125EJ1V0DS00
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
4.2 Non-Port Pins (2/2)
Pin Name
I/O
Alternate Function
Function
PCL
Output
P23
Clock output (for trimming main system clock and subsystem clock)
BUZ
Output
P24
Buzzer output
RTP0 to RTP7
Output
P120 to P127
Real-time output port that outputs data in synchronization with
trigger
I/O
P40 to P47
Lower address/data bus for expanding memory externally
Output
P80 to P87
Lower address bus for expanding memory externally
AD0 to AD7
A0 to A7
A8 to A15
P50 to P57
Middle address bus for expanding memory externally
A16 to A19
P60 to P63
Higher address bus for expanding memory externally
P64
Strobe signal output for reading from external memory
P65
Strobe signal output for writing to external memory
RD
Output
WR
WAIT
Input
P66
Wait insertion at external memory access
ASTB
Output
P67
Strobe output that externally latches address information output to
ports 4 through 6 and 8 to access external memory
EXANote
Output
P37
Status signal output at external memory access
RESET
Input
−
System reset input
X1
Input
−
Connecting crystal resonator for main system clock oscillation
X2
−
−
Connecting crystal resonator for subsystem clock oscillation
XT1
Input
XT2
−
ANI0 to ANI7
Input
P10 to P17
ANO0, ANO1
Output
P130, P131
AVREF0
−
A/D converter analog input
D/A converter analog output
−
A/D converter reference voltage input
AVREF1
D/A converter reference voltage input
AVDD
A/D converter positive power supply. Connect to VDD.
AVSS
GND for A/D converter and D/A converter. Connect to VSS.
VDD
Positive power supply
VSS
GND
VPP
Flash memory programming mode setting.
Applying high-voltage for program write/verify. Connect this pin to
VSS directly or via a pull-down resistor in normal operation mode.
Connect the VPP pin to VSS via a pull-down resistor in a system in
which the on-chip flash memory is written while mounted on the
target board. For the pull-down connection, it is recommended to
use a resistor with a resistance ranging from 470 Ω to 10 kΩ.
Note The EXA pin is available in the µPD78F4218A, 78F4218AY only.
Data Sheet U14125EJ1V0DS00
15
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
4.3 Pin I/O Circuits and Recommended Connections of Unused Pins
The I/O circuit type of each pin and recommended connections of unused pins are shown in Table 4-1.
For each type of input/output circuit, refer to Figure 4-1.
Table 4-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins (1/2)
Pin Name
P00/INTP0
I/O Circuit Type
I/O
8-N
I/O
P01/INTP1
Recommended Connection of Unused Pins
Input: Independently connect to VSS via a resistor
Output: Leave open
P02/INTP2/NMI
P03/INTP3 to P06/INTP6
P10/ANI0 to P17/ANI7
9
P20/RxD1/SI1
10-K
P21/TxD1/SO1
10-L
P22/ASCK1/SCK1
10-K
P23/PCL
10-L
Input
I/O
Connect to VSS or VDD
Input: Independently connect to VSS via a resistor
Output: Leave open
P24/BUZ
P25/SI0/SDA0Note 1
10-K
P26/SO0
10-L
Note 1
P27/SCK0/SCL0
10-K
P30/TO0 to P32/TO2
12-E
P33/TI1, P34/TI2
8-N
P35/TI00, P36/TI01
10-M
P37/EXA
Note 2
P40/AD0 to P47/AD7
12-E
5-A
P50/A8 to P57/A15
P60/A16 to P63/A19
P64/RD
P65/WR
P66/WAIT
P67/ASTB
P70/RxD2/SI2
8-N
P71/TxD2/SO2
10-M
P72/ASCK2/SCK2
8-N
P80/A0 to P87/A7
12-E
P90 to P95
13-D
P100/TI5/TO5
8-N
P101/TI6/TO6
P102/TI7/TO7
P103/TI8/TO8
P120/RTP0 to P127/RTP7
12-E
P130/ANO0, P131/ANO1
12-F
Notes 1. The SDA0 and SCL0 pins are available in the µPD78F4216AY, 78F4218AY only.
2. The EXA pin is available in the µPD78F4218A, 78F4218AY only.
16
Data Sheet U14125EJ1V0DS00
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Table 4-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins (2/2)
Pin Name
I/O Circuit Type
RESET
2-G
XT1
16
AVREF1
Recommended Connection of Unused Pins
−
Input
Connect to VSS
−
XT2
AVREF0
I/O
−
Leave open
Connect to VSS
Connect to VDD
AVDD
AVSS
Connect to VSS
VPP
Connect this pin to VSS directly or via a pull-down resist in normal
operation mode. Connect the VPP pin to VSS via a pull-down
resistor in a system in which the on-chip flash memory is written
while mounted on the target board.
For the pull-down connection, it is recommended to use a resistor
with a resistance ranging from 470 Ω to 10 kΩ.
Remark Because the circuit type numbers are standardized among the 78K Series products, they are not
sequential in some models (i.e., some circuits are not provided).
Data Sheet U14125EJ1V0DS00
17
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Figure 4-1. Types of Pin I/O Circuits (1/2)
Type 2-G
Type 10-K
VDD
Pullup
enable
P-ch
IN
VDD
Data
P-ch
IN/OUT
Open drain
Output disable
N-ch
Schmitt-triggered input with hysteresis characteristics
Type 5-A
Type 10-L
VDD
Pullup
enable
VDD
Pullup
enable
P-ch
P-ch
VDD
Data
VDD
Data
P-ch
P-ch
IN/OUT
Output
disable
IN/OUT
Open drain
Output disable
N-ch
N-ch
VSS
Input
enable
Type 8-N
Type 10-M
VDD
Pullup
enable
VDD
Pullup
enable
P-ch
P-ch
VDD
VDD
Data
Data
P-ch
P-ch
IN/OUT
Output
disable
N-ch
Output disable
N-ch
VSS
VDD
Type 12-E
Type 9
IN
IN/OUT
P-ch
N-ch
Comparator
+
Pullup
enable
P-ch
VDD
Data
–
P-ch
IN/OUT
VREF
Output
disable
(Threshold voltage)
Input
enable
18
Input
enable
N-ch
P-ch
Analog output
voltage
Data Sheet U14125EJ1V0DS00
N-ch
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Figure 4-1. Types of Pin I/O Circuits (2/2)
Type 16
Type 12-F
VDD
Data
Feedback
cut-off
P-ch
P-ch
IN/OUT
Output
disable
Input
enable
N-ch
VSS
Analog output
voltage
P-ch
N-ch
XT1
VSS
XT2
Type 13-D
IN/OUT
Data
Output disable
N-ch
VDD
RD
P-ch
Middle-voltage input buffer
Data Sheet U14125EJ1V0DS00
19
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
5. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS)
IMS is a register that is set by software and is used to specify a part of the internal memory that is not to be used.
By setting this register, the internal memory of the µPD78F4218AY can be mapped identically to that of a mask ROM
version with a different internal memory (ROM and RAM) capacity.
IMS is set with an 8-bit memory manipulation instruction.
RESET input sets IMS to FFH.
(1) µPD78F4216A, 78F4216AY
Figure 5-1. Internal Memory Size Switching Register (IMS) Format
Address: 0FFFCH
IMS
After reset: FFH
W
7
6
5
4
3
2
1
0
1
1
ROM1
ROM0
1
1
RAM1
RAM0
ROM1
ROM0
Internal ROM Capacity Selection
0
0
48 KB
0
1
64 KB
1
0
96 KB
1
1
128 KB
RAM1
RAM0
0
0
3,072 bytes
0
1
4,608 bytes
1
0
6,114 bytes
1
1
7,680 bytes
Peripheral RAM Capacity Selection
Caution IMS is not provided on the mask ROM versions (µPD784214A, 784215A, 784216A, µPD784214AY,
784215AY, and 784216AY).
Table 5-1 shows the IMS setting values to make the memory mapping the same as that of the mask ROM
versions.
Table 5-1. Setting Value of Internal Memory Size Switching Register (IMS)
Target Mask ROM Version
20
IMS Setting Value
µPD784214A, 784214AY
ECH
µPD784215A, 784215AY
FDH
µPD784216A, 784216AY
FFH
Data Sheet U14125EJ1V0DS00
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
(2) µPD78F4218A, 78F4218AY
Figure 5-2. Internal Memory Size Switching Register (IMS) Format
Address: 0FFFCH
IMS
After reset: FFH
W
7
6
5
4
3
2
1
0
1
1
ROM1
ROM0
1
1
RAM1
RAM0
ROM1
ROM0
Internal ROM Capacity Selection
0
0
64 KB
0
1
128 KB
1
0
192 KB
1
1
256 KB
RAM1
RAM0
0
0
3,072 bytes
0
1
6,656 bytes
1
0
7,168 bytes
1
1
12,288 bytes
Peripheral RAM Capacity Selection
Caution IMS is not provided on the mask ROM versions (µPD784217A, 784218A, 784217AY, and
784218AY).
Table 5-2 shows the IMS setting values to make the memory mapping the same as that of the mask ROM
versions.
Table 5-2. Setting Value of Internal Memory Size Switching Register (IMS)
Target Mask ROM Version
IMS Setting Value
µPD784217A, 784217AY
EFH
µPD784218A, 784218AY
FFH
Data Sheet U14125EJ1V0DS00
21
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
6. PROGRAMMING FLASH MEMORY
The flash memory can be written with the µPD78F4218AY mounted on the target board (on-board). To do so,
connect a dedicated flash programmer (Flashpro II (part number: FL-PR2), Flashpro III (part number: FL-PR3, PGFP3) to the host machine and target system.
Writing to flash memory can also be performed using flash memory writing adapter connected to Flashpro II or
Flashpro III.
Remark FL-PR2 and FL-PR3 are products of Naito Densei Machida Mfg. Co., Ltd.
6.1
Selecting Communication Mode
To write the flash memory, use Flashpro II and Flashpro III by serial communication.
Select a serial
communication mode from those listed in Table 6-1 in the format shown in Figure 6-1. Each communication mode is
selected by the number of VPP pulses shown in Table 6-1.
Table 6-1. Communication Modes
Communication
Mode
3-wire serial I/O
Number of
Channels
3
Pins Used
Note 1
SCK0/P27/SCL0
Number of
VPP Pulses
0
SO0/P26
Note 1
SI0/P25/SDA0
Note 2
Handshake
1
SCK1/ASCK1/P22
SO1/TxD1/P21
SI1/RxD1/P20
1
SCK2/ASCK2/P72
SO2/TxD2/P71
SI2/RxD2/P70
2
Note 1
SCK0/P27/SCL0
3
SO0/P26
Note 1
SI0/P25/SDA0
P24/BUZ
UART
2
TxD1/SO1/P21
RxD1/SI1/P20
8
TxD2/SO2/P71
RxD2/SI2/P70
9
Notes 1. The SCL0 and SDA0 pins are available in the µPD78F4216AY, 78F4218AY only.
2. This made is available in the µPD78F4216A, 78F4216AY (other than I, K, E standard)
This made is available in the µPD78F4218A, 78F4218AY (other than I standard)
Caution Be sure to select a communication mode with the number of VPP pulses shown in Table 6-1.
22
Data Sheet U14125EJ1V0DS00
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Figure 6-1. Communication Mode Selecting Format
VPP pulses
10 V
VPP
VDD
1
2
n
VSS
RESET
VDD
VSS
6.2
Flash programming mode
Flash Memory Programming Function
The flash memory is written by transferring or receiving commands and data in a selected communication mode.
The major functions of flash memory programming are listed in Table 6-2.
Table 6-2. Major Functions of Flash Memory Programming
Function
Description
Batch erasure
Erases all contents of memory.
Block erasure
Erases contents of specified memory block with one memory block
consisting of 16 KB.
Batch blank check
Checks erased status of entire memory.
Block blank check
Checks erased status of specified block.
Data write
Writes flash memory based on write start address and number of
data to be written (in bytes).
Batch verify
Compares all contents of memory with input data.
Block verify
Compares contents of specified memory block with input data.
Data Sheet U14125EJ1V0DS00
23
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
6.3
Connecting Flashpro II and Flashpro III
The Flashpro II, Flashpro III and µPD78F4218AY are connected differently depending on the selected
communication mode (3-wire serial I/O or UART).
Figures 6-2 to 6-4 show the connections in the respective
communication modes.
Figure 6-2. Connection of Flashpro II and Flashpro III in 3-Wire Serial I/O Mode
VPP
VDD
RESET
Flashpro ll,
Flashpro lll
SCK0 or SCK1 or SCK2
µ PD78F4218AY
SI0 or SI1 or SI2
SO0 or SO1 or SO2
VSS
Figure 6-3. Connection of Flashpro III in Handshake Mode
VPP
VDD
RESET
SCK0
Flashpro lll
SI0
µ PD78F4218AY
SO0
P24
VSS
Figure 6-4. Connection of Flashpro II and Flashpro III in UART Mode
VPP
VDD
RESET
Flashpro ll,
Flashpro lll
RxD1 or RxD2
µ PD78F4218AY
TxD1 or TxD2
VSS
24
Data Sheet U14125EJ1V0DS00
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
7. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°°C)
Parameter
Supply voltage
Symbol
Conditions
Ratings
Unit
VDD
−0.3 to +6.5
V
AVDD
−0.3 to VDD + 0.3
V
AVSS
−0.3 to VSS + 0.3
V
AVREF0
A/D converter reference voltage input
−0.3 to VDD + 0.3
V
AVREF1
D/A converter reference voltage input
−0.3 to VDD + 0.3
V
VI1
Other than P90 to P95
−0.3 to VDD + 0.3
V
VI2
P90 to P95
−0.3 to +12
V
VI3
VPP pin for programming
−0.3 to +10.5
V
Analog input voltage
VAN
Analog input pin
AVSS − 0.3 to AVREF0 + 0.3
V
Output voltage
VO
−0.3 to VDD + 0.3
V
Output current, low
IOL
Per pin
15
mA
Total of P2, P4 to P8
75
mA
Total of P0, P3, P9, P10, P12, P13
75
mA
Total of all pins
100
mA
Per pin
−10
mA
Total of all pins
−50
mA
Input voltage
Output current, high
IOH
N-ch open drain
Operating ambient
temperature
TA
−40 to +85
°C
Storage temperature
Tstg
−65 to +125
°C
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product is
on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Data Sheet U14125EJ1V0DS00
25
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Operating Conditions
• Operating ambient temperature (TA): −40 to +85°C
• Supply voltage and clock cycle time: See Figure 7-1
• Operating voltage with subsystem clock operation: VDD = 1.9 to 5.5 V
Figure 7-1. Supply Voltage and Clock Cycle Time (CPU Clock Frequency: fCPU)
10,000
8,000
Clock cycle time tCYK [ns]
500
400
Guaranteed
operating range
320
300
200
160
100
80
0
0
1
1.9 2
2.7 3
4
4.5
5
5.5
6
Supply voltage [V]
Capacitance (TA = 25°°C, VDD = VSS = 0 V)
Parameter
Input capacitance
Output capacitance
I/O capacitance
26
Symbol
CI
CO
CIO
Conditions
f = 1 MHz
Unmeasured pins
returned to 0 V.
MAX.
Unit
Other than Port 9
15
pF
Port 9
20
pF
Other than Port 9
15
pF
Port 9
20
pF
Other than Port 9
15
pF
Port 9
20
pF
Data Sheet U14125EJ1V0DS00
MIN.
TYP.
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Main System Clock Oscillator Characteristics (TA = −40 to +85°°C)
Resonator
Ceramic
resonator
or crystal
resonator
Recommended Circuit
X2
X1 VSS
External
clock
Parameter
Oscillation frequency
(fX)
X1 input frequency (fX)
X2
µ PD74HCU04
X1
Conditions
TYP.
MAX.
Unit
MHz
4.5 V ≤ VDD ≤ 5.5 V
2
12.5
2.7 V ≤ VDD < 4.5 V
2
6.25
2.0 V ≤ VDD < 2.7 V
2
3.125
1.9 V ≤ VDD < 2.0 V
2
2
4.5 V ≤ VDD ≤ 5.5 V
2
12.5
2.7 V ≤ VDD < 4.5 V
2
6.25
2.0 V ≤ VDD < 2.7 V
2
3.125
1.9 V ≤ VDD < 2.0 V
2
2
15
250
ns
4.5 V ≤ VDD ≤ 5.5 V
0
5
ns
2.7 V ≤ VDD < 4.5 V
0
10
2.0 V ≤ VDD < 2.7 V
0
20
1.9 V ≤ VDD < 2.0 V
0
30
X1 input high-/lowlevel width (tWXH, tWXL)
X1 input rising/falling
time (tXR, tXF)
MIN.
MHz
Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the
broken lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the system is operated by the subsystem clock,
the subsystem clock should be switched back to the main system clock after the oscillation
stabilization time is secured by the program.
Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation
themselves or apply to the resonator manufacturer for evaluation.
Data Sheet U14125EJ1V0DS00
27
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Subsystem Clock Oscillator Characteristics (TA = −40 to +85°°C)
Resonator
Crystal
resonator
Recommended Circuit
VSS XT2
XT1
Parameter
Oscillation frequency
(fXT)
Oscillation
stabilization timeNote
External
clock
XT2
XT1
µ PD74HCU04
Conditions
MIN.
TYP.
MAX.
Unit
32
32.768
35
kHz
1.2
2
s
4.5 V ≤ VDD ≤ 5.5 V
1.9 V ≤ VDD < 4.5 V
10
XT1 input frequency
(fXT)
32
35
kHz
XT1 input high-/lowlevel width (tXTH, tXTL)
14.3
15.6
µs
Note Time required to stabilize oscillation after applying supply voltage (VDD).
Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the
broken lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the device is operating on the subsystem clock,
wait until the oscillation stabilization time has been secured by the program before switching
back to the main system clock.
Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation
themselves or apply to the resonator manufacturer for evaluation.
28
Data Sheet U14125EJ1V0DS00
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
DC Characteristics (TA = −40 to +85°°C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V) (1/3)
Parameter
Input voltage, low
Symbol
VIL1
VIL2
V
2.2 V ≤ VDD ≤ 5.5 V
0
0.3VDD
1.9 V ≤ VDD < 2.2 V
0
0.2VDD
P00 to P06, P20, P22, P33, 2.2 V ≤ VDD ≤ 5.5 V
P34, P70, P72,
1.9 V ≤ VDD < 2.2 V
P100 to P103, RESET
0
0.2VDD
0
0.15VDD
Note 1
0.3VDD
1.9 V ≤ VDD < 2.2 V
0
0.2VDD
VIL4
P10 to P17, P130, P131
2.2 V ≤ VDD ≤ 5.5 V
0
0.3VDD
1.9 V ≤ VDD < 2.2 V
0
0.2VDD
VIH1
X1, X2, XT1, XT2
2.2 V ≤ VDD ≤ 5.5 V
0
0.2VDD
1.9 V ≤ VDD < 2.2 V
0
0.1VDD
2.2 V ≤ VDD ≤ 5.5 V
0
0.3VDD
1.9 V ≤ VDD < 2.2 V
0
0.2VDD
2.2 V ≤ VDD ≤ 5.5 V
0.7VDD
VDD
1.9 V ≤ VDD < 2.2 V
0.8VDD
VDD
P00 to P06, P20, P22, P33, 2.2 V ≤ VDD ≤ 5.5 V
P34, P70, P72,
1.9 V ≤ VDD < 2.2 V
P100 to P103, RESET
0.8VDD
VDD
0.85VDD
VDD
0.7VDD
12
P25, P27
Note 1
VIH3
P90 to P95
(N-ch open drain)
2.2 V ≤ VDD ≤ 5.5 V
1.9 V ≤ VDD < 2.2 V
0.8VDD
VDD
VIH4
P10 to P17, P130, P131
2.2 V ≤ VDD ≤ 5.5 V
0.7VDD
VDD
1.9 V ≤ VDD < 2.2 V
0.8VDD
VDD
2.2 V ≤ VDD ≤ 5.5 V
0.8VDD
VDD
1.9 V ≤ VDD < 2.2 V
0.85VDD
VDD
2.2 V ≤ VDD ≤ 5.5 V
0.7VDD
VDD
1.9 V ≤ VDD < 2.2 V
0.8VDD
VDD
VIH6
VOL1
X1, X2, XT1, XT2
P25, P27
V
V
V
V
V
V
V
V
V
0.4
V
P40 to P47, P50 to P57
Note 2
IOL = 8 mA
4.5 V ≤ VDD ≤ 5.5 V
1.0
V
VOL2
IOL = 400 µA
VOH1
IOH = −1 mA
VIN = 0 V
ILIL2
VIN = VDD
4.5 V ≤ VDD ≤ 5.5 V
0.8
Note 2
Note 2
IOL = −100 µA
ILIH1
V
4.5 V ≤ VDD ≤ 5.5 V
Note 2
ILIL1
V
For pins other than
P40 to P47, P50 to P57,
Note 1
P90 to P95 IOL = 1.6 mA
P90 to P95 IOL = 15 mA
Input leakage current, high
Unit
0
VIH5
Input leakage current, low
MAX.
2.2 V ≤ VDD ≤ 5.5 V
VIH2
Output voltage, high
TYP.
P90 to P95
(N-ch open drain)
VIL6
Output voltage, low
MIN.
VIL3
VIL5
Input voltage, high
Conditions
2.0
V
0.5
V
4.5 V ≤ VDD ≤ 5.5 V VDD − 1.0
V
VDD − 0.5
V
Note 2
Except X1, X2, XT1,
XT2
−3
µA
X1, X2, XT1, XT2
−20
µA
3
µA
Except X1, X2, XT1,
XT2
20
µA
ILIH3
VIN = 12 V (N-ch open drain) P90 to P95
20
µA
Output leakage current, low
ILOL1
VOUT = 0 V
−3
µA
Output leakage current, high
ILOH1
VOUT = VDD
3
µA
ILIH2
X1, X2, XT1, XT2
Notes 1. P21, P23, P24, P26, P30 to P32, P35 to P37, P40 to P47, P50 to P57, P60 to P67, P71, P80 to P87,
P120 to P127
2. Per pin
Data Sheet U14125EJ1V0DS00
29
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
DC Characteristics (TA = −40 to +85°°C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V) (2/3)
(1) µPD78F4216A, 78F4216AY
Parameter
Supply voltage
Symbol
IDD1
IDD2
IDD3
Conditions
Operation
mode
HALT mode
IDLE mode
TYP.
MAX.
Unit
fXX = 12.5 MHz, VDD = 5.0 V ±10%
MIN.
17
40
mA
fXX = 6 MHz, VDD = 3.0 V ±10%
5
17
mA
fXX = 2 MHz, VDD = 2.0 V ±5%
2
10
mA
fXX = 12.5 MHz, VDD = 5.0 V ±10%
6
20
mA
fXX = 6 MHz, VDD = 3.0 V ±10%
2
10
mA
fXX = 2 MHz, VDD = 2.0 V ±5%
0.4
7
mA
fXX = 12.5 MHz, VDD = 5.0 V ±10%
fXX = 6 MHz, VDD = 3.0 V ±10%
IDD4
IDD5
IDD6
Operation
modeNote
HALT
modeNote
IDLE
modeNote
mA
mA
fXX = 2 MHz, VDD = 2.0 V ±5%
0.3
0.9
mA
130
500
µA
fXX = 32 kHz, VDD = 3.0 V ±10%
90
350
µA
fXX = 32 kHz, 2.0 V ≤ VDD ≤ 2.7 V
80
300
µA
fXX = 32 kHz, 1.9 V ≤ VDD < 2.0 V
70
250
µA
fXX = 32 kHz, VDD = 5.0 V ±10%
60
200
µA
fXX = 32 kHz, VDD = 3.0 V ±10%
20
160
µA
fXX = 32 kHz, 2.0 V ≤ VDD ≤ 2.7 V
15
120
µA
fXX = 32 kHz, 1.9 V ≤ VDD < 2.0 V
10
100
µA
fXX = 32 kHz, VDD = 5.0 V ±10%
50
190
µA
fXX = 32 kHz, VDD = 3.0 V ±10%
15
150
µA
fXX = 32 kHz, 2.0 V ≤ VDD ≤ 2.7 V
12
110
µA
fXX = 32 kHz, 1.9 V ≤ VDD < 2.0 V
VDDDR
HALT, IDLE modes
Data retention current
IDDDR
STOP mode
RL
3
1.3
fXX = 32 kHz, VDD = 5.0 V ±10%
Data retention voltage
Pull-up resistor
1
0.5
7
1.9
90
µA
5.5
V
VDD = 2.0 V ±5%
2
10
µA
VDD = 5.0 V ±10%
10
50
µA
30
100
kΩ
VIN = 0 V
10
Note When main system clock is stopped and subsystem clock is operating.
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port
pins.
30
Data Sheet U14125EJ1V0DS00
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
DC Characteristics (TA = −40 to +85°°C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V) (3/3)
(2) µPD78F4218A, 78F4218AY
Parameter
Supply voltage
Symbol
IDD1
IDD2
IDD3
Conditions
Operation
mode
HALT mode
IDLE mode
MIN.
fXX = 12.5 MHz, VDD = 5.0 V ±10%
IDD5
IDD6
Operation
modeNote
HALT
modeNote
IDLE
modeNote
mA
6
17
mA
2
10
mA
fXX = 12.5 MHz, VDD = 5.0 V ±10%
7
20
mA
fXX = 6 MHz, VDD = 3.0 V ±10%
2
10
mA
fXX = 3 MHz, VDD = 2.0 V ±5%
0.5
7
mA
fXX = 12.5 MHz, VDD = 5.0 V ±10%
1
3
mA
0.5
1.3
mA
fXX = 3 MHz, VDD = 2.0 V ±5%
0.3
0.9
mA
fXX = 32 kHz, VDD = 5.0 V ±10%
140
500
µA
fXX = 32 kHz, VDD = 3.0 V ±10%
100
350
µA
fXX = 32 kHz, 2.0 V ≤ VDD ≤ 2.7 V
90
300
µA
fXX = 32 kHz, 1.9 V ≤ VDD < 2.0 V
80
250
µA
fXX = 32 kHz, VDD = 5.0 V ±10%
60
200
µA
fXX = 32 kHz, VDD = 3.0 V ±10%
20
160
µA
fXX = 32 kHz, 2.0 V ≤ VDD ≤ 2.7 V
15
120
µA
fXX = 32 kHz, 1.9 V ≤ VDD < 2.0 V
10
100
µA
fXX = 32 kHz, VDD = 5.0 V ±10%
50
190
µA
fXX = 32 kHz, VDD = 3.0 V ±10%
15
150
µA
fXX = 32 kHz, 2.0 V ≤ VDD ≤ 2.7 V
12
110
µA
fXX = 32 kHz, 1.9 V ≤ VDD < 2.0 V
VDDDR
HALT, IDLE modes
Data retention current
IDDDR
STOP mode
RL
Unit
40
fXX = 3 MHz, VDD = 2.0 V ±5%
Data retention voltage
Pull-up resistor
MAX.
19
fXX = 6 MHz, VDD = 3.0 V ±10%
fXX = 6 MHz, VDD = 3.0 V ±10%
IDD4
TYP.
7
1.9
90
µA
5.5
V
VDD = 2.0 V ±5%
2
10
µA
VDD = 5.0 V ±10%
10
50
µA
30
100
kΩ
VIN = 0 V
10
Note When main system clock is stopped and subsystem clock is operating.
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port
pins.
Data Sheet U14125EJ1V0DS00
31
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
AC Characteristics (TA = −40 to +85°°C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V)
(1) Read/write operation (1/2)
Parameter
Cycle time
Symbol
tCYK
Conditions
tSAST
Address hold time (from ASTB↓) tHSTLA
ASTB high-level width
Address hold time (from RD↑)
tWSTH
tHRA
Delay time from address to RD↓ tDAR
Address float time (from RD↓)
Data input time from address
Data input time from ASTB↓
tFAR
tDAID
tDSTID
Delay time from ASTB↓ to RD↓
Data hold time (from RD↑)
tDRID
tDSTR
tHRID
Unit
ns
2.7 V ≤ VDD < 4.5 V
160
ns
2.0 V ≤ VDD < 2.7 V
320
ns
500
ns
VDD = 5.0 V ±10%
(0.5 + a)T − 20
ns
VDD = 3.0 V ±10%
(0.5 + a)T − 40
ns
VDD = 2.0 V ±5%
(0.5 + a)T − 80
ns
VDD = 5.0 V ±10%
0.5T − 19
ns
VDD = 3.0 V ±10%
0.5T − 24
ns
VDD = 2.0 V ±5%
0.5T − 34
ns
VDD = 5.0 V ±10%
(0.5 + a)T − 17
ns
VDD = 3.0 V ±10%
(0.5 + a)T − 40
ns
VDD = 2.0 V ±5%
(0.5 + a)T − 110
ns
VDD = 5.0 V ±10%
0.5T − 14
ns
VDD = 3.0 V ±10%
0.5T − 14
ns
VDD = 2.0 V ±5%
0.5T − 14
ns
VDD = 5.0 V ±10%
(1 + a)T − 24
ns
VDD = 3.0 V ±10%
(1 + a)T − 35
ns
VDD = 2.0 V ±5%
(1 + a)T − 80
ns
VDD = 5.0 V ±10%
0
ns
VDD = 3.0 V ±10%
0
ns
VDD = 2.0 V ±5%
0
ns
VDD = 5.0 V ±10%
(2.5 + a + n)T − 37
ns
VDD = 3.0 V ±10%
(2.5 + a + n)T − 52
ns
VDD = 2.0 V ±5%
(2.5 + a + n)T − 120
ns
VDD = 5.0 V ±10%
(2 + n)T − 35
ns
VDD = 3.0 V ±10%
(2 + n)T − 50
ns
(2 + n)T − 80
ns
VDD = 5.0 V ±10%
= 2.0 V ±5%
(1.5 + n)T − 40
ns
VDD = 3.0 V ±10%
(1.5 + n)T − 50
ns
VDD = 2.0 V ±5%
(1.5 + n)T − 90
ns
VDD = 5.0 V ±10%
0.5T − 9
ns
VDD = 3.0 V ±10%
0.5T − 9
ns
VDD = 2.0 V ±5%
0.5T − 20
ns
VDD = 5.0 V ±10%
0
ns
VDD = 3.0 V ±10%
0
ns
VDD = 2.0 V ±5%
0
ns
Remark T: tCYK = 1/fXX (fXX: main system clock frequency)
a: 1 (during address wait), otherwise, 0
n: Number of waits (n ≥ 0)
32
MAX.
80
VDD
Data input time from RD↓
TYP.
4.5 V ≤ VDD ≤ 5.5 V
1.9 V ≤ VDD < 2.0 V
Address setup time (to ASTB↓)
MIN.
Data Sheet U14125EJ1V0DS00
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
AC Characteristics
(1) Read/write operation (2/2)
Parameter
Address active time from RD↑
Delay time from RD↑ to ASTB↑
RD low-level width
Symbol
tDRA
tDRST
tWRL
Delay time from address to WR↓ tDAW
Address hold time (from WR↑)
tHRD
Conditions
MIN.
TYP.
MAX.
Unit
VDD = 5.0 V ±10%
0.5T − 2
ns
VDD = 3.0 V ±10%
0.5T − 12
ns
VDD = 2.0 V ±5%
0.5T − 35
ns
VDD = 5.0 V ±10%
0.5T − 9
ns
VDD = 3.0 V ±10%
0.5T − 9
ns
VDD = 2.0 V ±5%
0.5T − 40
ns
VDD = 5.0 V ±10%
(1.5 + n)T − 25
ns
VDD = 3.0 V ±10%
(1.5 + n)T − 30
ns
VDD = 2.0 V ±5%
(1.5 + n)T − 25
ns
VDD = 5.0 V ±10%
(1 + a)T − 24
ns
VDD = 3.0 V ±10%
(1 + a)T − 34
ns
VDD = 2.0 V ±5%
(1 + a)T − 70
ns
VDD = 5.0 V ±10%
0.5T − 14
ns
VDD = 3.0 V ±10%
0.5T − 14
ns
VDD = 2.0 V ±5%
0.5T − 14
ns
Delay time from ASTB↓ to data tDSTOD
VDD = 5.0 V ±10%
0.5T + 15
ns
output
VDD = 3.0 V ±10%
0.5T + 30
ns
VDD = 2.0 V ±5%
0.5T + 240
ns
Delay time from WR↓ to data tDWOD
VDD = 5.0 V ±10%
0.5T − 30
ns
output
VDD = 3.0 V ±10%
0.5T − 30
ns
VDD = 2.0 V ±5%
0.5T − 30
ns
Delay time from ASTB↓ to WR↓ tDSTW
Data setup time (to WR↑)
Data hold time (from WR↑)
tSODWR
tHWOD
Delay time from WR↑ to ASTB↑ tDWST
WR low-level width
tWWL
VDD = 5.0 V ±10%
0.5T − 9
ns
VDD = 3.0 V ±10%
0.5T − 9
ns
VDD = 2.0 V ±5%
0.5T − 20
ns
VDD = 5.0 V ±10%
(1.5 + n)T − 20
ns
VDD = 3.0 V ±10%
(1.5 + n)T − 25
ns
VDD = 2.0 V ±5%
(1.5 + n)T − 70
ns
= 5.0 V ±10%
0.5T − 14
ns
VDD = 3.0 V ±10%
0.5T − 14
ns
VDD = 2.0 V ±5%
0.5T − 50
ns
VDD = 5.0 V ±10%
0.5T − 9
ns
VDD = 3.0 V ±10%
0.5T − 9
ns
VDD = 2.0 V ±5%
0.5T − 30
ns
VDD = 5.0 V ±10%
(1.5 + n)T − 25
ns
VDD = 3.0 V ±10%
(1.5 + n)T − 30
ns
VDD = 2.0 V ±5%
(1.5 + n)T − 30
ns
VDD
Remark T: tCYK = 1/fXX (fXX: main system clock frequency)
a: 1 (during address wait), otherwise, 0
n: Number of wait states (n ≥ 0)
Data Sheet U14125EJ1V0DS00
33
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
AC Characteristics
(2) External wait timing
Parameter
Input time from address to
Symbol
tDAWT
WAIT↓
Input time from ASTB↓ to
tDSTWT
WAIT↓
Conditions
MIN.
VDD = 5.0 V ±10%
Delay time from ASTB↓ to
tHSTWT
tDSTWTH
WAIT↑
Input time from RD↓ to WAIT↓
tDRWTL
Hold time from RD↓ to WAIT↓
Delay time from RD↓ to WAIT↑
Data input time from WAIT↑
Delay time from WAIT↑ to RD↑
Delay time from WAIT↑ to WR↑
Input time from WR↓ to WAIT↓
Hold time from WR↓ to WAIT
Delay time from WR↓ to WAIT↑
tDRWTH
tDWTID
tDWTR
tDWTW
tDWWTL
tHWWT
tDWWTH
(2 + a)T − 40
ns
(2 + a)T − 60
ns
(2 + a)T − 300
ns
VDD = 5.0 V ±10%
1.5T − 40
ns
VDD = 3.0 V ±10%
1.5T − 60
ns
1.5T − 260
ns
VDD = 5.0 V ±10%
(0.5 + n)T + 5
ns
VDD = 3.0 V ±10%
(0.5 + n)T + 10
ns
VDD = 2.0 V ±5%
(0.5 + n)T + 30
ns
VDD = 5.0 V ±10%
(1.5 + n)T − 40
ns
VDD = 3.0 V ±10%
(1.5 + n)T − 60
ns
VDD = 2.0 V ±5%
(1.5 + n)T − 90
ns
VDD = 5.0 V ±10%
T − 40
ns
VDD = 3.0 V ±10%
T − 60
ns
VDD = 5.0 V ±10%
T − 70
ns
nT + 5
ns
VDD = 3.0 V ±10%
nT + 10
ns
VDD = 2.0 V ±5%
nT + 30
ns
VDD = 5.0 V ±10%
(1 + n)T − 40
ns
VDD = 3.0 V ±10%
(1 + n)T − 60
ns
VDD = 2.0 V ±5%
(1 + n)T − 90
ns
VDD = 5.0 V ±10%
0.5T − 5
ns
VDD = 3.0 V ±10%
0.5T − 10
ns
VDD = 2.0 V ±5%
0.5T − 30
ns
VDD = 5.0 V ±10%
0.5T
ns
VDD = 3.0 V ±10%
0.5T
ns
VDD = 2.0 V ±5%
0.5T + 5
ns
VDD = 5.0 V ±10%
0.5T
ns
VDD = 3.0 V ±10%
0.5T
ns
VDD = 2.0 V ±5%
0.5T + 5
ns
VDD = 5.0 V ±10%
T − 40
ns
VDD = 3.0 V ±10%
T − 60
ns
VDD = 2.0 V ±5%
T − 90
ns
VDD = 5.0 V ±10%
nT + 5
ns
VDD = 3.0 V ±10%
nT + 10
ns
VDD = 2.0 V ±5%
nT + 30
ns
VDD = 5.0 V ±10%
(1 + n)T − 40
ns
VDD = 3.0 V ±10%
(1 + n)T − 60
ns
VDD = 2.0 V ±5%
(1 + n)T − 90
ns
Remark T: tCYK = 1/fXX (fXX: main system clock frequency)
a: 1 (during address wait), otherwise, 0
n: Number of wait states (n ≥ 0)
34
Unit
VDD = 2.0 V ±5%
VDD = 2.0 V ±5%
tHRWT
MAX.
VDD = 3.0 V ±10%
VDD = 2.0 V ±5%
Hold time from ASTB↓ to WAIT
TYP.
Data Sheet U14125EJ1V0DS00
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Serial Operation (TA = −40 to +85°°C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V)
(a) 3-wire serial I/O mode (SCK: Internal clock output)
Parameter
Symbol
Conditions
SCK cycle time
tKCY1
2.7 V ≤ VDD ≤ 5.5 V
SCK high-/low-level width
tKH1,
tKL1
2.7 V ≤ VDD ≤ 5.5 V
tSIK1
2.7 V ≤ VDD ≤ 5.5 V
SI setup time (to SCK↑)
SI hold time (from SCK↑)
tKSI1
SO output delay time
(from SCK↓)
tKSO1
MIN.
TYP.
MAX.
Unit
800
ns
3,200
ns
350
ns
1,500
ns
10
ns
30
ns
40
ns
30
ns
MAX.
Unit
(b) 3-wire serial I/O mode (SCK: External clock input)
Parameter
Symbol
Conditions
SCK cycle time
tKCY2
2.7 V ≤ VDD ≤ 5.5 V
SCK high-/low-level width
tKH2
tKL2
2.7 V ≤ VDD ≤ 5.5 V
tSIK2
2.7 V ≤ VDD ≤ 5.5 V
SI setup time (to SCK↑)
SI hold time (from SCK↑)
tKSI2
SO output delay time
(from SCK↓)
tKSO2
MIN.
TYP.
800
ns
3,200
ns
400
ns
1,600
ns
10
ns
30
ns
40
ns
30
ns
MAX.
Unit
(c) UART mode
Parameter
ASCK cycle time
Symbol
tKCY3
Conditions
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
ASCK high-/low-level width
tKH3
tKL3
MIN.
TYP.
417
ns
833
ns
1,667
ns
4.5 V ≤ VDD ≤ 5.5 V
208
ns
2.7 V ≤ VDD < 4.5 V
416
ns
833
ns
Data Sheet U14125EJ1V0DS00
35
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
(d) I2C bus mode
Parameter
Symbol
Standard Mode
High-Speed Mode
Unit
MIN.
MAX.
MIN.
MAX.
SCL0 clock frequency
fCLK
0
100
0
400
kHz
Bus free time (between stop
and start conditions)
tBUF
4.7
−
1.3
−
µs
tHD : STA
4.0
−
0.6
−
µs
Low-level width of SCL0 clock
tLOW
4.7
−
1.3
−
µs
High-level width of SCL0 clock
tHIGH
4.0
−
0.6
−
µs
Setup time of start/restart
conditions
tSU : STA
4.7
−
0.6
−
µs
Data hold When using CBUStime
compatible master
tHD : DAT
5.0
−
−
−
µs
0Note 2
−
0Note 2
0.9Note 3
µs
Hold timeNote1
2
When using I C bus
Data setup time
tSU : DAT
250
Note 4
−
−
ns
Note 5
20 + 0.1Cb
300
ns
100
Rise time of SDA0 and SCL0
signals
tR
−
1,000
Fall time of SDA0 and SCL0
signals
tF
−
300
20 + 0.1CbNote 5
300
ns
Setup time of stop condition
tSU : STO
4.0
−
0.6
−
µs
Pulse width of spike restricted
by input filter
tSP
−
−
0
50
ns
Load capacitance of each bus
line
Cb
−
400
−
400
pF
Notes 1. For the start condition, the first clock pulse is generated after the hold time.
2. To fill the undefined area of the SCL0 falling edge, it is necessary for the device to provide an internal
SDA0 signal (on VIHmin.) with at least 300 ns of hold time.
3. If the device does not extend the SCL0 signal low-level hold time (tLOW), only the maximum data hold
time tHD : DAT needs to be satisfied.
4. The high-speed mode I2C bus can be used in a standard mode I2C bus system. In this case, the
conditions described below must be satisfied.
• If the device does not extend the SCL0 signal low-level hold time
tSU : DAT ≥ 250 ns
• If the device extends the SCL0 signal low-level hold time
Be sure to transmit the data bit to the SDA0 line before the SCL0 line is released (tRmax. + tSU :
2
= 1,000 + 250 = 1,250 ns by standard mode I C bus specification)
5. Cb: Total capacitance per bus line (unit: pF)
36
Data Sheet U14125EJ1V0DS00
DAT
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Other Operations (TA = −40 to +85°°C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Symbol
NMI high-/low-level width
tWNIL
tWNIH
Interrupt input high-/low-level width
tWITL
tWITH
RESET high-/low-level width
tWRSL
tWRSH
Conditions
INTP0 to INTP6
MIN.
TYP.
MAX.
Unit
10
µs
100
ns
10
µs
Clock Output Operation (TA = −40 to +85°°C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
PCL cycle time
tCYCL
4.5 V ≤ VDD ≤ 5.5 V, nT
80
31,250
ns
PCL high-/low-level width
tCLL
tCLH
4.5 V ≤ VDD ≤ 5.5 V, 0.5T − 10
30
15,615
ns
PCL rise/fall time
tCLR
tCLF
4.5 V ≤ VDD ≤ 5.5 V
5
ns
2.7 V ≤ VDD < 4.5 V
10
ns
1.9 V ≤ VDD < 2.7 V
20
ns
Remark T: tCYK = 1/fXX (fXX: Main system clock frequency)
n: Divided frequency ratio set by software in the CPU
• When using the main system clock: n = 1, 2, 4, 8, 16, 32, 64, 128
• When using the subsystem clock: n = 1
Data Sheet U14125EJ1V0DS00
37
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
A/D Converter Characteristics (TA = −40 to +85°°C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
8
8
8
bits
2.7 V ≤ VDD ≤ 5.5 V
2.2 V ≤ AVREF0 ≤ VDD
±1.2
%FSR
1.9 V ≤ VDD < 2.7 V
1.9 V ≤ AVREF0 ≤ VDD
±1.6
%FSR
144
µs
Resolution
Notes 1, 2
Overall error
Conversion time
tCONV
14
Sampling time
tSAMP
24/fXX
Analog input voltage
VIAN
AVSS
AVREF0
V
Reference voltage
AVREF0
1.9
AVDD
V
Resistance between AVREF0 and AVSS
RAVREF0
When not A/D converting
µs
40
kΩ
Notes 1. Quantization error (±1/2 LSB) is not included.
2. Overall error is indicated as a ratio to the full-scale value.
Remark fXX : Main system clock frequency
D/A Converter Characteristics (TA = −40 to +85°°C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
8
8
8
Bits
R = 10 MΩ, 2.0 V ≤ AVREF1 ≤ VDD,
2.0 V ≤ VDD ≤ 5.5 V
±0.6
%FSR
R = 10 MΩ, 1.9 V ≤ AVREF1 ≤ VDD,
1.9 V ≤ VDD ≤ 2.0 V
±1.2
%FSR
4.5 V ≤ AVREF1 ≤ 5.5 V
10
µs
2.7 V ≤ AVREF1 < 4.5 V
15
µs
1.9 V ≤ AVREF1 < 2.7 V
20
µs
Resolution
Notes 1, 2
Overall error
Settling time
Load conditions:
C = 30 pF
Output resistance
RO
Reference voltage
AVREF1
AVREF1 current
AIREF1
DACS0, 1 = 55H
1.9
For only 1 channel
Notes 1. Quantization error (±1/2 LSB) is not included.
2. Overall error is indicated as a ratio to the full-scale value.
38
8
Data Sheet U14125EJ1V0DS00
kΩ
VDD
V
2.5
mA
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Data Retention Characteristics (TA = −40 to +85°°C, VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
1.9
MAX.
Unit
5.5
V
Data retention voltage
VDDDR
STOP mode
Data retention current
IDDDR
VDDDR = 5.0 V ±10%
10
50
µA
VDDDR = 2.0 V ±5%
2
10
µA
VDD rise time
tRVD
200
µs
VDD fall time
tFVD
200
µs
VDD hold time
(from STOP mode setting)
tHVD
0
ms
STOP release signal input time
tDREL
0
ms
Oscillation stabilization wait time
tWAIT
Crystal resonator
30
ms
Ceramic resonator
5
ms
RESET, P00/INTP0 to P06/INTP6
0
0.1VDDDR
V
0.9VDDDR
VDDDR
V
Low-level input voltage
VIL
High-level input voltage
VIH
AC Timing Test Points
VDD − 1 V
0.8VDD or 1.9 V
0.8VDD or 1.9 V
Test points
0.45 V
0.8 V
0.8 V
Data Sheet U14125EJ1V0DS00
39
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Timing Waveforms
(1) Read operations
(CLK)
tCYK
A0 to A7
(Output)
Lower address
Lower address
A8 to A19
(Output)
Higher address
Higher address
tDAID
tHRA
tDRA
tDSTID
AD0 to AD7
(I/O)
Hi-Z
Hi-Z
Lower address
(Output)
tSAST
Data (Input)
Hi-Z
tHRID
tHSTLA
tFAR
ASTB
(Output)
tWSTH
tDSTR
tDRST
tDAR
tDRID
RD
(Output)
tWRL
tDRWTH
tDRWTL
tHRWT
tDAWT
tDWTR
tDWTID
WAIT
(Input)
tDSTWT
tDSTWTH
tHSTWT
Remark The signal is output from pins A0 to A7 when P80 to P87 are unused.
40
Data Sheet U14125EJ1V0DS00
Lower address
(Output)
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
(2) Write operation
(CLK)
tCYK
A0 to A7
(Output)
Lower address
Lower address
A8 to A19
(Output)
Higher address
Higher address
tDAID
tHWA
tDAW
tDSTOD
AD0 to AD7
(Output)
Hi-Z
Lower address
(Output)
tSAST
Hi-Z
Lower address
(Output)
tHWOD
tHSTLA
tSODWR
tFAR
ASTB
(Output)
Hi-Z
Data (Output)
tWSTH
tDSTW
tDWST
tDAW
tDWOD
WR
(Output)
tWWL
tDWWTL
tDAWT
tDWWTH
tHWWT
tDWTW
tDWTID
WAIT
(Input)
tDSTWT
tDSTWTH
tHSTWT
Remark The signal is output from pins A0 to A7 when P80 to P87 are unused.
Data Sheet U14125EJ1V0DS00
41
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Serial Operation
(1) 3-wire serial I/O mode
tKCY1, 2
tKH1, 2
tKL1, 2
SCK
tKSO1, 2
tKSI1, 2
tSIK1, 2
SI/SO
(2) UART mode
tKCY3
tKH3
tKL3
ASCK
(3) I2C bus mode (µPD78F4216AY, 78F4218AY only)
tR
SCL0
tHD : DAT
tHD : STA
tHIGH
tSU : DAT
tF
tSU : STA
tHD : STA
tSP
tSU : STO
SDA0
tBUF
Stop
condition
42
Restart
condition
Start
condition
Data Sheet U14125EJ1V0DS00
Stop
condition
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Clock Output Timing
tCLH
tCLL
CLKOUT
tCLR
tCLF
tCYCL
Interrupt Input Timing
tWNIH
tWNIL
tWITH
tWITL
tWRSH
tWRSL
NMI
INTP0 to INTP6
Reset Input Timing
RESET
Data Sheet U14125EJ1V0DS00
43
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Clock Timing
tWXH
tWXL
X1
tXR
tXF
1/fX
tXTH
tXTL
XT1
1/fXT
Data Retention Characteristics
STOP mode setting
VDD
VDDDR
tHVD
tFVD
tRVD
RESET
NMI
(Cleared by falling edge)
NMI
(Cleared by rising edge)
44
Data Sheet U14125EJ1V0DS00
tDREL
tWAIT
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Flash Memory Programming Characteristics (VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V, VPP = 9.7
to 10.3 V)
(1) Basic characteristics
Parameter
Symbol
Operating frequency
fX
Note 1
Supply voltage
Conditions
MIN.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
2
12.5
MHz
2.7 V ≤ VDD < 4.5 V
2
6.25
MHz
2.0 V ≤ VDD < 2.7 V
2
3.125
MHz
1.9 V ≤ VDD < 2.0 V
2
2
MHz
1.9
5.5
V
0.2VDD
V
VDD
2
VPPL
Upon VPP low-level detection
0
VPP
Upon VPP high-level detection
0.9VDD
VDD
1.1VDD
V
VPPH
Upon VPP high-voltage detection
9.7
10
10.3
V
40
mA
100
mA
VDD supply current
IDD
VPP supply current
IPP
Write count
TYP.
VPP = 10 V
Note2
20
CWRT
Times
TA
−40
85
°C
Storage temperature
Tstg
−65
125
°C
Programming temperature
TPRG
10
40
°C
Note 3
Operating temperature
Note 4
Notes 1. µPD78F4216A, 78F4216AY
K standard: 2.7 V ≤ VDD < 5.5 V, VPP = 10.3 ±0.3 V
E standard: 2.7 V ≤ VDD < 5.5 V, VPP = 10.0 ±0.3 V
2. Operation cannot be guaranteed when the number of writes exceeds 20 times. In the case of the
µPD78F4216A and 78F4216AY with K standard, operation cannot be guaranteed when the number of
writes exceeds 5 times.
3. µPD78F4216A, 78F4216AY K standard: TA = −10 to +60°C
4. µPD78F4216A, 78F4216AY K standard: TA = −10 to +80°C
Cautions 1. If writing is not successful in write operation, execute the program command again, and
execute the verify command to confirm the normal completion of the write operation.
(µPD78F4216A, 78F4216AY: I, K, E, P standard)
2.
Handshake mode is supported by the following products.
µPD78F4216A, 78F4216AY: Other than I, K, E standard
µPD78F4218A, 78F4218AY: Other than I standard
Remark The fifth alphabetic character from the left in the lot number indicates the standard of the product. After
executing the program command, execute the verify command to confirm the normal completion of the
write operation.
Handshake mode is the CSI write mode that uses P24.
Data Sheet U14125EJ1V0DS00
45
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Flash Memory Programming Characteristics (VDD = AVDD = 1.9 to 5.5 V, VSS = AVSS = 0 V, VPP = 9.7
to 10.3 V)
(2) Serial write operation characteristics
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
VPP setup time
tPSRON
VPP high voltage
1.0
µs
VPP↑ setup time to VDD↑
tDRPSR
VPP high voltage
10
µs
RESET↑ set up time to VPP↑
tPSRRF
VPP high voltage
1.0
µs
VPP count start time from RESET↑
tRFCF
1.0
µs
Count execution time
tCOUNT
VPP counter high-level width
tCH
8.0
µs
VPP counter low-level width
tCL
8.0
µs
VPP counter noise elimination width
tNFW
1.0
40
Flash Memory Write Mode Setting Timing
VDD
VDD
0V
tDRPSR
tRFCF
tCH
VPPH
VPP
VPP
tCL
VPPL
tPSRON tPSRRF
tCOUNT
VDD
RESET (input)
0V
46
Data Sheet U14125EJ1V0DS00
ms
ns
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
8. PACKAGE DRAWINGS
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
A
B
75
76
51
50
detail of lead end
S
C D
Q
R
26
25
100
1
F
G
H
I
J
M
K
P
S
N
S
L
M
NOTE
Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
A
16.00±0.20
B
14.00±0.20
C
14.00±0.20
D
16.00±0.20
F
1.00
G
1.00
H
0.22 +0.05
−0.04
I
J
0.08
0.50 (T.P.)
K
1.00±0.20
L
0.50±0.20
M
0.17 +0.03
−0.07
N
0.08
P
1.40±0.05
Q
0.10±0.05
R
3° +7°
−3°
S
1.60 MAX.
S100GC-50-8EU, 8EA-2
Remark The external dimensions and material of the ES version are the same as those of the mass-produced
version.
Data Sheet U14125EJ1V0DS00
47
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
100-PIN PLASTIC QFP (14x20)
A
B
51
50
80
81
detail of lead end
S
C D
Q
R
31
30
100
1
F
G
J
H
I
M
P
K
S
N
S
L
M
NOTE
ITEM
Each lead centerline is located within 0.15 mm of
its true position (T.P.) at maximum material condition.
MILLIMETERS
A
23.6±0.4
B
20.0±0.2
C
14.0±0.2
D
17.6±0.4
F
0.8
G
H
0.6
0.30±0.10
I
0.15
J
K
L
0.65 (T.P.)
1.8±0.2
0.8±0.2
M
0.15+0.10
−0.05
N
0.10
P
2.7±0.1
Q
R
0.1±0.1
5°±5°
S
3.0 MAX.
P100GF-65-3BA1-4
Remark The external dimensions and material of the ES version are the same as those of the mass-produced
version.
48
Data Sheet U14125EJ1V0DS00
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
9. RECOMMENDED SOLDERING CONDITIONS
The µPD78F4218AY should be soldered and mounted under the following recommended conditions. For the
details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting
Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact your NEC sales
representative.
Table 9-1. Surface Mounting Type Soldering Conditions
(1) µPD78F4216AGC-8EU:100-pin plastic LQFP (fine pitch) (14 × 14)
µPD78F4218AGC-8EU:100-pin plastic LQFP (fine pitch) (14 × 14)
µPD78F4216AYGC-8EU:100-pin plastic LQFP (fine pitch) (14 × 14)
µPD78F4218AYGC-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14)
Soldering Method
Infrared reflow
Soldering Conditions
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Note
Count: Two times or less, Exposure limit: 7 days (after that, prebake at 125°C
Recommended
Condition Symbol
IR35-107-2
for 10 hours)
VPS
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
Note
Count: Two times or less, Exposure limit: 7 days (after that, prebake at 125°C
VP15-107-2
for 10 hours)
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
−
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution
Do not use different soldering methods together (except for partial heating).
(2) µPD78F4216AGF-3BA:100-pin plastic QFP (14 × 20)
µPD78F4218AGF-3BA:100-pin plastic QFP (14 × 20)
µPD78F4216AYGF-3BA:100-pin plastic QFP (14 × 20)
µPD78F4218AYGF-3BA: 100-pin plastic QFP (14 × 20)
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Count: Two times or less
IR35-00-2
VPS
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
Count: Two times or less
VP15-00-2
Wave soldering
Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once,
Preheating temperature: 120°C max. (package surface temperature)
WS60-00-1
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
Caution
−
Do not use different soldering methods together (except for partial heating).
Data Sheet U14125EJ1V0DS00
49
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the µPD78F4218AY. Also refer to
(5) Cautions on using development tools.
(1) Language processing software
RA78K4
Assembler package common to 78K/IV Series
CC78K4
C compiler package common to 78K/IV Series
DF784218
Device file common to µPD784216A, 784216AY, 784218A, 784218AY Subseries
CC78K4-L
C compiler library source file common to 78K/IV Series
(2) Flash memory writing tools
Flashpro II
(Part number: FL-PR2),
Flashpro III
(Part number: FL-PR3, PG-FP3)
Dedicated flash programmer for microcontroller incorporating flash memory
FA-100GF
Adapter for writing 100-pin plastic QFP (GF-3BA type) flash memory. Connection must be
performed in accordance with the target product.
FA-100GC
Adapter for writing 100-pin plastic LQFP (GC-8EU type) flash memory. Connection must be
performed in accordance with the target product.
(3) Debugging tools
• When IE-78K4-NS in-circuit emulator is used
IE-78K4-NS
In-circuit emulator common to 78K/IV Series
IE-70000-MC-PS-B
Power supply unit for IE-78K4-NS
IE-70000-98-IF-C
Interface adapter required when PC-9800 series PC (except notebook type) is used as host
machine (C bus supported)
IE-70000-CD-IF-A
PC card and cable when PC-9800 series notebook PC is used as host machine (PCMCIA
socket supported)
IE-70000-PC-IF-C
Interface adapter required when using IBM PC/AT
supported)
IE-70000-PCI-IF
Interface adapter required when using PC that incorporates PCI bus as host machine
IE-784225-NS-EM1
Emulation board to emulate µPD784216A, 784216AY, 784218A, 784218AY Subseries
NP-100GF
Emulation probe for 100-pin plastic QFP (GF-3BA type)
TM
compatibles as host machine (ISA bus
NP-100GC
Emulation probe for 100-pin plastic LQFP (GC-8EU type)
EV-9200GF-100
Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type)
TGC-100SDW
Conversion adapter to connect the NP-100GC and a target system board on which a 100-pin
plastic LQFP (GC-8EU type) can be mounted
ID78K4-NS
Integrated debugger for IE-78K4-NS
SM78K4
System simulator common to 78K/IV Series
DF784218
Device file common to µPD784216A, 784216AY, 784218A, 784218AY Subseries
50
Data Sheet U14125EJ1V0DS00
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
• When IE-784000-R in-circuit emulator is used
IE-784000-R
In-circuit emulator common to 78K/IV Series
IE-70000-98-IF-C
Interface adapter required when PC-9800 series PC (except notebook type) is used as host
machine (C bus supported)
IE-70000-PC-IF-C
Interface adapter required when using IBM PC/AT and compatibles as host machine (ISA bus
supported)
IE-70000-PCI-IF
Interface adapter required when using PC that incorporates PCI bus as host machine
IE-78000-R-SV3
Interface adapter and cable required when EWS is used as host machine
IE-784225-NS-EM1
Emulation board to emulate µPD784216A, 784216AY, 784218A, 784218AY Subseries
IE-784000-R-EM
Emulation board common to 78K/IV Series
IE-78K4-R-EX3
Emulation probe conversion board required when using IE-784225-NS-EM1 on IE-784000-R.
EP-784218GF-R
Emulation probe for 100-pin plastic QFP (GF-3BA type)
EP-78064GC-R
Emulation probe for 100-pin plastic LQFP (GC-8EU type)
EV-9200GF-100
Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type)
TGC-100SDW
Conversion adapter to connect the EP-78064GC-R and a target system board on which a
100-pin plastic LQFP (GC-8EU type) can be mounted
ID78K4
Integrated debugger for IE-784000-R
SM78K4
System simulator common to 78K/IV Series
DF784218
Device file common to µPD784216A, 784216AY, 784218A, 784218AY Subseries
(4) Real-time OS
RX78K/IV
Real-time OS for 78K/IV Series
MX78K4
OS for 78K/IV Series
Data Sheet U14125EJ1V0DS00
51
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
(5) Cautions on using development tools
• The ID78K4-NS, ID78K4, and SM78K4 are used in combination with the DF784218.
• The CC78K4 and RX78K/IV are used in combination with the RA78K4 and DF784218.
• The FL-PR2, FL-PR3, FA-100GF, FA-100GC, NP-100GF, and NP-100GC are products made by Naito
Densei Machida Mfg. Co., Ltd. (TEL: +81-44-822-3813).
• The TGC-100SDW is a product made by TOKYO ELETECH CORPORATION.
For further information, contact Daimaru Kogyo, Ltd.
Tokyo Electronic Division (TEL: +81-3-3820-7112)
Osaka Electronic Division (TEL: +81-6-6244-6672)
• For third party development tools, see the Single-Chip Microcontroller Development Tool Selection
Guide (U11069E).
• The host machine and OS suitable for each software are as follows:
Host Machine
PC
EWS
Software
PC-9800 series [Windows]
IBM PC/AT and compatibles
[Japanese/English Windows]
HP9000 Series 700 [HP-UX ]
TM
TM
TM
SPARCstation [SunOS , Solaris ]
TM
TM
NEWS (RISC) [NEWS-OS ]
RA78K4
√Note
√
Note
√
[OS]
CC78K4
√
TM
ID78K4-NS
√
−
ID78K4
√
√
√
−
SM78K4
RX78K/IV
MX78K4
Note
√
Note
√
√
√
Note DOS-based software
52
Data Sheet U14125EJ1V0DS00
TM
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
APPENDIX B. RELATED DOCUMENTS
Documents related to devices
Document Name
Document No.
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY,
784218AY Data Sheet
U14121E
µPD78F4216A, 78F4216AY, 78F4218A, 78F4218AY Data Sheet
This document
µPD784216A, 784216AY Subseries User’s Manual Hardware
U13570E
µPD784218A, 784218AY Subseries User’s Manual Hardware
U12970E
78K/IV Series User’s Manual Instructions
U10905E
78K/IV Series Instruction Table
−
78K/IV Series Instruction Set
−
78K/IV Series Application Note Software Basics
−
Documents related to development tools (user’s manuals)
Document Name
RA78K4 Assembler Package
Document No.
Language
U11162E
Operation
U11334E
RA78K Structured Assembler Preprocessor
U11743E
CC78K4 C Compiler
Language
U11571E
Operation
U11572E
IE-78K4-NS
U13356E
IE-784000-R
U12903E
IE-784218-R-EM1
U12155E
IE-784225-NS-EM1
U13742E
EP-78064
EEU-1469
SM78K4 System Simulator Windows Based
Reference
U10093E
SM78K Series System Simulator
External Part User Open
Interface Specifications
U10092E
ID78K4-NS Integrated Debugger PC Based
Reference
U12796E
ID78K4 Integrated Debugger Windows Based
Reference
U10440E
ID78K4 Integrated Debugger HP-UX, SunOS, NEWS-OS Based
Reference
U11960E
Caution
The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
Data Sheet U14125EJ1V0DS00
53
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Documents related to embedded software (user’s manuals)
Document Name
78K/IV Series Real-Time OS
78K/IV Series OS MX78K4
Document No.
Fundamental
U10603E
Installation
U10604E
Debugger
−
Fundamental
−
Other documents
Document Name
Document No.
SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM)
X13769X
Semiconductor Device Mounting Technology Manual
C10535E
Quality Grades on NEC Semiconductor Devices
C11531E
NEC Semiconductor Device Reliability/Quality Control System
C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
C11892E
Guide to Microcomputer-Related Products by Third Party
Caution
The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
54
−
Data Sheet U14125EJ1V0DS00
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
[MEMO]
Data Sheet U14125EJ1V0DS00
55
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
[MEMO]
56
Data Sheet U14125EJ1V0DS00
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
[MEMO]
Data Sheet U14125EJ1V0DS00
57
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
IEBus is a trademark of NEC Corporation.
Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or
other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
58
Data Sheet U14125EJ1V0DS00
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
Madrid Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860
United Square, Singapore
Tel: 65-253-8311
Fax: 65-250-3583
NEC Electronics Italiana s.r.l.
NEC Electronics (Germany) GmbH
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics (France) S.A.
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP Brasil
Tel: 55-11-6462-6810
Fax: 55-11-6462-6829
J00.7
Data Sheet U14125EJ1V0DS00
59
µPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
2
2
Purchase of NEC I C components conveys a license under the Philips I C Patent Rights to use these components
2
2
in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips.
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
• The information in this document is current as of August, 2000. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
• While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4