MC100EP139
Product Preview
÷2/4, ÷4/5/6
Clock
Generation Chip
The MC100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by
either a differential or single–ended ECL or, if positive power supplies
are used, LVPECL input signals. In addition, by using the VBB output,
a sinusoidal source can be AC coupled into the device. If a
single–ended input is to be used, the VBB output should be connected
to the CLK input and bypassed to ground via a 0.01µF capacitor.
The common enable (EN) is synchronous so that the internal
dividers will only be enabled/disabled when the internal clock is
already in the LOW state. This avoids any chance of generating a runt
clock pulse on the internal clock when the device is enabled/disabled
as can happen with an asynchronous control. The internal enable
flip–flop is clocked on the falling edge of the input clock, therefore, all
associated specification limits are referenced to the negative edge of
the clock input.
Upon startup, the internal flip–flops will attain a random state;
therefore, for systems which utilize multiple EP139s, the master reset
(MR) input must be asserted to ensure synchronization. For systems
which only use one EP139, the MR pin need not be exercised as the
internal divider design ensures synchronization between the ÷2/4 and
the ÷4/5/6 outputs of a single device. All VCC and VEE pins must be
externally connected to power supply to guarantee proper operation.
•
•
•
•
•
•
•
•
•
•
•
•
50ps Output–to–Output Skew
PECL mode: 3.0V to 5.5V VCC with VEE = 0V
ECL mode: 0V VCC with VEE = –3.0V to –5.5V
Synchronous Enable/Disable
Master Reset for Synchronization of Multiple Chips
Q Output will default LOW with inputs open or at VEE
ESD Protection: >2KV HBM, >100V MM
VBB Output
New Differential Input Common Mode Range
Moisture Sensitivity Level 2
For Additional Information, See Application Note AND8003/D
Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
Transistor Count = 758 devices
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TSSOP–20
DT SUFFIX
CASE 948E
SO–20
DW SUFFIX
CASE 751D
MARKING DIAGRAM
KEP
139
ALYW
A
L
Y
W
MC100EP139
AWLYWW
= Assembly Location
= Wafer Lot
= Year
= Work Week
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
Package
Shipping
MC100EP139DT
TSSOP
75 Units/Rail
MC100EP139DTR2
TSSOP
2500 Tape/Reel
MC100EP139DW
SOIC
38 Units/Rail
MC100EP139DWR2
SOIC
2500 Tape/Reel
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
Semiconductor Components Industries, LLC, 1999
December, 1999 – Rev. 1
1
Publication Order Number:
MC100EP139/D
Q0
Q1
Q1
Q2
Q2
Q3
Q3
VEE
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
VCC
EN
CLK
CLK
VBB
MR
VCC
DIVSELa
Q0
DIVSELb1
VCC
DIVSELb0
MC100EP139
Figure 1. 20–Lead SOIC (Top View)
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
FUNCTION TABLES
CLK
Z
ZZ
X
EN
MR
L
L
H
L
H
X
PIN DESCRIPTION
FUNCTION
Divide
Hold Q0:3
Reset Q0:3
Z = Low–to–High Transition
ZZ = High–to–Low Transition
DIVSELa
0
1
Q0:1 OUTPUTS
Divide by 2
Divide by 4
DIVSELb0 DIVSELb1
0
1
0
1
0
0
1
1
FUNCTION
PIN
CLK, CLK
ECL Diff Clock Inputs
EN
ECL Sync Enable
MR
ECL Master Reset
VBB
Q0, Q1, Q0, Q1
ECL Diff ÷2/4 Outputs
Q2, Q3, Q2, Q3
ECL Diff ÷4/5/6 Outputs
DIVSELa
ECL Freq. Select Input
DIVSELb0
ECL Freq. Select Input
DIVSELb1
Q2:3 OUTPUTS
VCC
VEE
Divide by 4
Divide by 6
Divide by 5
Divide by 5
ECL Reference Output
B2/4
B4/5/6
ECL Freq. Select Input B4/5/6
ECL Positive Supply
ECL Negative, 0 Supply
DIVSELa
Q0
CLK
÷2/4
CLK
R
Q0
Q1
Q1
Q2
EN
÷4/5/6
R
MR
DIVSELb0
DIVSELb1
Q2
Q3
Q3
Figure 2. Logic Diagram
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2
MC100EP139
CLK
Q (÷2)
Q (÷4)
Q (÷5)
Q (÷6)
Figure 3. Timing Diagram
CLK
tRR
RESET
Q (÷n)
Figure 4. Timing Diagram
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VEE
Power Supply (VCC = 0V)
–6.0 to 0
VDC
VCC
Power Supply (VEE = 0V)
6.0 to 0
VDC
VI
Input Voltage (VCC = 0V, VI not more negative than VEE)
–6.0 to 0
VDC
VI
Input Voltage (VEE = 0V, VI not more positive than VCC)
6.0 to 0
VDC
Iout
Output Current
50
100
mA
IBB
VBB Sink/Source Current{
± 0.5
mA
TA
Operating Temperature Range
–40 to +85
°C
Tstg
Storage Temperature
–65 to +150
°C
θJA (DT Suffix)
Thermal Resistance (Junction–to–Ambient)
140
100
°C/W
θJC (DT Suffix)
Thermal Resistance (Junction–to–Case)
23 to 41 ± 5%
°C/W
θJA (DW Suffix)
Thermal Resistance (Junction–to–Ambient)
90
60
°C/W
θJC (DW Suffix)
Thermal Resistance (Junction–to–Case)
33 to 35 ± 5%
°C/W
Tsol
Solder Temperature (<2 to 3 Seconds: 245°C desired)
265
°C
Continuous
Surge
Still Air
500lfpm
Still Air
500lfpm
* Maximum Ratings are those values beyond which damage to the device may occur.
{ Use for inputs of same package only.
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3
MC100EP139
DC CHARACTERISTICS, ECL/LVECL (VCC = 0V, VEE = –5.5V to –3.0V) (Note 3.)
–40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
(Note 1.)
70
85
100
70
90
105
75
95
110
mA
VOH
Output HIGH Voltage
(Note 2.)
–1250
–1100
–895
–1250
–1100
–895
–1250
–1100
–895
mV
VOL
Output LOW Voltage
(Note 2.)
–1995
–1850
–1650
–1995
–1850
–1650
–1995
–1850
–1650
mV
VIH
Input HIGH Voltage Single Ended
–1022
–1022
–1022
mV
VIL
Input LOW Voltage Single Ended
–1642
–1642
–1642
mV
IIH
Input HIGH Current
IIL
Input LOW Current
150
CLK
CLK
0.5
–150
150
0.5
–150
150
µA
µA
0.5
–150
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
1. VCC = 0V, VEE = VEEmin to VEEmax, all other pins floating.
2. All loading with 50 ohms to VCC –2.0 volts.
3. Input and output parameters vary 1:1 with VCC.
DC CHARACTERISTICS, LVPECL (VCC = 3.3V ± 0.3V, VEE = 0V) (Note 6.)
–40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
(Note 4.)
70
83
100
70
87
105
75
90
110
mA
VOH
Output HIGH Voltage
(Note 5.)
2050
2200
2405
2050
2200
2405
2050
2200
2405
mV
VOL
Output LOW Voltage
(Note 5.)
1305
1450
1650
1305
1450
1650
1305
1450
1650
mV
VIH
Input HIGH Voltage Single Ended
2277
2277
2277
mV
VIL
Input LOW Voltage Single Ended
1657
1657
1657
mV
IIH
Input HIGH Current
IIL
Input LOW Current
150
CLK
CLK
0.5
–150
150
0.5
–150
150
0.5
–150
µA
µA
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
4. VCC = 3.0V, VEE = 0V, all other pins floating.
5. All loading with 50 ohms to VCC –2.0 volts.
6. Input and output parameters vary 1:1 with VCC.
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4
MC100EP139
DC CHARACTERISTICS, PECL (VCC = 5.0V ± 0.5V, VEE = 0V) (Note 9.)
–40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
(Note 7.)
70
85
100
70
90
105
75
95
110
mA
VOH
Output HIGH Voltage
(Note 8.)
3750
3900
4105
3750
3900
4105
3750
3900
4105
mV
VOL
Output LOW Voltage
(Note 8.)
3005
3150
3350
3005
3150
3350
3005
3150
3350
mV
VIH
Input HIGH Voltage Single Ended
3977
3977
3977
mV
VIL
Input LOW Voltage Single Ended
3357
3357
3357
mV
IIH
Input HIGH Current
IIL
Input LOW Current
150
CLK
CLK
0.5
–150
150
0.5
–150
150
µA
µA
0.5
–150
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
7. VCC = 5.0V, VEE = 0V, all other pins floating.
8. All loading with 50 ohms to VCC –2.0 volts.
9. Input and output parameters vary 1:1 with VCC.
AC CHARACTERISTICS (VCC = 3.0V to 5.5V; VEE = 0V) or (VCC = 0V; VEE = –3.0V to –5.5V)
–40°C
Symbol
Characteristic
Min
Typ
fmax
Maximum Toggle
Frequency (Note 10.)
1.0
1.2
tPLH,
tPHL
Propagation Delay
550
700
tSKEW
Device Skew
Part–to–Part (Note 11.)
tJITTER
Cycle–to–Cycle Jitter
tr
tf
Output Rise and Fall Times
(20% – 80%)
ts
CLK, Q(DIFF)
CLK, Q(SE)
MR, Q
25°C
Max
800
Min
Typ
1.0
1.2
600
750
Q, Q
85°C
Max
900
Min
Typ
1.0
1.2
675
825
Q, Q
110
180
975
125
190
Setup Time
EN, CLK
DIVSEL, CLK
200
400
120
200
400
th
Hold Time
CLK, EN
CLK, DIVSEL
100
150
50
Vpp
Input Voltage Swing (Diff)
300
800
trr
Reset Recovery Time
tpw
Minimum Pulse Width
1200
TBD
275
450
215
120
200
400
120
ps
100
150
50
100
150
50
ps
300
800
300
800
550
450
10. Fmax guaranteed for functionality only. VOL and VOH levels are guaranteed at DC only.
11. Skew is measured between outputs under identical transitions.
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5
ps
150
1200
100
550
ps
ps
TBD
250
Unit
GHz
50
200
TBD
CLK
MR
Max
300
1200
ps
mV
ps
550
450
ps
MC100EP139
PACKAGE DIMENSIONS
TSSOP–20
DT SUFFIX
20 PIN PLASTIC TSSOP PACKAGE
CASE 948E–02
ISSUE A
20X
0.15 (0.006) T U
K REF
0.10 (0.004)
S
M
T U
S
V
S
K
K1
2X
20
L/2
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
11
B
L
J J1
–U–
PIN 1
IDENT
SECTION N–N
1
10
0.25 (0.010)
N
0.15 (0.006) T U
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE –W–.
M
A
–V–
N
F
DETAIL E
–W–
C
D
G
H
DETAIL E
0.100 (0.004)
–T– SEATING
PLANE
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6
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
–––
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
–––
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
MC100EP139
PACKAGE DIMENSIONS
SO–20
DW SUFFIX
20 PIN PLASTIC SOIC PACKAGE
CASE 751D–05
ISSUE F
q
A
20
X 45 _
h
1
10
20X
B
B
0.25
M
T A
S
B
S
A
L
H
M
E
0.25
10X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
11
B
M
D
18X
e
A1
SEATING
PLANE
DIM
A
A1
B
C
D
E
e
H
h
L
q
C
T
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7
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
MC100EP139
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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8
MC100EP139/D