ONSEMI SN74LS157D

SN74LS157
Quad 2-Input Multiplexer
The LSTTL / MSI SN74LS157 is a high speed Quad 2-Input
Multiplexer. Four bits of data from two sources can be selected using
the common Select and Enable inputs. The four buffered outputs
present the selected data in the true (non-inverted) form. The LS157
can also be used to generate any four of the 16 different functions of
two variables. The LS157 is fabricated with the Schottky barrier diode
process for high speed and is completely compatible with all
ON Semiconductor TTL families.
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LOW
POWER
SCHOTTKY
Schottky Process for High Speed
Multifunction Capability
Non-Inverting Outputs
Input Clamp Diodes Limit High Speed Termination Effects
Special Circuitry Ensures Glitch Free Multiplexing
ESD > 3500 Volts
GUARANTEED OPERATING RANGES
Symbol
VCC
Parameter
Supply Voltage
16
Min
Typ
Max
Unit
4.75
5.0
5.25
V
0
25
70
°C
TA
Operating Ambient
Temperature Range
IOH
Output Current – High
– 0.4
mA
IOL
Output Current – Low
8.0
mA
1
PLASTIC
N SUFFIX
CASE 648
16
1
SOIC
D SUFFIX
CASE 751B
ORDERING INFORMATION
 Semiconductor Components Industries, LLC, 1999
December, 1999 – Rev. 6
1
Device
Package
Shipping
SN74LS157N
16 Pin DIP
2000 Units/Box
SN74LS157D
16 Pin
2500/Tape & Reel
Publication Order Number:
SN74LS157/D
SN74LS157
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC
E
I0c
I1c
Zc
I0d
I1d
Zd
16
15
14
13
12
11
10
9
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
1
S
2
I0a
3
I1d
4
Za
5
I0b
6
I1b
7
Zb
8
GND
LOADING (Note a)
HIGH
LOW
1.0 U.L.
1.0 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
0.5 U.L.
0.5 U.L.
0.25 U.L.
0.25 U.L.
5 U.L.
PIN NAMES
S
E
I0a – I0d
I1a – I1d
Za – Zd
Common Select Input
Enable (Active LOW) Input
Data Inputs from Source 0
Data Inputs from Source 1
Multiplexer Outputs
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
LOGIC SYMBOL
15 2 3 5 6 14 13 11 10
E I0a I1a I0b I1b I0c I1c I0d I1d
1
S
Za
Zb
Zc
Zd
4
7
12
9
VCC = PIN 16
GND = PIN 8
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2
SN74LS157
LOGIC DIAGRAM
I0a
I1a
2
3
I0b
I1b
5
6
I0c
14
Za
I0d
13
Zb
I1d E S
11
10
12
7
4
I1c
1
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
9
Zc
15
Zd
FUNCTIONAL DESCRIPTION
The LS157 is a Quad 2-Input Multiplexer fabricated with
the Schottky barrier diode process for high speed. It selects
four bits of data from two sources under the control of a
common Select Input (S). The Enable Input (E) is active
LOW. When E is HIGH, all of the outputs (Z) are forced
LOW regardless of all other inputs.
The LS157 is the logic implementation of a 4-pole,
2-position switch where the position of the switch is
determined by the logic levels supplied to the Select Input.
The logic equations for the outputs are:
Za = E ⋅ (I1a ⋅ S + I0a ⋅ S)
Zb = E ⋅ (I1b ⋅ S + I0b ⋅ S)
Zc = E ⋅ (I1c ⋅ S + I0c ⋅ S)
Zd = E ⋅ (I1d ⋅ S + I0d ⋅ S)
A common use of the LS157 is the moving of data from
two groups of registers to four common output busses. The
particular register from which the data comes is determined
by the state of the Select Input. A less obvious use is as a
function generator. The LS157 can generate any four of the
16 different functions of two variables with one variable
common. This is useful for implementing highly irregular
logic.
TRUTH TABLE
ENABLE
SELECT
INPUT
E
S
I0
I1
Z
H
L
L
L
L
X
H
H
L
L
X
X
X
L
H
X
L
H
X
X
L
L
H
L
H
INPUTS
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
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3
OUTPUT
SN74LS157
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VIK
Input Clamp Diode Voltage
VOH
Output HIGH Voltage
VOL
O
Output LOW Voltage
IIH
Min
Typ
Unit
Max
2.0
0.8
– 0.65
2.7
– 1.5
3.5
Short Circuit Current (Note 1)
ICC
Power Supply Current
Guaranteed Input LOW Voltage for
All Inputs
V
VCC = MIN, IIN = – 18 mA
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
V
IOL = 4.0 mA
0.35
0.5
V
IOL = 8.0 mA
20
40
µA
VCC = MAX, VIN = 2.7 V
mA
VCC = MAX, VIN = 7.0 V
– 0.4
– 0.8
mA
VCC = MAX, VIN = 0.4 V
– 100
mA
VCC = MAX
16
mA
VCC = MAX
0.1
0.2
IOS
V
0.4
I0, I1
E, S
Input LOW Current
I0, I1
E, S
V
0.25
Input HIGH Current
I0, I1
E, S
IIL
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
– 20
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C)
Limits
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
tPLH
tPHL
Propagation Delay
Data to Output
9.0
9.0
14
14
ns
Figure 2
tPLH
tPHL
Propagation Delay
Enable to Output
13
14
20
21
ns
Figure 1
tPLH
tPHL
Propagation Delay
Select to Output
15
18
23
27
ns
Figure 2
VCC = 5.0 V
CL = 15 pF
AC WAVEFORMS
VIN
VOUT
1.3 V
1.3 V
VIN
tPHL
tPLH
1.3 V
1.3 V
VOUT
Figure 1.
1.3 V
tPHL
tPLH
1.3 V
1.3 V
Figure 2.
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1.3 V
SN74LS157
PACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
16
9
1
8
B
F
C
L
S
–T–
SEATING
PLANE
K
H
G
D
M
J
16 PL
0.25 (0.010)
M
T A
M
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DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
SN74LS157
PACKAGE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
16
9
1
8
–B–
P
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
8 PL
0.25 (0.010)
M
B
S
G
R
K
F
X 45 _
C
–T–
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
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DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
SN74LS157
Notes
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SN74LS157
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
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attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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SN74LS157/D