Philips Semiconductors Product specification PowerMOS transistor Clamped logic level FET BUK573-48C GENERAL DESCRIPTION QUICK REFERENCE DATA Protected N-channel enhancement mode logic level field-effect power transistor in a plastic full-pack envelope. The device is intended for use in automotive applications. It has built-in zener diodes providing active drain voltage clamping. SYMBOL PARAMETER V(CL)DSR ID Ptot WDSRR Drain-source clamp voltage Drain current (DC) Total power dissipation Repetitive clamped turn off energy; Tj = 150˚C Drain-source on-state resistance; VGS = 5 V PINNING - SOT186A PIN CONFIGURATION PIN RDS(ON) MIN. 40 TYP. MAX. UNIT 48 58 13 25 50 V A W mJ 85 mΩ SYMBOL DESCRIPTION d case 1 gate 2 drain 3 source case isolated g s 1 2 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS VDS VDG ±VGS ID ID IDM Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage temperature Junction Temperature Ptot Tstg Tj MIN. MAX. UNIT continuous continuous Ths = 25 ˚C Ths = 100 ˚C Ths = 25 ˚C - 30 30 15 13 8.2 52 V V V A A A Ths = 25 ˚C - - 55 - 55 25 150 150 W ˚C ˚C THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS Rth j-hs Thermal resistance junction to heatsink Thermal resistance junction to ambient with heatsink compound Rth j-a August 1994 1 MIN. TYP. MAX. UNIT - - 5 K/W - 55 - K/W Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Clamped logic level FET BUK573-48C STATIC CHARACTERISTICS Tj = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS V(BR)DG Drain-gate zener voltage VGS(TO) VGS(ON) Gate threshold voltage Gate voltage IDSS IGSS RDS(ON) Zero gate voltage drain current Gate source leakage current Drain-source on-state resistance 0.2 < -IG < 0.4 mA; -55˚C < Tj < 150˚C VDS = VGS; ID = 1 mA VDS = 10 V; ID = 10 A; -55˚C < Tj < 150˚C VDS = 30 V; VGS = 0 V; Tj =150 ˚C VGS = ±15 V; VDS = 0 V; Tj =150 ˚C VGS = 5 V; ID = 10 A MIN. TYP. MAX. UNIT 38 45 54 V 1.0 2.0 1.5 3.1 2.0 4.0 V V - 0.01 0.1 65 1.0 10 85 mA µA mΩ MIN. TYP. MAX. UNIT DYNAMIC CHARACTERISTICS Tj = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS V(CL)DSR Drain source clamp voltage (peak value) RG = 10 kΩ; ID = 10 A; -55 < Tj < 150˚C; Inductive load. 40 48 58 V gfs Forward transconductance VDS = 25 V; ID = 10 A 7 12 - S Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 550 240 100 825 350 160 pF pF pF td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 12 V; ID = 5 A; VGS = 5 V; RG = 10 kΩ; - 3.5 22 16 18 - µs µs µs µs Ld Internal drain inductance - 4.5 - nH Ls Internal source inductance Measured from drain lead 6 mm from package to centre of die Measured from source lead 6 mm from package to source bond pad - 7.5 - nH MIN. TYP. MAX. UNIT ISOLATION Tj = 25 ˚C unless otherwise specified SYMBOL PARAMETER Visol(rms) R.M.S. isolation voltage from all f = 50-60 Hz; sinusoidal waveform; three terminals to external R.H. < 65 %; clean and dust free heatsink - - 2500 VRMS Cisol Capacitance from T2 to external heatsink - 10 - pF August 1994 CONDITIONS f = 1 MHz 2 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Clamped logic level FET BUK573-48C REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS IDR Continuous reverse drain current Pulsed reverse drain current Diode forward voltage IDRM VSD MIN. TYP. MAX. UNIT - - - 13 A IF = 13 A ; VGS = 0 V - 1.05 52 1.3 A V CLAMPED ENERGY LIMITING VALUE SYMBOL PARAMETER CONDITIONS WDSRS Drain-source non repetitive clamped inductive turn off energy WDSRR 120 MIN. MAX. UNIT Tj = 25˚C prior to clamping; ID = 10 A; VGS = 5 V; RGS = 10 kΩ; inductive load (see Figs. 17,18) - 200 mJ Drain-source repetitive clamped Tj = 150˚C prior to clamping; inductive turn off energy ID = 10 A; VGS = 5 V; RGS = 10 kΩ; inductive load (see Figs. 17,18) - 50 mJ Normalised Power Derating PD% 120 with heatsink compound 110 Normalised Current Derating ID% with heatsink compound 110 100 90 100 90 80 70 80 70 60 60 50 50 40 40 30 30 20 20 10 10 0 0 20 40 60 80 Ths / C 100 120 0 140 0 Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Ths) August 1994 20 40 60 80 Ths / C 100 120 140 Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Ths); conditions: VGS ≥ 5 V 3 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Clamped logic level FET 100 BUK573-48C BUK573-48C tp = ID / A ID S/ = N) VD 1E+01 10 us 100 us O S( 0.5 RD 10 0.2 1E+00 1 ms 0.1 0.05 10 ms DC 1 ZTHX43 Zth j-hs / (K/W) 100 ms 0.02 1E-01 PD Self-clamped 0 1E-02 1E-07 0.1 1 100 10 VDS / V Fig.3. Safe operating area. Ths = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp ID / A 40 tp D= t T 1E-05 1E-03 t/s tp T 1E-01 1E+01 Fig.6. Transient thermal impedance. Zth j-hs = f(t); parameter D = tp/T BUK5Y3-48C 40 VGS / V = 5 ID / A BUK5Y3-48C 10 4.5 30 30 4 20 20 3.5 3 10 10 Tmb / degC = 150 25 -55 2.5 0 0 2 4 6 8 0 10 0 1 2 VDS / V Fig.4. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VGS 0.5 2.5 3 3.5 5 6 7 Fig.7. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V. BUK5Y3-48C RDS(ON) / Ohm 3 4 VGS / V 20 gfs / S BUK5Y3-48C VGS / V = 4 0.4 15 4.5 0.3 5 10 0.2 5 0.1 0 Tmb / degC = 150 25 -55 10 0 10 20 VDS / V 30 0 40 Fig.5. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID); parameter VGS August 1994 0 10 20 Id / A 30 40 Fig.8. Typical transconductance. gfs = f(ID); conditions: VDS = 25 V 4 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Clamped logic level FET 51 BUK573-48C V(CL)DSR / V BUK5Y3-48C 58 50 V(CL)DSR / V BUK5Y3-48C Tmb / degC = 150 25 -55 56 49 54 48 52 47 50 46 Tmb / degC = 45 44 43 48 150 25 -55 0 2 4 6 ID / A 8 46 10 44 12 1 Fig.9. Typical clamping voltage V(CL)DSR = f(ID) ; conditions: RG = 10 kΩ a 2 10 5 RG / kOhm 20 Fig.12. Typical clamping voltgage V(CL)DSR = f(RG) ; conditions: ID = 10 A. VGS(TO) / V Normalised RDS(ON) = f(Tj) max. 2 1.5 typ. 1.0 min. 1 0.5 0 0 -60 -40 -20 0 20 40 60 Tj / C 80 -60 100 120 140 Fig.10. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 10 A; VGS = 5 V 40 IS / A -40 -20 0 20 40 60 Tj / C 80 100 120 140 Fig.13. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS BUK5Y3-48C 1E-01 SUB-THRESHOLD CONDUCTION ID / A Tmb / degC = 150 25 -55 30 1E-02 2% 1E-03 98 % typ 20 1E-04 10 0 1E-05 1E-06 0 0.5 VSDS / V 1 0 1.5 Fig.11. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj August 1994 0.4 0.8 1.2 VGS / V 1.6 2 2.4 Fig.14. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS 5 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Clamped logic level FET 2000 BUK573-48C C / pF BUK5Y3-48C VDD Load 1000 t p : adjust for correct Ic 500 Ciss 200 Coss D.U.T. RG VGE 100 Crss Id measure 50 0.01 0.1 1 VDS / V 10 0V 100 0R1 Fig.17. Inductive clamping test circuit. Fig.15. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz 7 VGS / V I,V BUK5Y3-48C V(CL)DSR VDD / V = 12 30 6 5V 5 ID VDS VGS 4 t 3 P,E PDS = ID x VDS 2 E = PDS dt 1 0 WDSR 0 5 10 QG / nC 15 20 t Fig.16. Typical turn-on gate-charge characteristics. VGS = f(QG); conditions: ID = 10 A. August 1994 Fig.18. Typical Inductive Clamping waveforms 6 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Clamped logic level FET BUK573-48C MECHANICAL DATA Dimensions in mm Net Mass: 2 g 10.3 max 4.6 max 3.2 3.0 2.9 max 2.8 Recesses (2x) 2.5 0.8 max. depth 6.4 15.8 19 max. max. 15.8 max seating plane 3 max. not tinned 3 2.5 13.5 min. 1 0.4 2 3 M 1.0 (2x) 0.6 2.54 0.9 0.7 0.5 2.5 5.08 1.3 Fig.19. SOT186A; The seating plane is electrically isolated from all terminals. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for F-pack envelopes. 3. Epoxy meets UL94 V0 at 1/8". August 1994 7 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Clamped logic level FET BUK573-48C DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1996 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. August 1994 8 Rev 1.000 Error Log 573-48.C 1) Level: Warning Message: Picture is too large; will be automatically scaled Location: Document Body: [PICTURE] Page: 6 Distance from TOF: 6.47cm Level: 1 Section: 25 Block: Headline Column: 1 Page E1 96-11-11 04:08 pm